From patchwork Fri Feb 7 03:26:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bibo mao X-Patchwork-Id: 13964283 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 92DF31552F5; Fri, 7 Feb 2025 03:26:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738898806; cv=none; b=TaQA6G5S6syj8XvPGUyscCYB5niC+KVL9oL0wh8+T1oJ0kY5iCX4RusmuoS7HriLwX4KYUg/vOJ1D8NlwF+vtk7RZrpNVr9giqPRvQ14qdeaML89WyQYIsWUR5tqJ5Eh+QdKttTpK7sO+k9G0HG1Sk8KbQKWMjsVnjtOV/xgcoM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738898806; c=relaxed/simple; bh=nIg4KqlZLIE+9kHuoz8kq6iBTemjja4ssO61UhjLxdI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AO+O5hVvL35d4X1oLSMWu1J0YcJu5XwpjiTGVGCy2HsLvp/HqmTTBps3t1SOMqaaRthZvfGFfQ4OztS6OIW/rel7Qrl84KwApVAPvvnD6oeR8RlbctahAi67jJnpajiyJUbeV2lKid5el9OwPD0t/W0daNAWwheHU+ZvrmLiNlo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Ax3eJrfaVnOjFuAA--.22411S3; Fri, 07 Feb 2025 11:26:35 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMDx_MRqfaVn0JsDAA--.12326S3; Fri, 07 Feb 2025 11:26:34 +0800 (CST) From: Bibo Mao To: Tianrui Zhao Cc: Huacai Chen , WANG Xuerui , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] LoongArch: KVM: Fix typo issue about GCFG feature detection Date: Fri, 7 Feb 2025 11:26:32 +0800 Message-Id: <20250207032634.2333300-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250207032634.2333300-1-maobibo@loongson.cn> References: <20250207032634.2333300-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: qMiowMDx_MRqfaVn0JsDAA--.12326S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== This is typo issue about GCFG feature macro, comments is added for these macro and typo issue is fixed here. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/loongarch.h | 26 ++++++++++++++++++++++++++ arch/loongarch/kvm/main.c | 4 ++-- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h index 52651aa0e583..1a65b5a7d54a 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -502,49 +502,75 @@ #define LOONGARCH_CSR_GCFG 0x51 /* Guest config */ #define CSR_GCFG_GPERF_SHIFT 24 #define CSR_GCFG_GPERF_WIDTH 3 +/* Number PMU register started from PM0 passthrough to VM */ #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT) +#define CSR_GCFG_GPERFP_SHIFT 23 +/* Read-only bit: show PMU passthrough supported or not */ +#define CSR_GCFG_GPERFP (_ULCAST_(0x1) << CSR_GCFG_GPERFP_SHIFT) #define CSR_GCFG_GCI_SHIFT 20 #define CSR_GCFG_GCI_WIDTH 2 #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT) +/* All cacheop instructions will trap to host */ #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT) +/* Cacheop instruction except hit invalidate will trap to host */ #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT) +/* Cacheop instruction except hit and index invalidate will trap to host */ #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT) #define CSR_GCFG_GCIP_SHIFT 16 #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT) +/* Read-only bit: show feature CSR_GCFG_GCI_ALL supported or not */ #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT) +/* Read-only bit: show feature CSR_GCFG_GCI_HIT supported or not */ #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1)) +/* Read-only bit: show feature CSR_GCFG_GCI_SECURE supported or not */ #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2)) #define CSR_GCFG_TORU_SHIFT 15 +/* Operation with CSR register unimplemented will trap to host */ #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT) #define CSR_GCFG_TORUP_SHIFT 14 +/* Read-only bit: show feature CSR_GCFG_TORU supported or not */ #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT) #define CSR_GCFG_TOP_SHIFT 13 +/* Modificattion with CRMD.PLV will trap to host */ #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT) #define CSR_GCFG_TOPP_SHIFT 12 +/* Read-only bit: show feature CSR_GCFG_TOP supported or not */ #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT) #define CSR_GCFG_TOE_SHIFT 11 +/* ertn instruction will trap to host */ #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT) #define CSR_GCFG_TOEP_SHIFT 10 +/* Read-only bit: show feature CSR_GCFG_TOE supported or not */ #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT) #define CSR_GCFG_TIT_SHIFT 9 +/* Timer instruction such as rdtime/TCFG/TVAL will trap to host */ #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT) #define CSR_GCFG_TITP_SHIFT 8 +/* Read-only bit: show feature CSR_GCFG_TIT supported or not */ #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT) #define CSR_GCFG_SIT_SHIFT 7 +/* All privilege instruction will trap to host */ #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT) #define CSR_GCFG_SITP_SHIFT 6 +/* Read-only bit: show feature CSR_GCFG_SIT supported or not */ #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT) #define CSR_GCFG_MATC_SHITF 4 #define CSR_GCFG_MATC_WIDTH 2 #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF) +/* Cache attribute comes from GVA->GPA mapping */ #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF) +/* Cache attribute comes from GPA->HPA mapping */ #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF) +/* Cache attribute comes from weaker one of GVA->GPA and GPA->HPA mapping */ #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF) #define CSR_GCFG_MATP_NEST_SHIFT 2 +/* Read-only bit: show feature CSR_GCFG_MATC_NEST supported or not */ #define CSR_GCFG_MATP_NEST (_ULCAST_(0x1) << CSR_GCFG_MATP_NEST_SHIFT) #define CSR_GCFG_MATP_ROOT_SHIFT 1 +/* Read-only bit: show feature CSR_GCFG_MATC_ROOT supported or not */ #define CSR_GCFG_MATP_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATP_ROOT_SHIFT) #define CSR_GCFG_MATP_GUEST_SHIFT 0 +/* Read-only bit: show feature CSR_GCFG_MATC_GUEST suppoorted or not */ #define CSR_GCFG_MATP_GUEST (_ULCAST_(0x1) << CSR_GCFG_MATP_GUEST_SHIFT) #define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */ diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c index bf9268bf26d5..f6d3242b9234 100644 --- a/arch/loongarch/kvm/main.c +++ b/arch/loongarch/kvm/main.c @@ -303,9 +303,9 @@ int kvm_arch_enable_virtualization_cpu(void) * TOE=0: Trap on Exception. * TIT=0: Trap on Timer. */ - if (env & CSR_GCFG_GCIP_ALL) + if (env & CSR_GCFG_GCIP_SECURE) gcfg |= CSR_GCFG_GCI_SECURE; - if (env & CSR_GCFG_MATC_ROOT) + if (env & CSR_GCFG_MATP_ROOT) gcfg |= CSR_GCFG_MATC_ROOT; write_csr_gcfg(gcfg); From patchwork Fri Feb 7 03:26:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bibo mao X-Patchwork-Id: 13964285 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 985EE17AE1D; Fri, 7 Feb 2025 03:26:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738898806; cv=none; b=P9Bt5O6aE0Z6ftiYLE9GUAXh2iNsUtpmbs7qrbJV4xVGjeILv8glmi7A543ZuqvjqexaPQ1e7gOjHjfWnTGOXimvbwc2P9qVgFUXOCOWizlg7ehQ5yYTKc6/Q6ZH7Fyzr7hLQ0WcJk46E7UihEmQ7A+7ckB2p5pAWFdSo2O63Ro= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738898806; c=relaxed/simple; bh=02FGwJ1b4L+Qmh0mt8jK4ZSLOxYlbCsmrNC1feJZQn4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Mo5RkZo2QDjq8oZhwKwnx4TzpVsRsjfw21dsZw2XoVnILVnSBTxEbqqdiwdKFoKug9mo7hE4mdT5EsZRajooz7PHFHpKezMz4Xk0qXvF8un+Uw0vA/TmJFGnJIJfgPtqDPTDRCIBi8Y99hd5DQ2nErwc/zqLVf6/rv4wUk7+KK4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dxfa9rfaVnPjFuAA--.59786S3; Fri, 07 Feb 2025 11:26:35 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMDx_MRqfaVn0JsDAA--.12326S4; Fri, 07 Feb 2025 11:26:35 +0800 (CST) From: Bibo Mao To: Tianrui Zhao Cc: Huacai Chen , WANG Xuerui , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] LoongArch: KVM: Remove duplicated cache attribute setting Date: Fri, 7 Feb 2025 11:26:33 +0800 Message-Id: <20250207032634.2333300-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250207032634.2333300-1-maobibo@loongson.cn> References: <20250207032634.2333300-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: qMiowMDx_MRqfaVn0JsDAA--.12326S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Cache attribute comes from GPA->HPA secondary mmu page table and is configured when kvm is enabled. It is the same for all VMs, remove duplicated cache attribute setting on vCPU context switch. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/vcpu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index fb72095c8077..20f941af3e9e 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -1548,9 +1548,6 @@ static int _kvm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) /* Restore timer state regardless */ kvm_restore_timer(vcpu); - - /* Control guest page CCA attribute */ - change_csr_gcfg(CSR_GCFG_MATC_MASK, CSR_GCFG_MATC_ROOT); kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); /* Restore hardware PMU CSRs */ From patchwork Fri Feb 7 03:26:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bibo mao X-Patchwork-Id: 13964284 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DD2C217BB16; Fri, 7 Feb 2025 03:26:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738898806; cv=none; b=SAoyqAhpYVNqpBdXK9J/C5CEDZ6okh1eW5Mxb5yaCNzouGuOeuU3PIpcwKps93k1+za2g0haNsWAgm0bP9kRZQBiD7NB6IU48JkyNlENdcOz3uQWzOndMNsHcaxrvurpM3i1C8GhJBRuzqhgQ+mpqnHDsE9ejU+oRbGqQO744Yc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738898806; c=relaxed/simple; bh=uAACmwfTwi1FpXNOSvbzbkrI3utd3c8GcS6yWKXUNI0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mjsx69c+huLlqn+2vKkBdeTxXzxOFO0frHuEM9t1NMGvhhOlwdfKTO53wKWAYJS5Ft7TuLVqRCVbNHtZQz0EV5q+7JUhXWkoGMWimtBBm+ZcUx0r3rQKNMuo8K1bR/AOCRqhOAZVYSSrnAuTyAr+YteykRYqOvNcw6NKaRSMdnY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxieBtfaVnRDFuAA--.17414S3; Fri, 07 Feb 2025 11:26:37 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMDx_MRqfaVn0JsDAA--.12326S5; Fri, 07 Feb 2025 11:26:35 +0800 (CST) From: Bibo Mao To: Tianrui Zhao Cc: Huacai Chen , WANG Xuerui , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] LoongArch: KVM: Set host with kernel mode when switch to VM mode Date: Fri, 7 Feb 2025 11:26:34 +0800 Message-Id: <20250207032634.2333300-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250207032634.2333300-1-maobibo@loongson.cn> References: <20250207032634.2333300-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: qMiowMDx_MRqfaVn0JsDAA--.12326S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== PRMD and ERA register is only meaningful on the beginning stage of exception entry, and it can be overwritten for nested irq or exception. When CPU runs in VM mode, interrupt need be enabled on host. And the mode for host had better be kernel mode rather than random. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/switch.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S index 0c292f818492..1be185e94807 100644 --- a/arch/loongarch/kvm/switch.S +++ b/arch/loongarch/kvm/switch.S @@ -85,7 +85,7 @@ * Guest CRMD comes from separate GCSR_CRMD register */ ori t0, zero, CSR_PRMD_PIE - csrxchg t0, t0, LOONGARCH_CSR_PRMD + csrwr t0, LOONGARCH_CSR_PRMD /* Set PVM bit to setup ertn to guest context */ ori t0, zero, CSR_GSTAT_PVM