From patchwork Fri Feb 7 11:36:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13964851 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B357B2417ED; Fri, 7 Feb 2025 11:37:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928228; cv=none; b=uzkYIo4YWPrkOcUpvVv4nC6xfSc4OASux82+jkYt0vq9PwKWoMH5mXo+wtiKcXfsxwiSM+mXt0MkrECZ0Bq73xUnvXg1F5r0h7IgIY7jEWvOxt5BR7rHQktmmCP9WL+RF8WMWE2KhX2jMWB4kJpAI/qVRpikWRaI+/CZPFKyh3Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928228; c=relaxed/simple; bh=fVPMZGOrJVn+DUwrOh5n/qPz+bDJEOMm9YX7+NBtgS0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=crTK4Rn8dTrVeUN06NJXqnhWKvpnTpSYUUpVvEgjK/pCl7go4FEzKSyMvXkuUmCyJJ5GwlFiw3BWLt6ykyS8M9dUkUh/DmCwrXywysaGxA7dQbbdEigbIPyvgcu0yrBh3VtdD/YFNrCEiQxJHq4vWHtpJvGG3gwkfJxRRmIuQAk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 49oBAxSiSWSlCdzdeUSRkg== X-CSE-MsgGUID: +NvCL0HaToupsZkEJbsrTw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 07 Feb 2025 20:37:04 +0900 Received: from localhost.localdomain (unknown [10.226.93.6]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 82E424018324; Fri, 7 Feb 2025 20:37:00 +0900 (JST) From: Biju Das To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , Fabrizio Castro , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v4 01/12] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC Date: Fri, 7 Feb 2025 11:36:33 +0000 Message-ID: <20250207113653.21641-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> References: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences: - The TINT register base offset is 0x800 instead of zero. - The number of supported GPIO interrupts for TINT selection is 141 instead of 86. - The pin index and TINT selection index are not in the 1:1 map - The number of TSSR registers is 16 instead of 8 - Each TSSR register can program 2 TINTs instead of 4 TINTs Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E SoC. Acked-by: Rob Herring (Arm) Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v3->v4: * Updated typo in commit description offset->base offset. * Update typo 15->16 for the number of TSSR registers in RZ/G3E * Collected tags. v2->v3: * No change. v1->v2: * Collected tags. --- .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml index d7ef4f1323a7..3f99c8645767 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Interrupt Control Unit +title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit maintainers: - Fabrizio Castro @@ -20,7 +20,9 @@ description: properties: compatible: - const: renesas,r9a09g057-icu # RZ/V2H(P) + enum: + - renesas,r9a09g047-icu # RZ/G3E + - renesas,r9a09g057-icu # RZ/V2H(P) '#interrupt-cells': description: The first cell is the SPI number of the NMI or the From patchwork Fri Feb 7 11:36:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13964852 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 92E481A2C0E for ; Fri, 7 Feb 2025 11:37:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928229; cv=none; b=OwjwXRuS90s1jXNrwmBQv3C9J5TW19dIL//kwImCqqL9SvQ6HggUdDsZf+Xm4igDB5Do+sa6K0usTWwpKHbv1wSDPsHnmxUTgnv8/mSZwFA0tnLSyP1+y4yeANmkXkhdDThUosviGyz+jXGdHODay06lEiEXl4ovXKkcr7Q489U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928229; c=relaxed/simple; bh=yJBP9El5Kf8vUVZGo/RzhfrAG0vU+1B7lFIBPsJ8XvU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ylcan1rWlf+nHNJ0uZZGvgj+EFz7/UZj+qggev3oo4MZLKpabheLuv77ClaF4j4qRMn8TJp4X1dunhV5hMXJ50ZZ3myHtxtXXPImz+RWZcKOC39ZCcP19osU/hqjRTkku32IwjeyMOUYeYm11Ij6VxW4OOAlYVq+Phu2jyWqp7w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: iuP5/TlSRGOMOy7V8igNHA== X-CSE-MsgGUID: 4WqaKqV0RM+SujLA5CSeyg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 07 Feb 2025 20:37:07 +0900 Received: from localhost.localdomain (unknown [10.226.93.6]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id D8CAD4018328; Fri, 7 Feb 2025 20:37:04 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Tommaso Merciai Subject: [PATCH v4 02/12] irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv Date: Fri, 7 Feb 2025 11:36:34 +0000 Message-ID: <20250207113653.21641-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> References: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use rzv2h_icu_chip directly on irq_domain_set_hwirq_and_chip() and drop the global variable irqchip from struct rzv2h_icu_priv. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v3->v4: * Collected tag from Geert. v2->v3: * No change. v1->v2: * Collected tags. --- drivers/irqchip/irq-renesas-rzv2h.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index fe2d29e91026..fd432b43506b 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -83,13 +83,11 @@ /** * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure. * @base: Controller's base address - * @irqchip: Pointer to struct irq_chip * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers */ struct rzv2h_icu_priv { void __iomem *base; - const struct irq_chip *irqchip; struct irq_fwspec fwspec[ICU_NUM_IRQ]; raw_spinlock_t lock; }; @@ -390,7 +388,7 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, unsigne if (hwirq > (ICU_NUM_IRQ - 1)) return -EINVAL; - ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip, + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzv2h_icu_chip, (void *)(uintptr_t)tint); if (ret) return ret; @@ -446,8 +444,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) goto put_dev; } - rzv2h_icu_data->irqchip = &rzv2h_icu_chip; - rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); if (IS_ERR(rzv2h_icu_data->base)) { ret = PTR_ERR(rzv2h_icu_data->base); From patchwork Fri Feb 7 11:36:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13964853 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 511961A2C0E for ; Fri, 7 Feb 2025 11:37:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928232; cv=none; b=LsO+7MSwOMgxUlViXG9XcdI2RpCx/nmDDm4+tUGNZ1gSJQA3Z0mfgYAflSsS/VJ3Jgyj++vzf+n2OLZRDxL9S2YTz1mABEsH9EacQEjS3JV3vgsnMFNu7V68GjwARlR4XdeZ8ZHkryTpIZmQMQQZxRmQabiIoHNoTUXeNpFk5DU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928232; c=relaxed/simple; bh=0ojGATkfD8X3BAs+N0zeXSILTGGkWleCPcqL87tO+FA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lQHkXNZDuGlQleT2asPdZ7j/p5xqIlSobnw0Qjpp9W5+r15a8W41aKcBHCuwHRotugNkkSQKV36d5ZhkKP/yltyzSEnOqoNasUinQNvl1+Oj3Foq78ZCEt6eai2/6iC9FIdE/aVsBC0DONXvbRSSGBbV+X6FFYUu1T2tGJxr19A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: jaQ/nz6+Rjmfoxf8Zuh02Q== X-CSE-MsgGUID: lEB6/vpCTnyPbvIU4hzYnQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 07 Feb 2025 20:37:10 +0900 Received: from localhost.localdomain (unknown [10.226.93.6]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id DAE99400F31D; Fri, 7 Feb 2025 20:37:07 +0900 (JST) From: Biju Das To: Thomas Gleixner , Philipp Zabel Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 03/12] irqchip/renesas-rzv2h: Simplify rzv2h_icu_init() Date: Fri, 7 Feb 2025 11:36:35 +0000 Message-ID: <20250207113653.21641-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> References: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use devm_add_action_or_reset() for calling put_device in error path of rzv2h_icu_init() to simplify the code by using recently added devm_* helpers. Reviewed-by: Geert Uytterhoeven Reviewed-by: Philipp Zabel Signed-off-by: Biju Das --- v3->v4: * Collected the tags. v3: * New patch --- drivers/irqchip/irq-renesas-rzv2h.c | 37 +++++++++++++++-------------- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index fd432b43506b..fd678947df83 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -419,6 +419,11 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv *priv, struct device return 0; } +static void rzv2h_icu_put_device(void *data) +{ + put_device(data); +} + static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) { struct irq_domain *irq_domain, *parent_domain; @@ -431,41 +436,39 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) if (!pdev) return -ENODEV; + ret = devm_add_action_or_reset(&pdev->dev, rzv2h_icu_put_device, + &pdev->dev); + if (ret < 0) + return ret; + parent_domain = irq_find_host(parent); if (!parent_domain) { dev_err(&pdev->dev, "cannot find parent domain\n"); - ret = -ENODEV; - goto put_dev; + return -ENODEV; } rzv2h_icu_data = devm_kzalloc(&pdev->dev, sizeof(*rzv2h_icu_data), GFP_KERNEL); - if (!rzv2h_icu_data) { - ret = -ENOMEM; - goto put_dev; - } + if (!rzv2h_icu_data) + return -ENOMEM; rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); - if (IS_ERR(rzv2h_icu_data->base)) { - ret = PTR_ERR(rzv2h_icu_data->base); - goto put_dev; - } + if (IS_ERR(rzv2h_icu_data->base)) + return PTR_ERR(rzv2h_icu_data->base); ret = rzv2h_icu_parse_interrupts(rzv2h_icu_data, node); if (ret) { dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); - goto put_dev; + return ret; } resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL); - if (IS_ERR(resetn)) { - ret = PTR_ERR(resetn); - goto put_dev; - } + if (IS_ERR(resetn)) + return PTR_ERR(resetn); ret = reset_control_deassert(resetn); if (ret) { dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret); - goto put_dev; + return ret; } pm_runtime_enable(&pdev->dev); @@ -496,8 +499,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) pm_disable: pm_runtime_disable(&pdev->dev); reset_control_assert(resetn); -put_dev: - put_device(&pdev->dev); return ret; } From patchwork Fri Feb 7 11:36:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13964854 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4BDBC1A2C0E for ; Fri, 7 Feb 2025 11:37:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928234; cv=none; b=HvKaWpOUGpkGh3kBejdT6MVOIsKSiPFweGbXRl+jxf58+Dh/6JTlDX5ReaLDn4eMpzbDpIGvlqG7guHE8ziSihvQXaxvj4Cd1XlZlWqBwNuXP8KGrs/18Q9C8AZAX8XDQ4p2OoKqLNwZ7PeIzP5WqSAX6awWbu3oTAYPghO7ngM= ARC-Message-Signature: i=1; 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Fri, 7 Feb 2025 20:37:10 +0900 (JST) From: Biju Das To: Thomas Gleixner , Philipp Zabel Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, Tommaso Merciai Subject: [PATCH v4 04/12] irqchip/renesas-rzv2h: Use devm_reset_control_get_exclusive_deasserted() Date: Fri, 7 Feb 2025 11:36:36 +0000 Message-ID: <20250207113653.21641-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> References: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use devm_reset_control_get_exclusive_deasserted() to simplify rzv2h_icu_init(). Reviewed-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Reviewed-by: Philipp Zabel Signed-off-by: Biju Das --- v3->v4: * Collected tags. v2->v3: * Replaced 'goto put_dev' by 'return xxx' as put_device() called by devm_add_action_or_reset(). v1->v2: * Split the simplification patch into two. * Updated commit header and description. * Replaced devm_reset_control_get_optional_exclusive_deasserted()-> devm_reset_control_get_exclusive_deasserted(). * Moved simplification using devm_pm_runtime_enable() to next patch. --- drivers/irqchip/irq-renesas-rzv2h.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index fd678947df83..95df8e0755e3 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -461,13 +461,10 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) return ret; } - resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL); - if (IS_ERR(resetn)) - return PTR_ERR(resetn); - - ret = reset_control_deassert(resetn); - if (ret) { - dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret); + resetn = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL); + if (IS_ERR(resetn)) { + ret = PTR_ERR(resetn); + dev_err(&pdev->dev, "failed to acquire deasserted reset: %d\n", ret); return ret; } @@ -498,7 +495,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) pm_runtime_put(&pdev->dev); pm_disable: pm_runtime_disable(&pdev->dev); - reset_control_assert(resetn); return ret; } From patchwork Fri Feb 7 11:36:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13964855 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 02BBB1A9B4C for ; Fri, 7 Feb 2025 11:37:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928237; cv=none; b=l8g/pWq/ek+zxVO/s4J3CgU17JftFFz6/kfJtMJzqImWkloSRaMCbdxgU8miH6vLMDpbgg3Gu2LQqCv53kzQ6ptsG6qP1RHDtqetnjoAVQSH7RCSUeU2JikDlzTyXajICAuvpY8MdDquQ45UxqtpMpzj4pWcOPuh1U9NrQkZZg4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928237; c=relaxed/simple; bh=sCWaH8YQA8EZ8nbgrAyLX1Bz/TugEnmOoDJ+vfH7aQw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZEb/jCLpbhgwEDtm9RIJBXmFqGRtYOd+dXPvIZBLWtuejQA70i4WZNKZ0CqRWsffkjFqPK7KyP2Vi3ZSISMUr4bWUfpuqUVkc2oSDdI86BQucSb51Z5/EEF6G4QhJRQICe2Xke2uOAwzV9A9KNZRsye6wQVZTf/tjwjoMwlg7/Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 0Ois9cKsTT6Omv3yPJZY9w== X-CSE-MsgGUID: g6b//YXwR4qB/yIAWrqtCg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 07 Feb 2025 20:37:15 +0900 Received: from localhost.localdomain (unknown [10.226.93.6]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9372F4004D10; Fri, 7 Feb 2025 20:37:13 +0900 (JST) From: Biju Das To: Thomas Gleixner , Philipp Zabel Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 05/12] irqchip/renesas-rzv2h: Use devm_pm_runtime_enable() Date: Fri, 7 Feb 2025 11:36:37 +0000 Message-ID: <20250207113653.21641-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> References: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Simplify rzv2h_icu_init() by using devm_pm_runtime_enable(). Reviewed-by: Philipp Zabel Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v3->v4: * Collected tags. v2->v3: * Updated commit header. * Replaced 'goto put_dev' by 'return ret' as put_device() called by devm_add_action_or_reset(). v2: * New patch. --- drivers/irqchip/irq-renesas-rzv2h.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 95df8e0755e3..0211fd936514 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -468,11 +468,16 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) return ret; } - pm_runtime_enable(&pdev->dev); + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "devm_pm_runtime_enable failed, %d\n", ret); + return ret; + } + ret = pm_runtime_resume_and_get(&pdev->dev); if (ret < 0) { dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); - goto pm_disable; + return ret; } raw_spin_lock_init(&rzv2h_icu_data->lock); @@ -493,8 +498,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) pm_put: pm_runtime_put(&pdev->dev); -pm_disable: - pm_runtime_disable(&pdev->dev); return ret; } From patchwork Fri Feb 7 11:36:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13964856 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D614D1A83F5 for ; Fri, 7 Feb 2025 11:37:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928242; cv=none; b=MqYQOegc2hc5rNheGwQf35xH58UG5mQgox+iUFWw2AX8deFPZJq3CAVYpEt5YhxW6/M8d/Y+ycrFPbN+8OjsUCPFjQdPFibQNzOyDYy2gFBymN3Xc4Jod8IGZpgLBEzEOVeXQ2/bBgULFdrNusd2T7r4UF/y8CM2RjS/CsYdfPU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928242; c=relaxed/simple; bh=d8pvJZygiAhfn71zt4WERBrtkPHqaRjZfDNHPZ4O/vY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CfuYbptLbCzwj61fqKmwaEoOAi2Q4qORYaldwkU9QZzwbwhBCnlqeB25HmVwhSOOAR7Zd2z8s9xhAEQHTYH9hCkPjXJyaozAJt54vRdbGLRkzPAmf7cqmqM8fMeguKgw8XlKGtMEhE4zIztt7PoznStuGQsEjXK0hkCzZ9Z3Txg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: cAM3DqiKTVmG8ukCxqYygw== X-CSE-MsgGUID: glNzg5jpT9u9l9yJScpuhA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 07 Feb 2025 20:37:18 +0900 Received: from localhost.localdomain (unknown [10.226.93.6]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4C7374004D10; Fri, 7 Feb 2025 20:37:16 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Tommaso Merciai Subject: [PATCH v4 06/12] irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable Date: Fri, 7 Feb 2025 11:36:38 +0000 Message-ID: <20250207113653.21641-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> References: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences: - The TINT register base offset is 0x800 instead of zero.  - The number of GPIO interrupts for TINT selection is 141 instead of 86.  - The pin index and TINT selection index are not in the 1:1 map  - The number of TSSR registers is 16 instead of 8  - Each TSSR register can program 2 TINTs instead of 4 TINTs Introduce struct rzv2h_hw_info to handle these differences and add t_offs variable to take care of the TINT register offset difference between RZ/G3E and RZ/V2H. Refactor the code by moving rzv2h_icu_init() into rzv2h_icu_init_common() and pass the variable containing hw difference to support both these SoCs. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v3->v4: * Updated commit description with register offset->register base offset * Fixed typo 15->16 for the number of TSSR register for RZ/G3E. * Fixed the typo varable->variable. * Collected tag from Geert. v2->v3: * No change. v1->v2: * Collected tags * Started aligning kernel doc, struct members and struct initializers in a tabular fashion. --- drivers/irqchip/irq-renesas-rzv2h.c | 46 +++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 0211fd936514..e8014cd096f2 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -80,16 +80,26 @@ #define ICU_TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) #define ICU_PB5_TINT 0x55 +/** + * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. + * @t_offs: TINT offset + */ +struct rzv2h_hw_info { + u16 t_offs; +}; + /** * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure. * @base: Controller's base address * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers + * @info: Pointer to struct rzv2h_hw_info */ struct rzv2h_icu_priv { void __iomem *base; struct irq_fwspec fwspec[ICU_NUM_IRQ]; raw_spinlock_t lock; + const struct rzv2h_hw_info *info; }; static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *data) @@ -109,7 +119,7 @@ static void rzv2h_icu_eoi(struct irq_data *d) tintirq_nr = hw_irq - ICU_TINT_START; bit = BIT(tintirq_nr); if (!irqd_is_level_type(d)) - writel_relaxed(bit, priv->base + ICU_TSCLR); + writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); } else if (hw_irq >= ICU_IRQ_START) { tintirq_nr = hw_irq - ICU_IRQ_START; bit = BIT(tintirq_nr); @@ -137,12 +147,12 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) tssel_n = ICU_TSSR_TSSEL_N(tint_nr); guard(raw_spinlock)(&priv->lock); - tssr = readl_relaxed(priv->base + ICU_TSSR(k)); + tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); if (enable) tssr |= ICU_TSSR_TIEN(tssel_n); else tssr &= ~ICU_TSSR_TIEN(tssel_n); - writel_relaxed(tssr, priv->base + ICU_TSSR(k)); + writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k)); } static void rzv2h_icu_irq_disable(struct irq_data *d) @@ -245,8 +255,8 @@ static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq u32 bit = BIT(tint_nr); int k = tint_nr / 16; - tsctr = readl_relaxed(priv->base + ICU_TSCTR); - titsr = readl_relaxed(priv->base + ICU_TITSR(k)); + tsctr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSCTR); + titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(k)); titsel = ICU_TITSR_TITSEL_GET(titsr, titsel_n); /* @@ -255,7 +265,7 @@ static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq */ if ((tsctr & bit) && ((titsel == ICU_TINT_EDGE_RISING) || (titsel == ICU_TINT_EDGE_FALLING))) - writel_relaxed(bit, priv->base + ICU_TSCLR); + writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); } static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) @@ -306,21 +316,21 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) guard(raw_spinlock)(&priv->lock); - tssr = readl_relaxed(priv->base + ICU_TSSR(tssr_k)); + tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); - writel_relaxed(tssr, priv->base + ICU_TSSR(tssr_k)); + writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); - titsr = readl_relaxed(priv->base + ICU_TITSR(titsr_k)); + titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(titsr_k)); titsr &= ~ICU_TITSR_TITSEL_MASK(titsel_n); titsr |= ICU_TITSR_TITSEL_PREP(sense, titsel_n); - writel_relaxed(titsr, priv->base + ICU_TITSR(titsr_k)); + writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k)); rzv2h_clear_tint_int(priv, hwirq); - writel_relaxed(tssr | tien, priv->base + ICU_TSSR(tssr_k)); + writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); return 0; } @@ -424,7 +434,8 @@ static void rzv2h_icu_put_device(void *data) put_device(data); } -static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) +static int rzv2h_icu_init_common(struct device_node *node, struct device_node *parent, + const struct rzv2h_hw_info *hw_info) { struct irq_domain *irq_domain, *parent_domain; struct rzv2h_icu_priv *rzv2h_icu_data; @@ -490,6 +501,8 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) goto pm_put; } + rzv2h_icu_data->info = hw_info; + /* * coccicheck complains about a missing put_device call before returning, but it's a false * positive. We still need &pdev->dev after successfully returning from this function. @@ -502,6 +515,15 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) return ret; } +static const struct rzv2h_hw_info rzv2h_hw_params = { + .t_offs = 0, +}; + +static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) +{ + return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params); +} + IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu) IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init) IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu) From patchwork Fri Feb 7 11:36:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13964857 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4FB6A2417ED for ; Fri, 7 Feb 2025 11:37:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928243; cv=none; b=Fzns/t8Mw6VELJr64LV7tmP06i3gucWHWLV5gEvGooc+x/jfJxZfDQpFu7IkUstVkHtSdXngbptD3haItgTVNN6M24972tXYjl7/BYkFCIh6O2oaN5eh+Z0KU1AtV5GU6r9VtiZS0k7Qmsu7BmjRbndQBWmZ1Mve7N5NBOQEgRo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928243; c=relaxed/simple; bh=lV/Dk/YTbLbri7p2A3ZJqKNKdKS8GXF6V2nGhEwCEIo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kWaFDbXQuMz6IdGEZfnv4k0HGbH1320J/WJMaMxXm6flADYM9zUwM64udxanJJoeITY5hvTPM7LHzmTTFo+8lkFmGO9Aegx3P7GzGTue2a3j0PUYT9/cLiCs0jqKPayAf6aC2XQ0uGD+U8m+etGGK61uoVmQuHV2oC7fAkiC6Hw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: H7IcfjcMS3e6ZZRg8lTx2Q== X-CSE-MsgGUID: mUUvd+lySyGMkUKj+rX1zQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 07 Feb 2025 20:37:21 +0900 Received: from localhost.localdomain (unknown [10.226.93.6]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 57869400F31D; Fri, 7 Feb 2025 20:37:19 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Tommaso Merciai Subject: [PATCH v4 07/12] irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info Date: Fri, 7 Feb 2025 11:36:39 +0000 Message-ID: <20250207113653.21641-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> References: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The number of GPIO interrupts on RZ/G3E for TINT selection is 141 compared to 86 on RZ/V2H. Rename the macro ICU_PB5_TINT->ICU_RZV2H_TSSEL_MAX_VAL to hold this difference for RZ/V2H. Add max_tssel variable to struct rzv2h_hw_info to handle this difference. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v3->v4: * Collected tag from Geert. v2->v3: * No change. v1->v2: * Renamed the macro ICU_PB5_TINT->ICU_RZV2H_TSSEL_MAX_VAL. * Replaced hexa decimal constant with ICU_RZV2H_TSSEL_MAX_VAL in struct rzv2h_hw_params. --- drivers/irqchip/irq-renesas-rzv2h.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index e8014cd096f2..b52f5a85ce1c 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -78,14 +78,16 @@ #define ICU_TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define ICU_TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) -#define ICU_PB5_TINT 0x55 +#define ICU_RZV2H_TSSEL_MAX_VAL 0x55 /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset + * @max_tssel: TSSEL max value */ struct rzv2h_hw_info { u16 t_offs; + u8 max_tssel; }; /** @@ -298,13 +300,12 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) return -EINVAL; } + priv = irq_data_to_priv(d); tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d); - if (tint > ICU_PB5_TINT) + if (tint > priv->info->max_tssel) return -EINVAL; - priv = irq_data_to_priv(d); hwirq = irqd_to_hwirq(d); - tint_nr = hwirq - ICU_TINT_START; tssr_k = ICU_TSSR_K(tint_nr); @@ -517,6 +518,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, + .max_tssel = ICU_RZV2H_TSSEL_MAX_VAL, }; static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) From patchwork Fri Feb 7 11:36:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13964858 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3DDE52417ED for ; Fri, 7 Feb 2025 11:37:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928246; cv=none; b=R1CL9LsYrH35OSXGneSlYbdzmfQK5VEwrbDpb5XRI3MRLVFkcwhVX1l5vOmBxQ2IcSj1MRJP2upbSZ+qrGF2mH7BtZaWGD6qrcZr+CXKxEynKidQIlPSePlKIoQbkBq0QpEfhRwQViQHx9iVcMRLA7TkeT+idDrbj84gQBBe65Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928246; c=relaxed/simple; bh=awT4PQ6FRfvFAILZldWvvhRwomVUOLu2uqz2fBn68RY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PyCWAPhC92AeTjHw6BhbwjN9p7+4KyTOEbTURQQYlwxYLtS7rnQenEKBZM3KJkjBNj80CrCq2rd2+a4rW+NLtJojmFygdOCN899SXpFXvmqriEjbvfua1FiAXtSNnTLvJ3EeXUA2ZAxpbywhetZAhUt+8Wf0H9c7/V4PT0boxB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: HzKySYa0SEeRczVWRnZKdA== X-CSE-MsgGUID: YKVB3tb4RuGbxerjjazoyw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 07 Feb 2025 20:37:24 +0900 Received: from localhost.localdomain (unknown [10.226.93.6]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 53B044004D10; Fri, 7 Feb 2025 20:37:22 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 08/12] irqchip/renesas-rzv2h: Add field_width variable to struct rzv2h_hw_info Date: Fri, 7 Feb 2025 11:36:40 +0000 Message-ID: <20250207113653.21641-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> References: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On RZ/G3E the field width for TSSR register for a TINT is 16 compared to 8 on the RZ/V2H. Add field_width variable to struct rzv2h_hw_info to handle this difference and drop the macros ICU_TSSR_K and ICU_TSSR_TSSEL_N as (32 / field_width) provides the number of tints in TSSR register. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v4: New patch using field_width to handle the differences. --- drivers/irqchip/irq-renesas-rzv2h.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index b52f5a85ce1c..d96e4b2032b4 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,8 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_K(tint_nr) ((tint_nr) / 4) -#define ICU_TSSR_TSSEL_N(tint_nr) ((tint_nr) % 4) #define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) #define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) #define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) @@ -84,10 +82,12 @@ * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset * @max_tssel: TSSEL max value + * @field_width: TSSR field width */ struct rzv2h_hw_info { u16 t_offs; u8 max_tssel; + u8 field_width; }; /** @@ -140,13 +140,15 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) struct rzv2h_icu_priv *priv = irq_data_to_priv(d); unsigned int hw_irq = irqd_to_hwirq(d); u32 tint_nr, tssel_n, k, tssr; + u8 nr_tint; if (hw_irq < ICU_TINT_START) return; tint_nr = hw_irq - ICU_TINT_START; - k = ICU_TSSR_K(tint_nr); - tssel_n = ICU_TSSR_TSSEL_N(tint_nr); + nr_tint = 32 / priv->info->field_width; + k = tint_nr / nr_tint; + tssel_n = tint_nr % nr_tint; guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); @@ -278,6 +280,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) unsigned int hwirq; u32 tint, sense; int tint_nr; + u8 nr_tint; switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_LEVEL_LOW: @@ -308,8 +311,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) hwirq = irqd_to_hwirq(d); tint_nr = hwirq - ICU_TINT_START; - tssr_k = ICU_TSSR_K(tint_nr); - tssel_n = ICU_TSSR_TSSEL_N(tint_nr); + nr_tint = 32 / priv->info->field_width; + tssr_k = tint_nr / nr_tint; + tssel_n = tint_nr % nr_tint; titsr_k = ICU_TITSR_K(tint_nr); titsel_n = ICU_TITSR_TITSEL_N(tint_nr); @@ -519,6 +523,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, .max_tssel = ICU_RZV2H_TSSEL_MAX_VAL, + .field_width = 8, }; static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) From patchwork Fri Feb 7 11:36:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13964859 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 151AF2417ED for ; Fri, 7 Feb 2025 11:37:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: A+01QWNUQVyJcDNPPCws7w== X-CSE-MsgGUID: W3JJfU+tRV6DahmIjqAFnw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 07 Feb 2025 20:37:26 +0900 Received: from localhost.localdomain (unknown [10.226.93.6]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id C069F4004D10; Fri, 7 Feb 2025 20:37:24 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 09/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro Date: Fri, 7 Feb 2025 11:36:41 +0000 Message-ID: <20250207113653.21641-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> References: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. The macro ICU_TSSR_TIEN(n) can be replaced with the inline logic BIT(field_width - 1) << (n * fieldwidth) for supporting both SoCs. Signed-off-by: Biju Das --- v4: * New patch --- drivers/irqchip/irq-renesas-rzv2h.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index d96e4b2032b4..6d1de9277c7d 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -66,7 +66,6 @@ #define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) #define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) -#define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) @@ -153,9 +152,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); if (enable) - tssr |= ICU_TSSR_TIEN(tssel_n); + tssr |= BIT(priv->info->field_width - 1) << (tssel_n * priv->info->field_width); else - tssr &= ~ICU_TSSR_TIEN(tssel_n); + tssr &= ~(BIT(priv->info->field_width - 1) << (tssel_n * priv->info->field_width)); writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k)); } @@ -317,7 +316,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) titsr_k = ICU_TITSR_K(tint_nr); titsel_n = ICU_TITSR_TITSEL_N(tint_nr); - tien = ICU_TSSR_TIEN(titsel_n); + tien = BIT(priv->info->field_width - 1) << (titsel_n * priv->info->field_width); guard(raw_spinlock)(&priv->lock); From patchwork Fri Feb 7 11:36:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13964860 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 50F0B2417ED for ; Fri, 7 Feb 2025 11:37:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928251; cv=none; b=cPeotNKE4G7/OBA6Q5z5CN9mgQlAk2/D3ndmGxzjaGsM2+EAduxTOrlKixjBkVT6lrETKCdRqn+ln8l1EIafzuc4x/sUc01o4jswh+9NArohgT1lDChkBoGdJD64bMo2Aal9yeEyaoG51/XBgtrLe1QpfNe7s82gZ7clVnns8Mo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928251; c=relaxed/simple; bh=OHMkWSRLgxYy86+l0psAk8dW9QdPoTKP3zaI73JyHP0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=vC6BWNoSdRgPuc3JMUuSxY5eO2lhGqAZCLlL7tcwxKkR4gP3SsT8qKB2LrDSX8v8itg0PDkznEe8KQpQi2c401gNxUSsZ9trSh0rP6SITLE17FqgSi3kXhhE4VucnkhDF4GM+Dvos8/JNvGUFYVO8Z93hFdtOhlXcSMTZcHFADE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: GAANTO/+SPSoaCSci2maLA== X-CSE-MsgGUID: Jwg6OtM7TG2zz7rmRjyzKA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 07 Feb 2025 20:37:29 +0900 Received: from localhost.localdomain (unknown [10.226.93.6]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 3C1B14004D10; Fri, 7 Feb 2025 20:37:26 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 10/12] irqchip/renesas-rzv2h: Drop macros ICU_TSSR_TSSEL_{MASK,PREP} Date: Fri, 7 Feb 2025 11:36:42 +0000 Message-ID: <20250207113653.21641-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> References: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H. Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved bits is ignored. Use the bitmask GENMASK(field_width - 2, 0) on both SoCs for extracting TSSEL and we can drop the macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v4: * New patch --- drivers/irqchip/irq-renesas-rzv2h.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 6d1de9277c7d..71d06820e598 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,9 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) -#define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) - #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) #define ICU_TITSR_TITSEL_PREP(titsel, n) ICU_IITSR_IITSEL_PREP(titsel, n) @@ -321,8 +318,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); - tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); - tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); + tssr &= ~((GENMASK(priv->info->field_width - 2, 0) << + (tssel_n * priv->info->field_width)) | tien); + tssr |= (tint << (tssel_n * priv->info->field_width)); writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); From patchwork Fri Feb 7 11:36:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13964861 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C4B442417ED for ; Fri, 7 Feb 2025 11:37:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928255; cv=none; b=gmwEs76tWsvpl6Z/N5ZzeAXcOwE9C7rV4ZTJlmakhdu3Qq2fzgx1R9JN7z83lEYbW91HxWKCoEsQml/kLfEuSo8lw8spZ7pe0E/cojhfXW0I/ppYRTYeNqDR6BGgzBIlo/B84JbvuC2GONw5wjkx/+FYgyP7dcdRypT0409QUOc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738928255; c=relaxed/simple; bh=L/vptIL4q2c8njnuU75EUEnW+S7DG5V3gjcftmPO7AU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r23nUpx3F5eowM7VvkKPZf2ot0zMkkk9BARIkSTFEYOmx3IDqfnHTJ+xL+jRsyxekrjOEnx3aTdzor5DB5rJyKsNv86Ya4aT7L5ClwdhoebkUA5cYjPEG1jzxlOJRhS9//oX1VYgNm8WmH59CEhyBVHEBM3CjbVm2tlVLlh25Y4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: MgnVFrYzSPapcL4XmSkOOQ== X-CSE-MsgGUID: P94pfTMwRfS1JO8uvlLJGg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 07 Feb 2025 20:37:32 +0900 Received: from localhost.localdomain (unknown [10.226.93.6]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id AC0464004D10; Fri, 7 Feb 2025 20:37:29 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Tommaso Merciai Subject: [PATCH v4 11/12] irqchip/renesas-rzv2h: Add RZ/G3E support Date: Fri, 7 Feb 2025 11:36:43 +0000 Message-ID: <20250207113653.21641-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> References: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences: - The TINT register base offset is 0x800 instead of zero. - The number of GPIO interrupts for TINT selection is 141 instead of 86. - The pin index and TINT selection index are not in the 1:1 map. - The number of TSSR registers is 16 instead of 8. - Each TSSR register can program 2 TINTs instead of 4 TINTs. Add support for the RZ/G3E driver by filling the rzv2h_hw_info table and adding LUT for mapping between pin index and TINT selection index. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v3->v4: * Updated commit description fixing typos * Updated rzg3e_hw_params with .field_width and dropped .tien, .tssel_mask,.tssel_shift, .tssr_k as it can be derived from former. v2->v3: * No change. v1->v2: * Introduced ICU_RZG3E_{TSSEL_MAX_VAL,TINT_OFFSET} macros and used these macros in struct rzv2h_hw_params rather than using the hex constants. --- drivers/irqchip/irq-renesas-rzv2h.c | 46 +++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 71d06820e598..4c541389681a 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -72,15 +72,19 @@ #define ICU_TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define ICU_TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +#define ICU_RZG3E_TINT_OFFSET 0x800 +#define ICU_RZG3E_TSSEL_MAX_VAL 0x8c #define ICU_RZV2H_TSSEL_MAX_VAL 0x55 /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. + * @tssel_lut: TINT lookup table * @t_offs: TINT offset * @max_tssel: TSSEL max value * @field_width: TSSR field width */ struct rzv2h_hw_info { + const u8 *tssel_lut; u16 t_offs; u8 max_tssel; u8 field_width; @@ -304,6 +308,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) if (tint > priv->info->max_tssel) return -EINVAL; + if (priv->info->tssel_lut) + tint = priv->info->tssel_lut[tint]; + hwirq = irqd_to_hwirq(d); tint_nr = hwirq - ICU_TINT_START; @@ -517,18 +524,57 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p return ret; } +/* Mapping based on port index on Table 4.2-6 and TSSEL bits on Table 4.6-4 */ +static const u8 rzg3e_tssel_lut[] = { + 81, 82, 83, 84, 85, 86, 87, 88, /* P00-P07 */ + 89, 90, 91, 92, 93, 94, 95, 96, /* P10-P17 */ + 111, 112, /* P20-P21 */ + 97, 98, 99, 100, 101, 102, 103, 104, /* P30-P37 */ + 105, 106, 107, 108, 109, 110, /* P40-P45 */ + 113, 114, 115, 116, 117, 118, 119, /* P50-P56 */ + 120, 121, 122, 123, 124, 125, 126, /* P60-P66 */ + 127, 128, 129, 130, 131, 132, 133, 134, /* P70-P77 */ + 135, 136, 137, 138, 139, 140, /* P80-P85 */ + 43, 44, 45, 46, 47, 48, 49, 50, /* PA0-PA7 */ + 51, 52, 53, 54, 55, 56, 57, 58, /* PB0-PB7 */ + 59, 60, 61, /* PC0-PC2 */ + 62, 63, 64, 65, 66, 67, 68, 69, /* PD0-PD7 */ + 70, 71, 72, 73, 74, 75, 76, 77, /* PE0-PE7 */ + 78, 79, 80, /* PF0-PF2 */ + 25, 26, 27, 28, 29, 30, 31, 32, /* PG0-PG7 */ + 33, 34, 35, 36, 37, 38, /* PH0-PH5 */ + 4, 5, 6, 7, 8, /* PJ0-PJ4 */ + 39, 40, 41, 42, /* PK0-PK3 */ + 9, 10, 11, 12, 21, 22, 23, 24, /* PL0-PL7 */ + 13, 14, 15, 16, 17, 18, 19, 20, /* PM0-PM7 */ + 0, 1, 2, 3 /* PS0-PS3 */ +}; + +static const struct rzv2h_hw_info rzg3e_hw_params = { + .tssel_lut = rzg3e_tssel_lut, + .t_offs = ICU_RZG3E_TINT_OFFSET, + .max_tssel = ICU_RZG3E_TSSEL_MAX_VAL, + .field_width = 16, +}; + static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, .max_tssel = ICU_RZV2H_TSSEL_MAX_VAL, .field_width = 8, }; +static int rzg3e_icu_init(struct device_node *node, struct device_node *parent) +{ + return rzv2h_icu_init_common(node, parent, &rzg3e_hw_params); +} + static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) { return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params); } IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu) +IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init) IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init) IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu) MODULE_AUTHOR("Fabrizio Castro "); From patchwork Fri Feb 7 11:36:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13964862 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 071102417ED; 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dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: KYtpl/rWRWS8wMkN2wVeSw== X-CSE-MsgGUID: ArHasAppQMGYh10TKZF3OA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 07 Feb 2025 20:37:36 +0900 Received: from localhost.localdomain (unknown [10.226.93.6]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 21B544018328; Fri, 7 Feb 2025 20:37:32 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Fabrizio Castro , Tommaso Merciai Subject: [PATCH v4 12/12] arm64: dts: renesas: r9a09g047: Add icu node Date: Fri, 7 Feb 2025 11:36:44 +0000 Message-ID: <20250207113653.21641-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> References: <20250207113653.21641-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add interrupt control node to RZ/G3E ("R9A09G047") SoC DTSI and add icu as interrupt-parent of pincontrol. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v3->v4: * Dropped RZG3E_* macros. v2->v3: * No change. v1->v2: * Collected tags. --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index fe5eec87f2a5..4bc0b77f721a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -131,6 +131,95 @@ soc: soc { #size-cells = <2>; ranges; + icu: interrupt-controller@10400000 { + compatible = "renesas,r9a09g047-icu"; + reg = <0 0x10400000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "port_irq0", "port_irq1", "port_irq2", + "port_irq3", "port_irq4", "port_irq5", + "port_irq6", "port_irq7", "port_irq8", + "port_irq9", "port_irq10", "port_irq11", + "port_irq12", "port_irq13", "port_irq14", + "port_irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks = <&cpg CPG_MOD 0x5>; + power-domains = <&cpg>; + resets = <&cpg 0x36>; + }; + pinctrl: pinctrl@10410000 { compatible = "renesas,r9a09g047-pinctrl"; reg = <0 0x10410000 0 0x10000>; @@ -140,6 +229,7 @@ pinctrl: pinctrl@10410000 { gpio-ranges = <&pinctrl 0 0 232>; #interrupt-cells = <2>; interrupt-controller; + interrupt-parent = <&icu>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; };