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Signed-off-by: Andrew Cooper Reviewed-By: Oleksii Kurochko --- CC: Oleksii Kurochko CC: Anthony PERARD CC: Michal Orzel CC: Jan Beulich CC: Julien Grall CC: Roger Pau Monné CC: Stefano Stabellini https://gitlab.com/xen-project/people/andyhhp/xen/-/pipelines/1660821676 For-4.20. Boot selftests are new in 4.20, and work in each other archtiecture. --- xen/arch/riscv/setup.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 38ca4f3baa1b..f2b6e684ac69 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -109,6 +109,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, */ system_state = SYS_STATE_boot; + init_constructors(); + if ( acpi_disabled ) { printk("Booting using Device Tree\n"); From patchwork Fri Feb 7 22:01:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13965997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74F55C0219D for ; Fri, 7 Feb 2025 22:01:41 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.884033.1293848 (Exim 4.92) (envelope-from ) id 1tgWPl-0003hK-OU; Fri, 07 Feb 2025 22:01:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 884033.1293848; Fri, 07 Feb 2025 22:01:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tgWPl-0003h8-Lb; Fri, 07 Feb 2025 22:01:33 +0000 Received: by outflank-mailman (input) for mailman id 884033; Fri, 07 Feb 2025 22:01:32 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tgWPk-0002Xy-C3 for xen-devel@lists.xenproject.org; Fri, 07 Feb 2025 22:01:32 +0000 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [2a00:1450:4864:20::32b]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 16c9c6d2-e59f-11ef-a073-877d107080fb; Fri, 07 Feb 2025 23:01:31 +0100 (CET) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4361f796586so30590035e9.3 for ; Fri, 07 Feb 2025 14:01:31 -0800 (PST) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. 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To branch further, it needs pairing with an AUIPC instruction. CALL is a pseudo-op which allows the linker to pick the appropriate sequence while processing relaxations. This avoids a build failure of the form: prelink.o: in function `start': xen/xen/arch/riscv/riscv64/head.S:28:(.text.header+0x2c): relocation truncated to fit: R_RISCV_JAL against symbol `calc_phys_offset' defined in .init.text section in prelink.o make[3]: *** [arch/riscv/Makefile:18: xen-syms] Error 1 when Xen gets large enough, e.g. with CONFIG_UBSAN enabled. Signed-off-by: Andrew Cooper --- CC: Oleksii Kurochko CC: Anthony PERARD CC: Michal Orzel CC: Jan Beulich CC: Julien Grall CC: Roger Pau Monné CC: Stefano Stabellini --- xen/arch/riscv/entry.S | 2 +- xen/arch/riscv/riscv64/head.S | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/xen/arch/riscv/entry.S b/xen/arch/riscv/entry.S index bf974655f8b3..4db818ba8d24 100644 --- a/xen/arch/riscv/entry.S +++ b/xen/arch/riscv/entry.S @@ -49,7 +49,7 @@ save_to_stack: REG_S t0, CPU_USER_REGS_SSTATUS(sp) mv a0, sp - jal do_trap + call do_trap restore_registers: /* Restore stack_cpu_regs */ diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S index 2a1b3dad9191..9c40512e612e 100644 --- a/xen/arch/riscv/riscv64/head.S +++ b/xen/arch/riscv/riscv64/head.S @@ -28,7 +28,7 @@ FUNC(start) add t3, t3, __SIZEOF_POINTER__ bltu t3, t4, .L_clear_bss - jal reset_stack + call reset_stack /* * save hart_id ( bootcpu_id ) and dtb_base as a0 and a1 register can @@ -37,16 +37,16 @@ FUNC(start) mv s0, a0 mv s1, a1 - jal calc_phys_offset + call calc_phys_offset mv s2, a0 - jal setup_initial_pagetables + call setup_initial_pagetables /* Calculate proper VA after jump from 1:1 mapping */ la a0, .L_primary_switched sub a0, a0, s2 - jal turn_on_mmu + call turn_on_mmu .L_primary_switched: /* @@ -54,11 +54,11 @@ FUNC(start) * recalculated after jump from 1:1 mapping world as 1:1 mapping * will be removed soon in start_xen(). */ - jal reset_stack + call reset_stack /* Xen's boot cpu id is equal to 0 so setup TP register for it */ li a0, 0 - jal setup_tp + call setup_tp /* restore hart_id ( bootcpu_id ) and dtb address */ mv a0, s0 From patchwork Fri Feb 7 22:01:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13965998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07A6DC0219E for ; Fri, 7 Feb 2025 22:01:43 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.884034.1293852 (Exim 4.92) (envelope-from ) id 1tgWPm-0003jp-1p; Fri, 07 Feb 2025 22:01:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 884034.1293852; Fri, 07 Feb 2025 22:01:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tgWPl-0003il-T6; Fri, 07 Feb 2025 22:01:33 +0000 Received: by outflank-mailman (input) for mailman id 884034; Fri, 07 Feb 2025 22:01:33 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tgWPl-0002Xy-Fn for xen-devel@lists.xenproject.org; Fri, 07 Feb 2025 22:01:33 +0000 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [2a00:1450:4864:20::444]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 177a9ca8-e59f-11ef-a073-877d107080fb; Fri, 07 Feb 2025 23:01:33 +0100 (CET) Received: by mail-wr1-x444.google.com with SMTP id ffacd0b85a97d-38dd14c99c3so210236f8f.3 for ; Fri, 07 Feb 2025 14:01:32 -0800 (PST) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. [92.26.98.202]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dcb4410e6sm2636035f8f.8.2025.02.07.14.01.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 14:01:31 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 177a9ca8-e59f-11ef-a073-877d107080fb DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1738965692; x=1739570492; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bHWhi9LlP88PFOcKM3oJlGjDcIcKjnkLzR/D136D9GI=; b=bpfS/Sf8/9nCarnHsuVf/iohWwcMK/u2SuDRyXd6sEo/8CiwdgKCBnhTaxDdIXktBJ Jg0BXLeJzmJGO5U/0gj+DXOpcXfqMWCzAB286vNVNZZE6lmJ4JF0tCaxp4l/se0HZHwI WoSrCIrw2IlXHBnAsgckjUV07mWmlCzlwa57o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738965692; x=1739570492; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bHWhi9LlP88PFOcKM3oJlGjDcIcKjnkLzR/D136D9GI=; b=sY1LYdJgSEpLDgIrBSTsf8Ly2HqQmQWb/0BIpzhPck43AWZCubti1hn8tbFKfHYv/Z YJ1R5gY8BrLfZZTTS0Xa4eXyMSD2WobwFZltqgmDO/HLlAPsRH5cI2Zd3BDKKpAAlseR nuGplOQGhR44dNfo0Vyg/9KMeHD1NS+q/LjZgTwKQAbukTO5e2k3L0QFfvvBKsJscYUE Ki6hlI8Usv1a+4DdF4NzZo9QCt4DKS7ZFdzJQFvuAw5D7IbjPy96hHXhtsjV4Qfc7pBj An6ARgkUA04jBbRb8An9Frs79WdjVaGjyNyvWwfqv/O9TciIQIW+YEgZVxilhlW+jkS1 mL0A== X-Gm-Message-State: AOJu0Yx/ZrWXu1MEathAd4SvX+H1FYeBXnG6cGZ4nUMoi0RMV57L+wem XKUfZCh9u+8VnkwFCR27yjsjK91o2VWLJaldHtKDP1YiQa+x1enodAU4Ncpjn6N4XpA9ua2+189 2ZPqZhw== X-Gm-Gg: ASbGncuwO22xml2k/50X4ACi5GABw4FmpRJkDbRUV9C2v6EsRTSLWOVpO61bXI3EDoH idYXlc6gskr0hU9gh8pMY4kp8pwQy3sDPm2jw6t7O7k4HVRAdAmOvk7U3N5tjYm8Fu7qZBDlr5P H4mn854wPHTuR9PBRrSR2C9xOixKZktuN1kvDR5kF+wAU+frNVr1OvVgulaRhG1CfpT3AGkiSc2 +JCKZmWwGpnsrh582T0jgaIAl17b4x4VSx+WYqG1vlCxxgGxpjFY/W07uJROiWC+EKsNOgx81ui poXy8JWYq9LuuVsS+/3d2+gA/KP3fLt/Oa3Lu1W53sCiOMLCgdyyHJEocYF0kkd3gDfGqKY= X-Google-Smtp-Source: AGHT+IGToOrXAyQPYAf4GdaAsMQzgNSFBh22mxX8a3arJxgNN1SUCCQSqaQrCu1bLfz8Q+/cY2mrSA== X-Received: by 2002:a5d:5f48:0:b0:385:f7a3:fed1 with SMTP id ffacd0b85a97d-38dc935ef28mr4234767f8f.44.1738965691999; Fri, 07 Feb 2025 14:01:31 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Oleksii Kurochko , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH for-4.20 3/3] RISCV: Activate UBSAN in testing Date: Fri, 7 Feb 2025 22:01:22 +0000 Message-Id: <20250207220122.380214-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250207220122.380214-1-andrew.cooper3@citrix.com> References: <20250207220122.380214-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 RISC-V has less complicated headers, so update ubsan.c to pull in everything it needs. Provide dump_execution_state(), and update the printk() message to make it more obvious that it's an outstanding task. As with commit 8ef2ac727e21 ("automation: enable UBSAN for debug tests"), enable UBSAN in RISC-V testing too. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Stefano Stabellini --- CC: Oleksii Kurochko CC: Anthony PERARD CC: Michal Orzel CC: Jan Beulich CC: Julien Grall CC: Roger Pau Monné CC: Stefano Stabellini Testing of this series: https://gitlab.com/xen-project/people/andyhhp/xen/-/jobs/9078817715 Sample run with an intentional UBSAN failure: https://gitlab.com/xen-project/people/andyhhp/xen/-/jobs/9078570135 --- automation/gitlab-ci/build.yaml | 3 +++ xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/include/asm/processor.h | 2 ++ xen/arch/riscv/traps.c | 2 +- xen/common/ubsan/ubsan.c | 5 ++++- 5 files changed, 11 insertions(+), 2 deletions(-) diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml index fb55d4ce5568..35e224366f62 100644 --- a/automation/gitlab-ci/build.yaml +++ b/automation/gitlab-ci/build.yaml @@ -359,6 +359,9 @@ debian-12-riscv64-gcc-debug: CONTAINER: debian:12-riscv64 KBUILD_DEFCONFIG: tiny64_defconfig HYPERVISOR_ONLY: y + EXTRA_XEN_CONFIG: | + CONFIG_UBSAN=y + CONFIG_UBSAN_FATAL=y # Arm32 cross-build diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index 00f329054c94..fa95cd0a4213 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -4,6 +4,7 @@ config RISCV select GENERIC_BUG_FRAME select HAS_DEVICE_TREE select HAS_PMAP + select HAS_UBSAN select HAS_VMAP config RISCV_64 diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/include/asm/processor.h index 90b800956303..39696fb58dc6 100644 --- a/xen/arch/riscv/include/asm/processor.h +++ b/xen/arch/riscv/include/asm/processor.h @@ -91,6 +91,8 @@ static inline void sfence_vma(void) asm volatile ( "sfence.vma" ::: "memory" ); } +#define dump_execution_state() run_in_exception_handler(show_execution_state) + #endif /* __ASSEMBLY__ */ #endif /* ASM__RISCV__PROCESSOR_H */ diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index d55a4a827b8c..ea3638a54fed 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -140,7 +140,7 @@ void vcpu_show_execution_state(struct vcpu *v) void show_execution_state(const struct cpu_user_regs *regs) { - printk("implement show_execution_state(regs)\n"); + printk("TODO: Implement show_execution_state(regs)\n"); } void arch_hypercall_tasklet_result(struct vcpu *v, long res) diff --git a/xen/common/ubsan/ubsan.c b/xen/common/ubsan/ubsan.c index 7f73f94759db..e99370322b44 100644 --- a/xen/common/ubsan/ubsan.c +++ b/xen/common/ubsan/ubsan.c @@ -10,8 +10,11 @@ * */ -#include +#include +#include +#include #include +#include #define __noreturn noreturn #define pr_err(...) printk(XENLOG_ERR __VA_ARGS__)