From patchwork Sat Aug 18 00:08:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkata Narendra Kumar Gutta X-Patchwork-Id: 10569449 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6244E139A for ; Sat, 18 Aug 2018 00:09:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 518D42BA76 for ; Sat, 18 Aug 2018 00:09:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 45FED2BA8D; Sat, 18 Aug 2018 00:09:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7EA642BA80 for ; Sat, 18 Aug 2018 00:09:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726342AbeHRDOQ (ORCPT ); Fri, 17 Aug 2018 23:14:16 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:40494 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726054AbeHRDOQ (ORCPT ); Fri, 17 Aug 2018 23:14:16 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id CF38B624C0; Sat, 18 Aug 2018 00:08:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1534550925; bh=yNyN9CtZNJbAKE+N6+F9qkLKoMCdJe26xlVBad6kwY4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CeyqkzHlR00d8k0XszgHwLY79qPC7LeFngf+8SGiY362vlk7ggWLMf4EPwe2Gh8UB Ks9UVRZnuDWUNHQe5Ven7kZ6OYos/cA4a8wJLNqlK0914S3iYkdQCEI0K29wRO/QyK rcgDYLJRWZvN9aiRYJfbAZyGbSb7LDVLgplA/tqM= Received: from vgutta-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: vnkgutta@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3260B6249E; Sat, 18 Aug 2018 00:08:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1534550924; bh=yNyN9CtZNJbAKE+N6+F9qkLKoMCdJe26xlVBad6kwY4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cYcYW7sMbLO2RikoJQfHlUX1g5G/Sx2IP1wL0+eqhPhGcQxV94YFMJX9IdrOupSTf jPV8bVpMnc/i4/dT4CgaR2EikbLhpFcC9Chc0fHSL5zsobGlFGtDeAwRv4ShxaTwR/ xx8bwZw1Tr8jrGGhe6n4MVS53tVxznfDrkWtSmdA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3260B6249E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vnkgutta@codeaurora.org From: Venkata Narendra Kumar Gutta To: robh@kernel.org, mchehab@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, rishabhb@codeaurora.org, bp@alien8.de, evgreen@chromium.org Cc: Venkata Narendra Kumar Gutta Subject: [PATCH v2 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Date: Fri, 17 Aug 2018 17:08:32 -0700 Message-Id: <1534550915-18230-2-git-send-email-vnkgutta@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534550915-18230-1-git-send-email-vnkgutta@codeaurora.org> References: <1534550915-18230-1-git-send-email-vnkgutta@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, boradcast base is set to end of the LLCC banks, which may not be correct always. As the number of banks may vary for each chipset and the broadcast base could be at a different address as well. This info depends on the chipset, so get the broadcast base info from the device tree (DT). Add broadcast base in LLCC driver and use this for broadcast writes. Signed-off-by: Venkata Narendra Kumar Gutta Reviewed-by: Evan Green --- drivers/soc/qcom/llcc-slice.c | 55 +++++++++++++++++++++++--------------- include/linux/soc/qcom/llcc-qcom.h | 4 +-- 2 files changed, 35 insertions(+), 24 deletions(-) diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c index fcaad1a..a63640d 100644 --- a/drivers/soc/qcom/llcc-slice.c +++ b/drivers/soc/qcom/llcc-slice.c @@ -105,22 +105,24 @@ static int llcc_update_act_ctrl(u32 sid, u32 slice_status; int ret; - act_ctrl_reg = drv_data->bcast_off + LLCC_TRP_ACT_CTRLn(sid); - status_reg = drv_data->bcast_off + LLCC_TRP_STATUSn(sid); + act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); + status_reg = LLCC_TRP_STATUSn(sid); /* Set the ACTIVE trigger */ act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; - ret = regmap_write(drv_data->regmap, act_ctrl_reg, act_ctrl_reg_val); + ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, + act_ctrl_reg_val); if (ret) return ret; /* Clear the ACTIVE trigger */ act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; - ret = regmap_write(drv_data->regmap, act_ctrl_reg, act_ctrl_reg_val); + ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, + act_ctrl_reg_val); if (ret) return ret; - ret = regmap_read_poll_timeout(drv_data->regmap, status_reg, + ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, slice_status, !(slice_status & status), 0, LLCC_STATUS_READ_DELAY); return ret; @@ -225,16 +227,13 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev) int ret; const struct llcc_slice_config *llcc_table; struct llcc_slice_desc desc; - u32 bcast_off = drv_data->bcast_off; sz = drv_data->cfg_size; llcc_table = drv_data->cfg; for (i = 0; i < sz; i++) { - attr1_cfg = bcast_off + - LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id); - attr0_cfg = bcast_off + - LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id); + attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id); + attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id); attr1_val = llcc_table[i].cache_mode; attr1_val |= llcc_table[i].probe_target_ways << @@ -259,10 +258,12 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev) attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK; attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT; - ret = regmap_write(drv_data->regmap, attr1_cfg, attr1_val); + ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, + attr1_val); if (ret) return ret; - ret = regmap_write(drv_data->regmap, attr0_cfg, attr0_val); + ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, + attr0_val); if (ret) return ret; if (llcc_table[i].activate_on_init) { @@ -278,24 +279,36 @@ int qcom_llcc_probe(struct platform_device *pdev, { u32 num_banks; struct device *dev = &pdev->dev; - struct resource *res; - void __iomem *base; + struct resource *llcc_banks_res, *llcc_bcast_res; + void __iomem *llcc_banks_base, *llcc_bcast_base; int ret, i; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); + llcc_banks_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "llcc_base"); + llcc_banks_base = devm_ioremap_resource(&pdev->dev, llcc_banks_res); + if (IS_ERR(llcc_banks_base)) + return PTR_ERR(llcc_banks_base); - drv_data->regmap = devm_regmap_init_mmio(dev, base, - &llcc_regmap_config); + drv_data->regmap = devm_regmap_init_mmio(dev, llcc_banks_base, + &llcc_regmap_config); if (IS_ERR(drv_data->regmap)) return PTR_ERR(drv_data->regmap); + llcc_bcast_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "llcc_broadcast_base"); + llcc_bcast_base = devm_ioremap_resource(&pdev->dev, llcc_bcast_res); + if (IS_ERR(llcc_bcast_base)) + return PTR_ERR(llcc_bcast_base); + + drv_data->bcast_regmap = devm_regmap_init_mmio(dev, llcc_bcast_base, + &llcc_regmap_config); + if (IS_ERR(drv_data->bcast_regmap)) + return PTR_ERR(drv_data->bcast_regmap); + ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0, &num_banks); if (ret) @@ -317,8 +330,6 @@ int qcom_llcc_probe(struct platform_device *pdev, for (i = 0; i < num_banks; i++) drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; - drv_data->bcast_off = num_banks * BANK_OFFSET_STRIDE; - drv_data->bitmap = devm_kcalloc(dev, BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long), GFP_KERNEL); diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 7e3b9c6..c681e79 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -70,22 +70,22 @@ struct llcc_slice_config { /** * llcc_drv_data - Data associated with the llcc driver * @regmap: regmap associated with the llcc device + * @bcast_regmap: regmap associated with llcc broadcast offset * @cfg: pointer to the data structure for slice configuration * @lock: mutex associated with each slice * @cfg_size: size of the config data table * @max_slices: max slices as read from device tree - * @bcast_off: Offset of the broadcast bank * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids * @offsets: Pointer to the bank offsets array */ struct llcc_drv_data { struct regmap *regmap; + struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; struct mutex lock; u32 cfg_size; u32 max_slices; - u32 bcast_off; u32 num_banks; unsigned long *bitmap; u32 *offsets; From patchwork Sat Aug 18 00:08:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkata Narendra Kumar Gutta X-Patchwork-Id: 10569453 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3E65D174F for ; Sat, 18 Aug 2018 00:09:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2D6A72BA76 for ; Sat, 18 Aug 2018 00:09:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 21B6E2BA8D; Sat, 18 Aug 2018 00:09:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B502F2BA76 for ; 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Sat, 18 Aug 2018 00:08:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1534550925; bh=4AQtvlKEktSclZdZmrS7yx+qJJsnDzeTSNcs7y8PnbY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XSxg6gejVExNTK1SDJr11Kd3fVWPBX5LKevLl7MNdUDC1hlvZ8uahk06avYzeGIPb eiLX/G5yRwSeOQz6C+oLleebaLOE5ogOjyNArDQLOUnl1vxDWanEBRRY4oMB1xgnbZ SFLqA7XHKxfAkbAzjHO52GkuTP+MvDo0eLpS30WA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 005B7621AD Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vnkgutta@codeaurora.org From: Venkata Narendra Kumar Gutta To: robh@kernel.org, mchehab@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, rishabhb@codeaurora.org, bp@alien8.de, evgreen@chromium.org Cc: Venkata Narendra Kumar Gutta Subject: [PATCH v2 2/4] drivers: soc: Add support to register LLCC EDAC driver Date: Fri, 17 Aug 2018 17:08:33 -0700 Message-Id: <1534550915-18230-3-git-send-email-vnkgutta@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534550915-18230-1-git-send-email-vnkgutta@codeaurora.org> References: <1534550915-18230-1-git-send-email-vnkgutta@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Cache error reporting controller is to detect and report single and double bit errors on Last Level Cache Controller (LLCC) cache. Add required support to register LLCC EDAC driver as platform driver, from LLCC driver. Signed-off-by: Venkata Narendra Kumar Gutta Reviewed-by: Evan Green --- drivers/soc/qcom/llcc-slice.c | 18 ++++++++++++++++-- include/linux/soc/qcom/llcc-qcom.h | 2 ++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c index a63640d..09c8bb0 100644 --- a/drivers/soc/qcom/llcc-slice.c +++ b/drivers/soc/qcom/llcc-slice.c @@ -224,7 +224,7 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev) u32 attr0_val; u32 max_cap_cacheline; u32 sz; - int ret; + int ret = 0; const struct llcc_slice_config *llcc_table; struct llcc_slice_desc desc; @@ -282,6 +282,7 @@ int qcom_llcc_probe(struct platform_device *pdev, struct resource *llcc_banks_res, *llcc_bcast_res; void __iomem *llcc_banks_base, *llcc_bcast_base; int ret, i; + struct platform_device *llcc_edac; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) @@ -341,6 +342,19 @@ int qcom_llcc_probe(struct platform_device *pdev, mutex_init(&drv_data->lock); platform_set_drvdata(pdev, drv_data); - return qcom_llcc_cfg_program(pdev); + ret = qcom_llcc_cfg_program(pdev); + if (ret) + return ret; + + drv_data->ecc_irq = platform_get_irq(pdev, 0); + if (drv_data->ecc_irq >= 0) { + llcc_edac = platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); + } + + return ret; } EXPORT_SYMBOL_GPL(qcom_llcc_probe); diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index c681e79..2e4b34d 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -78,6 +78,7 @@ struct llcc_slice_config { * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids * @offsets: Pointer to the bank offsets array + * @ecc_irq: interrupt for llcc cache error detection and reporting */ struct llcc_drv_data { struct regmap *regmap; @@ -89,6 +90,7 @@ struct llcc_drv_data { u32 num_banks; unsigned long *bitmap; u32 *offsets; + int ecc_irq; }; #if IS_ENABLED(CONFIG_QCOM_LLCC) From patchwork Sat Aug 18 00:08:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkata Narendra Kumar Gutta X-Patchwork-Id: 10569451 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4B276139A for ; Sat, 18 Aug 2018 00:09:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 36F6F2BA71 for ; Sat, 18 Aug 2018 00:09:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2B05C2BA80; Sat, 18 Aug 2018 00:09:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CE5482BA71 for ; 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Sat, 18 Aug 2018 00:08:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1534550926; bh=AGUMAz9kgsyxtTdglSk4mLQiqyg/qGkPnipKUYdPjY4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SRuaIGh86sXCC38N6WaPCfaJqMLC8u/KfQokZnqYSvcz45kVfcZHk5mvaDl/5iv1V WYtN3eEGyxnBhIXUQ1X4yCHDjCfGIcBItGbjKiZ1rV0Lm0/1PXg4zkznENLyy0zzuv R9OQX9MO9wHwWLfPkp4SMujuWo/T6NEnl8FFNHdE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CB146624C2 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vnkgutta@codeaurora.org From: Venkata Narendra Kumar Gutta To: robh@kernel.org, mchehab@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, rishabhb@codeaurora.org, bp@alien8.de, evgreen@chromium.org Cc: Venkata Narendra Kumar Gutta Subject: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Date: Fri, 17 Aug 2018 17:08:34 -0700 Message-Id: <1534550915-18230-4-git-send-email-vnkgutta@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534550915-18230-1-git-send-email-vnkgutta@codeaurora.org> References: <1534550915-18230-1-git-send-email-vnkgutta@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Channagoud Kadabi Add error reporting driver for Single Bit Errors (SBEs) and Double Bit Errors (DBEs). As of now, this driver supports erp for Last Level Cache Controller (LLCC). This driver takes care of dumping registers and adding config options to enable and disable panic when the errors happen in cache. Signed-off-by: Channagoud Kadabi Signed-off-by: Venkata Narendra Kumar Gutta Co-developed-by: Venkata Narendra Kumar Gutta --- MAINTAINERS | 8 + drivers/edac/Kconfig | 28 +++ drivers/edac/Makefile | 1 + drivers/edac/qcom_edac.c | 446 +++++++++++++++++++++++++++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 25 +++ 5 files changed, 508 insertions(+) create mode 100644 drivers/edac/qcom_edac.c diff --git a/MAINTAINERS b/MAINTAINERS index 0a23427..0bff713 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5227,6 +5227,14 @@ L: linux-edac@vger.kernel.org S: Maintained F: drivers/edac/ti_edac.c +EDAC-QUALCOMM +M: Channagoud Kadabi +M: Venkata Narendra Kumar Gutta +L: linux-arm-msm@vger.kernel.org +L: linux-edac@vger.kernel.org +S: Maintained +F: drivers/edac/qcom_edac.c + EDIROL UA-101/UA-1000 DRIVER M: Clemens Ladisch L: alsa-devel@alsa-project.org (moderated for non-subscribers) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 57304b2..da8f150 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -460,4 +460,32 @@ config EDAC_TI Support for error detection and correction on the TI SoCs. +config EDAC_QCOM + tristate "QCOM EDAC Controller" + depends on EDAC + help + Support for error detection and correction on the + QCOM SoCs. + +config EDAC_QCOM_LLCC + tristate "QCOM EDAC Controller for LLCC Cache" + depends on EDAC_QCOM && QCOM_LLCC + help + Support for error detection and correction on the + QCOM LLCC cache. Report errors caught by LLCC ECC + mechanism. + + For debugging issues having to do with stability and overall system + health, you should probably say 'Y' here. + +config EDAC_QCOM_LLCC_PANIC_ON_UE + bool "Panic on uncorrectable errors - qcom llcc" + depends on EDAC_QCOM_LLCC + help + Forcibly cause a kernel panic if an uncorrectable error (UE) is + detected. This can reduce debugging times on hardware which may be + operating at voltages or frequencies outside normal specification. + + For production builds, you should probably say 'N' here. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 02b43a7..716096d 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o +obj-$(CONFIG_EDAC_QCOM) += qcom_edac.o diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c new file mode 100644 index 0000000..9a8c670 --- /dev/null +++ b/drivers/edac/qcom_edac.c @@ -0,0 +1,446 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "edac_mc.h" +#include "edac_device.h" + +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE +#define LLCC_ERP_PANIC_ON_UE 1 +#else +#define LLCC_ERP_PANIC_ON_UE 0 +#endif + +#define EDAC_LLCC "qcom_llcc" + +#define TRP_SYN_REG_CNT 6 + +#define DRP_SYN_REG_CNT 8 + +#define LLCC_COMMON_STATUS0 0x0003000C +#define LLCC_LB_CNT_MASK GENMASK(31, 28) +#define LLCC_LB_CNT_SHIFT 28 + +/* single & Double Bit syndrome register offsets */ +#define TRP_ECC_SB_ERR_SYN0 0x0002304C +#define TRP_ECC_DB_ERR_SYN0 0x00020370 +#define DRP_ECC_SB_ERR_SYN0 0x0004204C +#define DRP_ECC_DB_ERR_SYN0 0x00042070 + +/* Error register offsets */ +#define TRP_ECC_ERROR_STATUS1 0x00020348 +#define TRP_ECC_ERROR_STATUS0 0x00020344 +#define DRP_ECC_ERROR_STATUS1 0x00042048 +#define DRP_ECC_ERROR_STATUS0 0x00042044 + +/* TRP, DRP interrupt register offsets */ +#define DRP_INTERRUPT_STATUS 0x00041000 +#define TRP_INTERRUPT_0_STATUS 0x00020480 +#define DRP_INTERRUPT_CLEAR 0x00041008 +#define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004 +#define TRP_INTERRUPT_0_CLEAR 0x00020484 +#define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440 + +/* Mask and shift macros */ +#define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0) +#define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16) +#define ECC_DB_ERR_WAYS_SHIFT BIT(4) + +#define ECC_SB_ERR_COUNT_MASK GENMASK(23, 16) +#define ECC_SB_ERR_COUNT_SHIFT BIT(4) +#define ECC_SB_ERR_WAYS_MASK GENMASK(15, 0) + +#define SB_ECC_ERROR BIT(0) +#define DB_ECC_ERROR BIT(1) + +#define DRP_TRP_INT_CLEAR GENMASK(1, 0) +#define DRP_TRP_CNT_CLEAR GENMASK(1, 0) + +/* Config registers offsets*/ +#define DRP_ECC_ERROR_CFG 0x00040000 + +/* TRP, DRP interrupt register offsets */ +#define CMN_INTERRUPT_0_ENABLE 0x0003001C +#define CMN_INTERRUPT_2_ENABLE 0x0003003C +#define TRP_INTERRUPT_0_ENABLE 0x00020488 +#define DRP_INTERRUPT_ENABLE 0x0004100C + +#define SB_ERROR_THRESHOLD 0x1 +#define SB_ERROR_THRESHOLD_SHIFT 24 +#define SB_DB_TRP_INTERRUPT_ENABLE 0x3 +#define TRP0_INTERRUPT_ENABLE 0x1 +#define DRP0_INTERRUPT_ENABLE BIT(6) +#define SB_DB_DRP_INTERRUPT_ENABLE 0x3 + +enum { + LLCC_DRAM_CE = 0, + LLCC_DRAM_UE, + LLCC_TRAM_CE, + LLCC_TRAM_UE, + LLCC_ERR_TYPE_MAX = LLCC_TRAM_UE + 1, +}; + +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap) +{ + u32 sb_err_threshold; + int ret; + + /* Enable TRP in instance 2 of common interrupt enable register */ + ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE, + TRP0_INTERRUPT_ENABLE, + TRP0_INTERRUPT_ENABLE); + if (ret) + return ret; + + /* Enable ECC interrupts on Tag Ram */ + ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE, + SB_DB_TRP_INTERRUPT_ENABLE, + SB_DB_TRP_INTERRUPT_ENABLE); + if (ret) + return ret; + + /* Enable SB error for Data RAM */ + sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT); + ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG, + sb_err_threshold); + if (ret) + return ret; + + /* Enable DRP in instance 2 of common interrupt enable register */ + ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE, + DRP0_INTERRUPT_ENABLE, + DRP0_INTERRUPT_ENABLE); + if (ret) + return ret; + + /* Enable ECC interrupts on Data Ram */ + ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE, + SB_DB_DRP_INTERRUPT_ENABLE); + return ret; +} + +/* Clear the error interrupt and counter registers */ +static int +qcom_llcc_clear_errors_status(int err_type, struct llcc_drv_data *drv) +{ + int ret = 0; + + switch (err_type) { + case LLCC_DRAM_CE: + case LLCC_DRAM_UE: + /* Clear the interrupt */ + ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR, + DRP_TRP_INT_CLEAR); + if (ret) + return ret; + + /* Clear the counters */ + ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR, + DRP_TRP_CNT_CLEAR); + if (ret) + return ret; + break; + case LLCC_TRAM_CE: + case LLCC_TRAM_UE: + ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR, + DRP_TRP_INT_CLEAR); + if (ret) + return ret; + + ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR, + DRP_TRP_CNT_CLEAR); + if (ret) + return ret; + break; + } + return ret; +} + +/* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/ +static int +dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) +{ + struct llcc_edac_reg_data *reg_data = &(drv->edac_reg[err_type]); + int err_cnt, err_ways, ret, i; + u32 synd_reg, synd_val; + + for (i = 0; i < reg_data->reg_cnt; i++) { + synd_reg = reg_data->synd_reg + (i * 4); + ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + &synd_val); + if (ret) + goto clear; + edac_printk(KERN_CRIT, EDAC_LLCC, "%s: ECC_SYN%d: 0x%8x\n", + reg_data->err_name, i, synd_val); + } + + ret = regmap_read(drv->regmap, + drv->offsets[bank] + reg_data->err_status_reg, + &err_cnt); + if (ret) + goto clear; + + err_cnt &= reg_data->err_count_mask; + err_cnt >>= reg_data->err_count_shift; + edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error count: 0x%4x\n", + reg_data->err_name, err_cnt); + + ret = regmap_read(drv->regmap, + drv->offsets[bank] + reg_data->err_ways_status, + &err_ways); + if (ret) + goto clear; + + err_ways &= reg_data->err_ways_mask; + err_ways >>= reg_data->err_ways_shift; + + edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error ways: 0x%4x\n", + reg_data->err_name, err_ways); + +clear: + ret = qcom_llcc_clear_errors_status(err_type, drv); + return ret; +} + +static int +dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) +{ + struct llcc_drv_data *drv = edev_ctl->pvt_info; + int ret = 0; + + ret = dump_syn_reg_values(drv, bank, err_type); + if (ret) + return ret; + + switch (err_type) { + case LLCC_DRAM_CE: + edac_device_handle_ce(edev_ctl, 0, bank, + "LLCC Data RAM correctable Error"); + break; + case LLCC_DRAM_UE: + edac_device_handle_ue(edev_ctl, 0, bank, + "LLCC Data RAM uncorrectable Error"); + break; + case LLCC_TRAM_CE: + edac_device_handle_ce(edev_ctl, 0, bank, + "LLCC Tag RAM correctable Error"); + break; + case LLCC_TRAM_UE: + edac_device_handle_ue(edev_ctl, 0, bank, + "LLCC Tag RAM uncorrectable Error"); + break; + } + + return ret; +} + +static irqreturn_t +llcc_ecc_irq_handler(int irq, void *edev_ctl) +{ + struct edac_device_ctl_info *edac_dev_ctl; + irqreturn_t irq_rc = IRQ_NONE; + u32 drp_error, trp_error, i; + struct llcc_drv_data *drv; + int ret; + + edac_dev_ctl = (struct edac_device_ctl_info *)edev_ctl; + drv = edac_dev_ctl->pvt_info; + + for (i = 0; i < drv->num_banks; i++) { + /* Look for Data RAM errors */ + ret = regmap_read(drv->regmap, + drv->offsets[i] + DRP_INTERRUPT_STATUS, + &drp_error); + if (ret) + return irq_rc; + + if (drp_error & SB_ECC_ERROR) { + edac_printk(KERN_CRIT, EDAC_LLCC, + "Single Bit Error detected in Data Ram\n"); + ret = dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i); + if (!ret) + irq_rc = IRQ_HANDLED; + } else if (drp_error & DB_ECC_ERROR) { + edac_printk(KERN_CRIT, EDAC_LLCC, + "Double Bit Error detected in Data Ram\n"); + ret = dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i); + if (!ret) + irq_rc = IRQ_HANDLED; + } + + /* Look for Tag RAM errors */ + ret = regmap_read(drv->regmap, + drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + &trp_error); + if (ret) + return irq_rc; + + if (trp_error & SB_ECC_ERROR) { + edac_printk(KERN_CRIT, EDAC_LLCC, + "Single Bit Error detected in Tag Ram\n"); + ret = dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i); + if (!ret) + irq_rc = IRQ_HANDLED; + } else if (trp_error & DB_ECC_ERROR) { + edac_printk(KERN_CRIT, EDAC_LLCC, + "Double Bit Error detected in Tag Ram\n"); + ret = dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i); + if (!ret) + irq_rc = IRQ_HANDLED; + } + } + + return irq_rc; +} + +static void llcc_edac_reg_data_init(struct llcc_edac_reg_data *edac_reg) +{ + + struct llcc_edac_reg_data *reg_data; + + /* Initialize register info for LLCC_DRAM_CE */ + reg_data = &edac_reg[LLCC_DRAM_CE]; + reg_data->err_name = "DRAM Single-bit"; + reg_data->reg_cnt = DRP_SYN_REG_CNT; + reg_data->synd_reg = DRP_ECC_SB_ERR_SYN0; + reg_data->err_status_reg = DRP_ECC_ERROR_STATUS1; + reg_data->err_count_mask = ECC_SB_ERR_COUNT_MASK; + reg_data->err_count_shift = ECC_SB_ERR_COUNT_SHIFT; + reg_data->err_ways_status = DRP_ECC_ERROR_STATUS0; + reg_data->err_ways_mask = ECC_SB_ERR_WAYS_MASK; + + /* Initialize register info for LLCC_DRAM_UE */ + reg_data = &edac_reg[LLCC_DRAM_UE]; + reg_data->err_name = "DRAM Double-bit"; + reg_data->reg_cnt = DRP_SYN_REG_CNT; + reg_data->synd_reg = DRP_ECC_DB_ERR_SYN0; + reg_data->err_status_reg = DRP_ECC_ERROR_STATUS1; + reg_data->err_count_mask = ECC_DB_ERR_COUNT_MASK; + reg_data->err_ways_status = DRP_ECC_ERROR_STATUS0; + reg_data->err_ways_mask = ECC_DB_ERR_WAYS_MASK; + reg_data->err_ways_shift = ECC_DB_ERR_WAYS_SHIFT; + + /* Initialize register info for LLCC_TRAM_CE */ + reg_data = &edac_reg[LLCC_TRAM_CE]; + reg_data->err_name = "TRAM Single-bit"; + reg_data->reg_cnt = TRP_SYN_REG_CNT; + reg_data->synd_reg = TRP_ECC_SB_ERR_SYN0; + reg_data->err_status_reg = TRP_ECC_ERROR_STATUS1; + reg_data->err_count_mask = ECC_SB_ERR_COUNT_MASK; + reg_data->err_count_shift = ECC_SB_ERR_COUNT_SHIFT; + reg_data->err_ways_status = TRP_ECC_ERROR_STATUS0; + reg_data->err_ways_mask = ECC_SB_ERR_WAYS_MASK; + + /* Initialize register info for LLCC_TRAM_UE */ + reg_data = &edac_reg[LLCC_TRAM_UE]; + reg_data->err_name = "TRAM Double-bit"; + reg_data->reg_cnt = TRP_SYN_REG_CNT; + reg_data->synd_reg = TRP_ECC_DB_ERR_SYN0; + reg_data->err_status_reg = TRP_ECC_ERROR_STATUS1; + reg_data->err_count_mask = ECC_DB_ERR_COUNT_MASK; + reg_data->err_ways_status = TRP_ECC_ERROR_STATUS0; + reg_data->err_ways_mask = ECC_DB_ERR_WAYS_MASK; + reg_data->err_ways_shift = ECC_DB_ERR_WAYS_SHIFT; +} + +static int qcom_llcc_edac_probe(struct platform_device *pdev) +{ + struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data; + struct edac_device_ctl_info *edev_ctl; + struct device *dev = &pdev->dev; + int ecc_irq; + int rc; + + /* Initialize register set for the error types*/ + llcc_driv_data->edac_reg = devm_kcalloc(dev, LLCC_ERR_TYPE_MAX, + sizeof(struct llcc_edac_reg_data), + GFP_KERNEL); + llcc_edac_reg_data_init(llcc_driv_data->edac_reg); + + rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap); + if (rc) + return rc; + + /* Allocate edac control info */ + edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank", + llcc_driv_data->num_banks, 1, + NULL, 0, + edac_device_alloc_index()); + + if (!edev_ctl) + return -ENOMEM; + + edev_ctl->dev = dev; + edev_ctl->mod_name = dev_name(dev); + edev_ctl->dev_name = dev_name(dev); + edev_ctl->ctl_name = "llcc"; + edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE; + edev_ctl->pvt_info = llcc_driv_data; + + rc = edac_device_add_device(edev_ctl); + if (rc) + goto out_mem; + + platform_set_drvdata(pdev, edev_ctl); + + /* Request for ecc irq */ + ecc_irq = llcc_driv_data->ecc_irq; + if (ecc_irq < 0) { + rc = -ENODEV; + goto out_dev; + } + rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, + IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); + if (rc) + goto out_dev; + + return rc; + +out_dev: + edac_device_del_device(edev_ctl->dev); +out_mem: + edac_device_free_ctl_info(edev_ctl); + + return rc; +} + +static int qcom_llcc_edac_remove(struct platform_device *pdev) +{ + struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&pdev->dev); + + edac_device_del_device(edev_ctl->dev); + edac_device_free_ctl_info(edev_ctl); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static const struct of_device_id qcom_llcc_edac_match_table[] = { +#ifdef EDAC_QCOM_LLCC + { .compatible = "qcom,llcc-edac" }, +#endif + { }, +}; + +static struct platform_driver qcom_llcc_edac_driver = { + .probe = qcom_llcc_edac_probe, + .remove = qcom_llcc_edac_remove, + .driver = { + .name = "qcom_llcc_edac", + .of_match_table = qcom_llcc_edac_match_table, + }, +}; +module_platform_driver(qcom_llcc_edac_driver); + +MODULE_DESCRIPTION("QCOM EDAC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 2e4b34d..25096e0 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -84,6 +84,7 @@ struct llcc_drv_data { struct regmap *regmap; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; + struct llcc_edac_reg_data *edac_reg; struct mutex lock; u32 cfg_size; u32 max_slices; @@ -93,6 +94,30 @@ struct llcc_drv_data { int ecc_irq; }; +/** + * llcc_edac_reg_data - llcc edac registers data for each error type + * @err_name: name of the error + * @reg_cnt: number of registers + * @synd_reg: syndrome register address + * @err_status_reg: Status register address to read the error count + * @err_count_mask: Mask value to get the error count + * @err_count_shift: Shift value to get the error count + * @err_ways_status: Status register address to read error ways + * @err_ways_mask: Mask value to get the error ways + * @err_ways_shift: Shift value to get the error ways + */ +struct llcc_edac_reg_data { + char *err_name; + int reg_cnt; + int synd_reg; + int err_status_reg; + int err_count_mask; + int err_count_shift; + int err_ways_status; + int err_ways_mask; + int err_ways_shift; +}; + #if IS_ENABLED(CONFIG_QCOM_LLCC) /** * llcc_slice_getd - get llcc slice descriptor From patchwork Sat Aug 18 00:08:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkata Narendra Kumar Gutta X-Patchwork-Id: 10569447 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A9D8109C for ; Sat, 18 Aug 2018 00:09:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EEC712BA76 for ; Sat, 18 Aug 2018 00:09:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CC6C22BAA4; Sat, 18 Aug 2018 00:09:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 12F382BA76 for ; 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Sat, 18 Aug 2018 00:08:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1534550927; bh=aLZeTp6N7J45OWOIwIEW2ZLhcBoEwiP0cn+Srs879R8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EuKDx3a28ssryRhxGLUmYr+Nn+/MTCFyzoBi+XIYcuZ6V1jSicV6KX5jTgxTmFFjl VNBjB/27RPCEqsMHHZZGBWa/S1APe2aZj2rWNaUdUe6Ro+RFREmmsg/iVnEl2hRPYj O4qmOn+YT6E85tmsfTNfNhC/VvyN23oJjcDr3E9U= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 95A856249E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vnkgutta@codeaurora.org From: Venkata Narendra Kumar Gutta To: robh@kernel.org, mchehab@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, rishabhb@codeaurora.org, bp@alien8.de, evgreen@chromium.org Cc: Venkata Narendra Kumar Gutta Subject: [PATCH v2 4/4] dt-bindigs: msm: Update documentation of qcom,llcc Date: Fri, 17 Aug 2018 17:08:35 -0700 Message-Id: <1534550915-18230-5-git-send-email-vnkgutta@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534550915-18230-1-git-send-email-vnkgutta@codeaurora.org> References: <1534550915-18230-1-git-send-email-vnkgutta@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add reg-names and interrupts for LLCC documentation and the usage examples. llcc broadcast base is added in addition to llcc base, which is used for llcc broadcast writes. Signed-off-by: Venkata Narendra Kumar Gutta --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt index 5e85749..b4b1c86 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -18,9 +18,22 @@ Properties: Value Type: Definition: Start address and the the size of the register region. +- reg-names: + Usage: required + Value Type: + Definition: Register region names. Must be "llcc_base", "llcc_bcast_base". + +- interrupts: + Usage: required + Definition: The interrupt is associated with the llcc edac device. + It's used for llcc cache single and double bit error detection + and reporting. + Example: cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x250000>; + reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; + reg-names = "llcc_base", "llcc_bcast_base"; + interrupts = ; };