From patchwork Sun Feb 9 03:32:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13966611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 120D5C02198 for ; Sun, 9 Feb 2025 03:34:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tgy44-0005sD-Mt; Sat, 08 Feb 2025 22:33:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tgy3p-0005pA-Hk; Sat, 08 Feb 2025 22:32:45 -0500 Received: from mail-pl1-f177.google.com ([209.85.214.177]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tgy3k-0001PT-Go; Sat, 08 Feb 2025 22:32:43 -0500 Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-21f6d2642faso19270845ad.1; Sat, 08 Feb 2025 19:32:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739071958; x=1739676758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=40hOV1XLmKGFFIuKf1SgFgrMU4Y3jviwBqNER7UevnM=; b=tbFTHo7Zr34NV16sxBEzvLubokqveC+FpZTN1CZjG5hJb7umQC7c7HZKRT2alM2T25 dTu42Sl3tvQ6M9n+6aPy69of2S7nKnrsSyDlzZ8AdvJkrFCk9AEA2hMUdDfpJfJMpn97 aBVjDy4U/IGzhV+x5q6P4SRKvhfLxQwFSCu+U7JHxIr2EmhnzQwkz0HpmV0oDs18RCc3 WXR/xtYhEQSCQojHAOVVrlHtgCD74VbEVAJsmPHg77RGZeLQLwULILGxAkxyoW/4tsKi i27idnB/UPeBoR3NbYKd9GSdkpiOPMorKV9dwUgj+9z+l8RPf2HcQD/aZInVJB/2E9Ql KBAQ== X-Forwarded-Encrypted: i=1; AJvYcCVw7W3svtQqN6Y2RutvgMDNXZWGNnn4kwL/WVVLU/rw+ZtKPl7NJsUJucKKclnPLGNIA7KF/+PzCQ==@nongnu.org X-Gm-Message-State: AOJu0YyXz0vLcHmADaPNF3wjb9LMxHzx510K3IHyUyLNpP8N6LzQikt1 SdxF18eb9ellu8eg8oASLE4DQ5stjRK03N5GjIjVKVFQuW6w/Cq/YVec8Gh3 X-Gm-Gg: ASbGnctMe7LJIW6zXUpG3HpiCMopOBqS7ga6OIWK5f8XNSMG1JKTjWKuAl7DQpuLNVP up24VQdd6y57ktvFSxb4xVYB7rhrl9lWQ8ZikZFXmBZmxQ1HolYgrqyueVZsLiIeS5KwkKFlWgT v5QCchmsisRPa6kB84PX3D8n3UfC/KodjadNd7lMjAtzLyZ3TpJRZaQ96XoNpj5vmDE4TXnbrBa b4kXjNNNC8AtCkt2TNMW2RqdzyrWsbVMtsAntO/joY1A3MCOU6JLuC8+n/R9iRjajM79bkGnddT lGKwo8Mo/xA7oZJkFuh6NwaOe0fPkP/+nn43JFALty0Z0AM= X-Google-Smtp-Source: AGHT+IH+ALL7cX3DTai2279KB0dFYtI4aVNWY7NNbmRvoL6IvzpattoDFsNJlsAfIqIRWpUroDR/Dw== X-Received: by 2002:a05:6a21:9211:b0:1ed:a4e2:8638 with SMTP id adf61e73a8af0-1ee03b78d70mr16423609637.39.1739071958132; Sat, 08 Feb 2025 19:32:38 -0800 (PST) Received: from localhost.localdomain ([2607:fb90:9e97:4903:dc10:4530:8a3f:fdb6]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-ad5453e2366sm1333610a12.47.2025.02.08.19.32.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Feb 2025 19:32:37 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , Zhao Liu , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH RFC 1/4] cpu-exec: support single-step without debug Date: Sat, 8 Feb 2025 19:32:30 -0800 Message-ID: <20250209033233.53853-2-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20250209033233.53853-1-j@getutm.app> References: <20250209033233.53853-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.177; envelope-from=osy86dev@gmail.com; helo=mail-pl1-f177.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.07, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently, single-stepping is tied to GDB debugging. This means that when EXCP_DEBUG is returned, a debug exception is triggered in many cases. We define a new EXCP_SINGLESTEP to differentiate the case where we want a single step to not be tied to a debug exception. We also define a new flag for cpu->singlestep_enabled called SSTEP_NODEBUG which is set when we want to use single-step for purposes other than debugging. Signed-off-by: Joelle van Dyne --- include/exec/cpu-common.h | 1 + include/hw/core/cpu.h | 1 + target/arm/internals.h | 3 ++- accel/tcg/cpu-exec.c | 35 +++++++++++++++++++++++++---------- cpu-target.c | 7 +++++-- 5 files changed, 34 insertions(+), 13 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index b1d76d6985..e1c798b07d 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -22,6 +22,7 @@ #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ +#define EXCP_SINGLESTEP 0x10006 /* singlestep without debugging */ void cpu_exec_init_all(void); void cpu_exec_step_atomic(CPUState *cpu); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fb397cdfc5..e3c8450f8f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1072,6 +1072,7 @@ void qemu_init_vcpu(CPUState *cpu); #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ +#define SSTEP_NODEBUG 0x8 /* Single-stepping is not for debugging */ /** * cpu_single_step: diff --git a/target/arm/internals.h b/target/arm/internals.h index 863a84edf8..961cd9927a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -57,7 +57,8 @@ static inline bool excp_is_internal(int excp) || excp == EXCP_HALTED || excp == EXCP_EXCEPTION_EXIT || excp == EXCP_KERNEL_TRAP - || excp == EXCP_SEMIHOST; + || excp == EXCP_SEMIHOST + || excp == EXCP_SINGLESTEP; } /* diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8b773d8847..6b4e63e69e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -349,7 +349,7 @@ static bool check_for_breakpoints_slow(CPUState *cpu, vaddr pc, * so that one could (gdb) singlestep into the guest kernel's * architectural breakpoint handler. */ - if (cpu->singlestep_enabled) { + if (cpu->singlestep_enabled && !(cpu->singlestep_enabled & SSTEP_NODEBUG)) { return false; } @@ -529,7 +529,11 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) * is handled in cpu_handle_exception. */ if (unlikely(cpu->singlestep_enabled) && cpu->exception_index == -1) { - cpu->exception_index = EXCP_DEBUG; + if (!(cpu->singlestep_enabled & SSTEP_NODEBUG)) { + cpu->exception_index = EXCP_DEBUG; + } else { + cpu->exception_index = EXCP_SINGLESTEP; + } cpu_loop_exit(cpu); } @@ -781,13 +785,20 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) cpu->exception_index = -1; if (unlikely(cpu->singlestep_enabled)) { - /* - * After processing the exception, ensure an EXCP_DEBUG is - * raised when single-stepping so that GDB doesn't miss the - * next instruction. - */ - *ret = EXCP_DEBUG; - cpu_handle_debug_exception(cpu); + if (!(cpu->singlestep_enabled & SSTEP_NODEBUG)) { + /* + * After processing the exception, ensure an EXCP_DEBUG is + * raised when single-stepping so that GDB doesn't miss the + * next instruction. + */ + *ret = EXCP_DEBUG; + cpu_handle_debug_exception(cpu); + } else { + /* + * In case of non-debug single step, just return + */ + *ret = EXCP_SINGLESTEP; + } return true; } } else if (!replay_has_interrupt()) { @@ -892,7 +903,11 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * next instruction. */ if (unlikely(cpu->singlestep_enabled)) { - cpu->exception_index = EXCP_DEBUG; + if (!(cpu->singlestep_enabled & SSTEP_NODEBUG)) { + cpu->exception_index = EXCP_DEBUG; + } else { + cpu->exception_index = EXCP_SINGLESTEP; + } bql_unlock(); return true; } diff --git a/cpu-target.c b/cpu-target.c index 667688332c..6293477ed9 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -322,9 +322,12 @@ void list_cpus(void) CPU loop after each instruction */ void cpu_single_step(CPUState *cpu, int enabled) { - if (cpu->singlestep_enabled != enabled) { - cpu->singlestep_enabled = enabled; + int previous = cpu->singlestep_enabled; + bool prev_debug_en = previous && !(previous & SSTEP_NODEBUG); + bool cur_debug_en = enabled && !(enabled & SSTEP_NODEBUG); + cpu->singlestep_enabled = enabled; + if (prev_debug_en != cur_debug_en) { #if !defined(CONFIG_USER_ONLY) const AccelOpsClass *ops = cpus_get_accel(); if (ops->update_guest_debug) { From patchwork Sun Feb 9 03:32:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 13966610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC6A9C021A1 for ; Sun, 9 Feb 2025 03:33:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tgy3z-0005qV-4o; Sat, 08 Feb 2025 22:32:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tgy3p-0005p9-Hh for qemu-devel@nongnu.org; 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Sat, 08 Feb 2025 19:32:40 -0800 (PST) Received: from localhost.localdomain ([2607:fb90:9e97:4903:dc10:4530:8a3f:fdb6]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-ad5453e2366sm1333610a12.47.2025.02.08.19.32.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Feb 2025 19:32:40 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , Zhao Liu , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Mahmoud Mandour , Pierrick Bouvier , Peter Xu , David Hildenbrand Subject: [PATCH RFC 2/4] cpu-target: support emulation from non-TCG accels Date: Sat, 8 Feb 2025 19:32:31 -0800 Message-ID: <20250209033233.53853-3-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20250209033233.53853-1-j@getutm.app> References: <20250209033233.53853-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.178; envelope-from=osy86dev@gmail.com; helo=mail-pl1-f178.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.07, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We create a toggle to allow TCG emulation to be used dynamically when running other accelerators. Tracking dirty code can be expensive so we need to flush the TLBs and TBs every time we toggle emulation mode. Plugin support is currently disabled when running in this mode. Signed-off-by: Joelle van Dyne --- include/hw/core/cpu.h | 10 ++++++++++ accel/tcg/plugin-gen.c | 4 ++++ accel/tcg/tb-maint.c | 2 +- accel/tcg/tcg-accel-ops.c | 3 ++- cpu-target.c | 13 +++++++++++++ plugins/core.c | 12 ++++++++++++ system/physmem.c | 5 +++-- 7 files changed, 45 insertions(+), 4 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e3c8450f8f..dbbaca06ee 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -569,6 +569,9 @@ struct CPUState { /* track IOMMUs whose translations we've cached in the TCG TLB */ GArray *iommu_notifiers; + /* doing emulation when not in TCG backend */ + bool emulation_enabled; + /* * MUST BE LAST in order to minimize the displacement to CPUArchState. */ @@ -1083,6 +1086,13 @@ void qemu_init_vcpu(CPUState *cpu); */ void cpu_single_step(CPUState *cpu, int enabled); +/** + * cpu_emulate: + * @cpu: CPU to set to emulation mode + * @enabled: enable emulation mode + */ +void cpu_emulate(CPUState *cpu, bool enabled); + /* Breakpoint/watchpoint flags */ #define BP_MEM_READ 0x01 #define BP_MEM_WRITE 0x02 diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 7e5f040bf7..e07dffeb00 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -388,6 +388,10 @@ bool plugin_gen_tb_start(CPUState *cpu, const DisasContextBase *db) { struct qemu_plugin_tb *ptb; + if (cpu->emulation_enabled) { + return false; + } + if (!test_bit(QEMU_PLUGIN_EV_VCPU_TB_TRANS, cpu->plugin_state->event_mask)) { return false; diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 3f1bebf6ab..14d4bed347 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -791,7 +791,7 @@ done: void tb_flush(CPUState *cpu) { - if (tcg_enabled()) { + if (tcg_enabled() || unlikely(cpu->emulation_enabled)) { unsigned tb_flush_count = qatomic_read(&tb_ctx.tb_flush_count); if (cpu_in_serial_context(cpu)) { diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 6e3f1fa92b..3c07407ccf 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -32,6 +32,7 @@ #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "qemu/timer.h" +#include "exec/cpu-common.h" #include "exec/exec-all.h" #include "exec/hwaddr.h" #include "exec/tb-flush.h" @@ -74,7 +75,7 @@ void tcg_cpu_destroy(CPUState *cpu) int tcg_cpu_exec(CPUState *cpu) { int ret; - assert(tcg_enabled()); + assert(tcg_enabled() || cpu->emulation_enabled); cpu_exec_start(cpu); ret = cpu_exec(cpu); cpu_exec_end(cpu); diff --git a/cpu-target.c b/cpu-target.c index 6293477ed9..8df75e915a 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -339,6 +339,19 @@ void cpu_single_step(CPUState *cpu, int enabled) } } +void cpu_emulate(CPUState *cpu, bool enabled) +{ + if (cpu->emulation_enabled != enabled) { + cpu->emulation_enabled = enabled; + + if (enabled) { + /* FIXME: track dirty code to improve performance */ + tb_flush(cpu); + tlb_flush(cpu); + } + } +} + void cpu_abort(CPUState *cpu, const char *fmt, ...) { va_list ap; diff --git a/plugins/core.c b/plugins/core.c index bb105e8e68..dee6ffd722 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -55,6 +55,10 @@ struct qemu_plugin_ctx *plugin_id_to_ctx_locked(qemu_plugin_id_t id) static void plugin_cpu_update__async(CPUState *cpu, run_on_cpu_data data) { + if (cpu->emulation_enabled) { + return; + } + bitmap_copy(cpu->plugin_state->event_mask, &data.host_ulong, QEMU_PLUGIN_EV_MAX); tcg_flush_jmp_cache(cpu); @@ -499,6 +503,10 @@ qemu_plugin_vcpu_syscall(CPUState *cpu, int64_t num, uint64_t a1, uint64_t a2, struct qemu_plugin_cb *cb, *next; enum qemu_plugin_event ev = QEMU_PLUGIN_EV_VCPU_SYSCALL; + if (cpu->emulation_enabled) { + return; + } + if (!test_bit(ev, cpu->plugin_state->event_mask)) { return; } @@ -521,6 +529,10 @@ void qemu_plugin_vcpu_syscall_ret(CPUState *cpu, int64_t num, int64_t ret) struct qemu_plugin_cb *cb, *next; enum qemu_plugin_event ev = QEMU_PLUGIN_EV_VCPU_SYSCALL_RET; + if (cpu->emulation_enabled) { + return; + } + if (!test_bit(ev, cpu->plugin_state->event_mask)) { return; } diff --git a/system/physmem.c b/system/physmem.c index 67c9db9daa..4bb2976646 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -2696,7 +2696,9 @@ static void tcg_commit_cpu(CPUState *cpu, run_on_cpu_data data) CPUAddressSpace *cpuas = data.host_ptr; cpuas->memory_dispatch = address_space_to_dispatch(cpuas->as); - tlb_flush(cpu); + if (tcg_enabled() || cpu->emulation_enabled) { + tlb_flush(cpu); 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Sat, 08 Feb 2025 19:32:42 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Cameron Esfahani , Roman Bolshakov , Phil Dennis-Jordan , Paolo Bonzini , Peter Xu , David Hildenbrand , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH RFC 3/4] hvf: arm: emulate instruction when ISV=0 Date: Sat, 8 Feb 2025 19:32:32 -0800 Message-ID: <20250209033233.53853-4-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20250209033233.53853-1-j@getutm.app> References: <20250209033233.53853-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.48; envelope-from=osy86dev@gmail.com; helo=mail-pj1-f48.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.07, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On a data abort, the processor will try to decode the faulting instruction so the hypervisor can emulate the read/write. However, it is not always able to do this and ISV=0 whenever the instruction is not decoded. This is the case for example if the faulting instruction is SIMD or a LDP/STP. When this happens, we can use TCG to emulate the faulting instruction. This is needed if the processor uses one of these instructions to access memory that is currently unmapped such as with VGA VRAM. Signed-off-by: Joelle van Dyne --- include/system/hvf_int.h | 2 +- target/arm/hvf_arm.h | 5 ++ accel/hvf/hvf-accel-ops.c | 2 +- system/physmem.c | 2 +- target/arm/hvf/hvf.c | 100 ++++++++++++++++++++++++++++++++++++-- target/i386/hvf/hvf.c | 2 +- 6 files changed, 106 insertions(+), 7 deletions(-) diff --git a/include/system/hvf_int.h b/include/system/hvf_int.h index 42ae18433f..7b85dbc495 100644 --- a/include/system/hvf_int.h +++ b/include/system/hvf_int.h @@ -64,7 +64,7 @@ void assert_hvf_ok_impl(hv_return_t ret, const char *file, unsigned int line, const char *exp); #define assert_hvf_ok(EX) assert_hvf_ok_impl((EX), __FILE__, __LINE__, #EX) const char *hvf_return_string(hv_return_t ret); -int hvf_arch_init(void); +int hvf_arch_init(MachineState *ms); hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range); int hvf_arch_init_vcpu(CPUState *cpu); void hvf_arch_vcpu_destroy(CPUState *cpu); diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index 26c717b382..6ebef31390 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -41,4 +41,9 @@ static inline uint32_t hvf_arm_get_max_ipa_bit_size(void) #endif +/** + * hvf_arm_init_emulator() - initialize TCG emulator + */ +void hvf_arm_init_emulator(int splitwx, unsigned max_cpus); + #endif diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 945ba72051..1caf713118 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -346,7 +346,7 @@ static int hvf_accel_init(MachineState *ms) hvf_state = s; memory_listener_register(&hvf_memory_listener, &address_space_memory); - return hvf_arch_init(); + return hvf_arch_init(ms); } static inline int hvf_gdbstub_sstep_flags(void) diff --git a/system/physmem.c b/system/physmem.c index 4bb2976646..950cac5971 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -771,7 +771,7 @@ void cpu_address_space_init(CPUState *cpu, int asidx, newas = &cpu->cpu_ases[asidx]; newas->cpu = cpu; newas->as = as; - if (tcg_enabled()) { + if (tcg_enabled() || hvf_enabled()) { newas->tcg_as_listener.log_global_after_sync = tcg_log_global_after_sync; newas->tcg_as_listener.commit = tcg_commit; newas->tcg_as_listener.name = "tcg"; diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 28886970c9..2c70e691fb 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -37,6 +37,17 @@ #include "gdbstub/enums.h" +#if defined(CONFIG_TCG) +#include "accel/tcg/internal-common.h" +#include "accel/tcg/tcg-accel-ops.h" +#include "exec/tb-flush.h" +#include "hw/core/cpu.h" +#include "qapi/error.h" +#include "qemu/units.h" +#include "system/tcg.h" +#include "tcg/startup.h" +#endif /* defined(CONFIG_TCG) */ + #define MDSCR_EL1_SS_SHIFT 0 #define MDSCR_EL1_MDE_SHIFT 15 @@ -150,6 +161,17 @@ void hvf_arm_init_debug(void) g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps); } +#if defined(CONFIG_TCG) +void hvf_arm_init_emulator(int splitwx, unsigned max_cpus) +{ + mttcg_enabled = true; + page_init(); + tb_htable_init(); + tcg_init(64 * MiB, splitwx, max_cpus); + tcg_prologue_init(); +} +#endif /* defined(CONFIG_TCG) */ + #define HVF_SYSREG(crn, crm, op0, op1, op2) \ ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) @@ -968,6 +990,9 @@ void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) void hvf_arch_vcpu_destroy(CPUState *cpu) { +#if defined(CONFIG_TCG) + tcg_exec_unrealizefn(cpu); +#endif } hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range) @@ -1060,13 +1085,26 @@ int hvf_arch_init_vcpu(CPUState *cpu) arm_cpu->isar.id_aa64mmfr0); assert_hvf_ok(ret); + /* enable TCG emulator */ +#if defined(CONFIG_TCG) + tcg_register_thread(); + tcg_cpu_init_cflags(cpu, current_machine->smp.max_cpus > 1); + tcg_exec_realizefn(cpu, &error_fatal); +#endif + return 0; } void hvf_kick_vcpu_thread(CPUState *cpu) { - cpus_kick_thread(cpu); - hv_vcpus_exit(&cpu->accel->fd, 1); + if (cpu->emulation_enabled) { + cpu_exit(cpu); + } else { + cpus_kick_thread(cpu); + if (cpu->accel) { + hv_vcpus_exit(&cpu->accel->fd, 1); + } + } } static void hvf_raise_exception(CPUState *cpu, uint32_t excp, @@ -1881,6 +1919,50 @@ static inline uint64_t sign_extend(uint64_t value, uint32_t bits) return (uint64_t)((int64_t)(value << (64 - bits)) >> (64 - bits)); } +#if defined(CONFIG_TCG) +static int emulate_single_instruction(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + int prev_ss_enable = cpu->singlestep_enabled; + int ret; + + cpu_synchronize_state(cpu); + arm_rebuild_hflags(env); + cpu_emulate(cpu, true); + cpu_single_step(cpu, SSTEP_NODEBUG | SSTEP_ENABLE); + do { + if (cpu_can_run(cpu)) { + bql_unlock(); + ret = tcg_cpu_exec(cpu); + bql_lock(); + if (ret == EXCP_ATOMIC) { + bql_unlock(); + cpu_exec_step_atomic(cpu); + bql_lock(); + ret = 0; + } + /* retry if we got an interrupt */ + if (ret != EXCP_INTERRUPT) { + break; + } + } + + qatomic_set_mb(&cpu->exit_request, 0); + qemu_wait_io_event(cpu); + } while (!cpu->unplug || cpu_can_run(cpu)); + cpu_single_step(cpu, prev_ss_enable); + cpu_emulate(cpu, false); + cpu->accel->dirty = true; + flush_cpu_state(cpu); + if (!ret && prev_ss_enable) { + /* if single-stepping, always return EXCP_DEBUG */ + ret = EXCP_DEBUG; + } + return ret; +} +#endif + int hvf_vcpu_exec(CPUState *cpu) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -1993,7 +2075,15 @@ int hvf_vcpu_exec(CPUState *cpu) break; } +#if defined(CONFIG_TCG) + if (unlikely(!isv)) { + ret = emulate_single_instruction(cpu); + advance_pc = false; + break; + } +#else assert(isv); +#endif if (iswrite) { val = hvf_get_reg(cpu, srt); @@ -2124,7 +2214,7 @@ static void hvf_vm_state_change(void *opaque, bool running, RunState state) } } -int hvf_arch_init(void) +int hvf_arch_init(MachineState *ms) { hvf_state->vtimer_offset = mach_absolute_time(); vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer); @@ -2132,6 +2222,10 @@ int hvf_arch_init(void) hvf_arm_init_debug(); +#if defined(CONFIG_TCG) + hvf_arm_init_emulator(0, ms->smp.max_cpus); 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Sat, 08 Feb 2025 19:32:44 -0800 (PST) From: Joelle van Dyne To: qemu-devel@nongnu.org Cc: Joelle van Dyne , Paolo Bonzini , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH RFC 4/4] hw/arm/virt: enable VGA Date: Sat, 8 Feb 2025 19:32:33 -0800 Message-ID: <20250209033233.53853-5-j@getutm.app> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20250209033233.53853-1-j@getutm.app> References: <20250209033233.53853-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.46; envelope-from=osy86dev@gmail.com; helo=mail-pj1-f46.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.07, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Joelle van Dyne --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 256013ca80..6818c54787 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -11,6 +11,7 @@ config ARM_VIRT imply TPM_TIS_I2C imply NVDIMM imply IOMMUFD + imply VIRTIO_VGA select ARM_GIC select ACPI select ARM_SMMUV3