From patchwork Sun Feb 9 04:16:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13966629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20A5BC0219D for ; Sun, 9 Feb 2025 04:20:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DvFsqgBHoepkWBjGC1yP+KOn/8qryanxa+3zb4U83Ao=; b=sIoRVCvSAmu2oi0qiWhceHEbpP 3Bn0E7qICAY1y0mb+QnBgT2T0StCQtZ7GJquqZq8zAdLoj6BPlGrCRGxCNRiKZ+yzav6j0b9SisRZ ABeZapSShWfB+eqKRATnX+yeUwR9Ve9UCRAuZkZzHQkqhw8XkWp7g2+WPX2hMeCUMTD4Ehq3VdanG ypLPHfVyRmOaYhTwTxidUnNWHvtg9BSt2iT8Ap5+6GxhYE6KNkECqT7QlLXY0ay1BffTWtZnvIUl2 2O/XoBXiEcDn4lMBTVyHuZw+vnAag30MNDzIM4Hnuk9HKSz9oIHB7bniVRxRYZ3QjRVGidQxf4gUK //v85Jvg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tgynf-0000000E33D-3YUm; Sun, 09 Feb 2025 04:20:07 +0000 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tgyl1-0000000E2H1-0IJn for linux-arm-kernel@lists.infradead.org; Sun, 09 Feb 2025 04:17:24 +0000 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2f9ba87f5d4so4708276a91.3 for ; Sat, 08 Feb 2025 20:17:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1739074642; x=1739679442; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DvFsqgBHoepkWBjGC1yP+KOn/8qryanxa+3zb4U83Ao=; b=ZhA1QhQF6RbBN70YHFPxplw9pQyOyDyCcHQUzrRG1Zq75CgTyYW7SIi/4ql2bVxHc9 jBoStP4eaHWs39I/UVCQtuQVNIHnrMIOUTfsL0iGE8lBnYq7fIsttOQVVrsFLLSEt1bf KGu4NDFdsC74RMNu7SlzW3FKdShCpytmvU0pvTje0gLo5cYALvN/dbmT4NI4RMlv+M7g Cg8Ua81FkQRUIOAVcBeCIzIryR3yIVzOO+HIaQg9T7oYh6Up8PK1jghvoU7GgPIL2ECL xGStANAxnPwh5obYJy2QW/6rhrCJn0ueL1Ug6TsQYM2ieVyR3U3ymgowu1n4cEXAgtgB uedA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739074642; x=1739679442; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DvFsqgBHoepkWBjGC1yP+KOn/8qryanxa+3zb4U83Ao=; b=BsXjScLQimpIb9bzBlLke8uce3g1G0pWwMeKvfR7xu5aNM+uHsKnc62Lk7C5jEyxYG ASftuf35zp1ZLEeiIhLpBJIYrVNLoa4NW2FnvPiVthcRmnXVejRsoGNG8Zxr/EfJRNaz 1PTsXXZWjdcgIyqncAQGtjumyZCj2aMQMbtq+J9Nlp6DHBQpAZI8k60B5EFH4hOYzBxi aLcZigoXuiEl00UZaxCgQyuq7U5KpRVYVu4uo7ZS/12uwJZrSTsvyTOI2AhbKcL6oMW7 NwbqhkASOeQZ+WcwR96U299qBWJ1+WHOVu8adI/X0sjrJlxQDyXE+X2af5Jo43+amvFO rgJQ== X-Forwarded-Encrypted: i=1; AJvYcCWqWa5+roFlJr2JR0vh3KGNbPc8y9p6wBZD62ld9vKYd07T1oM5pKkvcEcVQuhcgAU4ebL15Oc+gAU+1O4SK0xl@lists.infradead.org X-Gm-Message-State: AOJu0Yy74V2Q+gLIq1urtU00o8giwLS2wVsPj+2Hh8U6dYsTbibM1yAl ic1eiiE9/kFAWIORHIyczcVxNlz+CzFhPEuhi7PGmoI9qvKWUztY6Q/QNlBsyho= X-Gm-Gg: ASbGnctqo2MV8jgykRQNBPnKNTayw2zMzCmavMs5kchKLX7p6ePovuFyNx1R4l0X9U9 eXxMRgRk4J/1geKUftS++mBvTSprNh/+WD8QenWuFIg2ptoJI73+jHHu4ItWtLO6MFXh+HpwjqL egmsZLOOhlbpAuz+am8cpfLWoqmHvC5s2IWlxL08IsqeuTSWs9ooss3cZQbQOxFvV0Yh4PJvll8 lC+gIe26Q7lR+4RPJUYWHfVYJC/E0Gzyr+b8bL0LzWQzh4XoI1aLhryCTYBKFY9vHWPobBjgHZm B1B8SmgZm+NkKZ0lABq51ZnmHF+H0ucqufpKMznegSDlMXteGIWvBoU= X-Google-Smtp-Source: AGHT+IHRXdIPs1mvVVeCpBykzAl+ifFcG5qlvMFYrTkFKgREylWnQV7fAuN/+eShJoWgxmV452gK/Q== X-Received: by 2002:a05:6a00:b41:b0:730:8a0a:9f06 with SMTP id d2e1a72fcca58-7308a0aad32mr287596b3a.16.1739074642169; Sat, 08 Feb 2025 20:17:22 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73073eba116sm1898410b3a.124.2025.02.08.20.17.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2025 20:17:21 -0800 (PST) From: Anup Patel To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: hpa@zytor.com, Marc Zyngier , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Palmer Dabbelt , Paul Walmsley , Atish Patra , Andrew Jones , Sunil V L , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel Subject: [PATCH v5 01/11] irqchip/riscv-imsic: Set irq_set_affinity for IMSIC base Date: Sun, 9 Feb 2025 09:46:45 +0530 Message-ID: <20250209041655.331470-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250209041655.331470-1-apatel@ventanamicro.com> References: <20250209041655.331470-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250208_201723_172926_F0FE36B4 X-CRM114-Status: GOOD ( 14.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Andrew Jones Instead of using imsic_irq_set_affinity() for leaf MSI domains, use imsic_irq_set_affinity() for the non-leaf IMSIC base domain and use irq_chip_set_affinity_parent() for leaf MSI domains. Signed-off-by: Andrew Jones Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-imsic-platform.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index c708780e8760..5d7c30ad8855 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -96,9 +96,8 @@ static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask bool force) { struct imsic_vector *old_vec, *new_vec; - struct irq_data *pd = d->parent_data; - old_vec = irq_data_get_irq_chip_data(pd); + old_vec = irq_data_get_irq_chip_data(d); if (WARN_ON(!old_vec)) return -ENOENT; @@ -116,13 +115,13 @@ static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask return -ENOSPC; /* Point device to the new vector */ - imsic_msi_update_msg(d, new_vec); + imsic_msi_update_msg(irq_get_irq_data(d->irq), new_vec); /* Update irq descriptors with the new vector */ - pd->chip_data = new_vec; + d->chip_data = new_vec; - /* Update effective affinity of parent irq data */ - irq_data_update_effective_affinity(pd, cpumask_of(new_vec->cpu)); + /* Update effective affinity */ + irq_data_update_effective_affinity(d, cpumask_of(new_vec->cpu)); /* Move state of the old vector to the new vector */ imsic_vector_move(old_vec, new_vec); @@ -135,6 +134,9 @@ static struct irq_chip imsic_irq_base_chip = { .name = "IMSIC", .irq_mask = imsic_irq_mask, .irq_unmask = imsic_irq_unmask, +#ifdef CONFIG_SMP + .irq_set_affinity = imsic_irq_set_affinity, +#endif .irq_retrigger = imsic_irq_retrigger, .irq_compose_msi_msg = imsic_irq_compose_msg, .flags = IRQCHIP_SKIP_SET_WAKE | @@ -245,7 +247,7 @@ static bool imsic_init_dev_msi_info(struct device *dev, if (WARN_ON_ONCE(domain != real_parent)) return false; #ifdef CONFIG_SMP - info->chip->irq_set_affinity = imsic_irq_set_affinity; + info->chip->irq_set_affinity = irq_chip_set_affinity_parent; #endif break; default: From patchwork Sun Feb 9 04:16:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13966630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9665C0219D for ; Sun, 9 Feb 2025 04:21:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=dDa5uVtGTmKoF+EGxYZ14lQBrXBy+Zgm46G016g9yok=; b=U8jRNTA/KNrb5/bpMfS47tYrXI gHC3DgHhK0VDv9ez3Ndw341DSS568+kK4GZxI6N72aM1YQG2ebZwE3s4obqh50oTS7eGMg/v+byE1 BaleVOyVtaXRiAeTEvnncaI/Z5mokxK89jp2yAw+Q0Uhsr0/jCv6M5di4LxhcF3VSAMyCtkYZYe7v QNyB6FqITFJowlx5X4ac31hQV9RHp5GlEjcaOJB8u6w8sykyXwePuqBFkNgLF/0mahq5pxhBLwZ3w ypvZYPddNpklrehDZNJ9vy0fuC61x+nOg2Euaq/RrdtThkUjugyqleUp723oTpESbLiqE1ZvQAW7q MJFqj7DQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tgyp2-0000000E3FN-0Rbr; Sun, 09 Feb 2025 04:21:32 +0000 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tgyl9-0000000E2K4-1R2P for linux-arm-kernel@lists.infradead.org; Sun, 09 Feb 2025 04:17:32 +0000 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-2f43d17b0e3so6221980a91.0 for ; Sat, 08 Feb 2025 20:17:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1739074651; x=1739679451; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dDa5uVtGTmKoF+EGxYZ14lQBrXBy+Zgm46G016g9yok=; b=OC6WOEOI6P393eaTXBXRGTPIDJ49XDZsrAlE43coLCU+uCTk7LhUpBGpoe1QJ653nO 0JdgH/z0q8Ei64fhhj4RnC257Q7j7SuTbAW+otzjnZOTI01nuShezbOqszx44YdMF2WD XyY8kjSBLj9e1O16fIFiJ2pVfxc5eUwyzvzgZBAtBlFCQq6Mbp3UCAn/giUKG4RnwbeF 778rChqeGXmtfTBmP5VS3f3kYDv+SruGjLlnRdSHcJdNRCQcEbOZ5fUcCLcjuPI9h3YK mCMMGD2l69UNoW6b2F9aIrWk6FGw6/EXTlYj9JEvI+4Cai4AzcymOOLx/3j3B3y/B0I8 gP0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739074651; x=1739679451; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dDa5uVtGTmKoF+EGxYZ14lQBrXBy+Zgm46G016g9yok=; b=v1UV7hHa1T/5hWWSl4KVU0hmAzn17AEn2c9zrV62LWXFP3AO90DXLE0WnwV+bunOck asAjiNBx8HUCnDR4j+v0/7JE2nwEs0RIUQTmCtvedMYy4C2uk4TUgyWEybmpWfH08zC+ 6ty3z3w4AghCNML2Haserr0BfnzlM/EmTz5kmxODrJXJw5jP++HC86SAZkWjDoJg4dD7 sFAKMHe6/i4fVpfJIJGKIcHKDBQ4NE7jxWDjv5KIQaf6NYW4G7GJzLaJtIB24DVsgCTR /OeJRg18oxd+5LGJhopw1oy/Irwd15XbZuo3H1Jy5BBuiLCkgmqCO6vrUmgqdlb4aGbK JCLg== X-Forwarded-Encrypted: i=1; AJvYcCWYHbwwsOf8n2BWI0izzqlUc4Va6yF8e9fgqNZq367q7EAxmiDYI9VybhVh287CpYpz2IZQDQogz0OCAqAdL5fR@lists.infradead.org X-Gm-Message-State: AOJu0Yz+EEVYyfTdagneOY7pACjvJKyAKa1WY/ISOysrUkF8Vc/RpYWP D+isA/e2qSAkiabYPtH4TovsMahetJ6Ci+MUd7L3OpbV+NkngeEmryoucTlJx9E= X-Gm-Gg: ASbGncvDLqslR8g4L42iMEp52lp2CeUwfNJW0tMb4QutSWogr7ZzK8/t3cz3m2GwhFj nzVQULBtNbUGOXq/7FyM4Vk3gksvUKpXtpKrh78gMFDmQDnniT7qz2y7Ua4KJ9a3mzQG1oBipxl CRnM7thdQErfSeQOCRJRGFx4VTwbBeiokuiubwFZB/21aYsyA9DONn4kegrIrqaKXzcpOpeDb5L NETf9oVGMKoQX7GlMuddRC4uVJBg1aEpBcMODB0bwTKeY9zSlMzH5hU3HolsicbkqZgaNEs9czS CQ3AZbnbkG+b/f3/OmThOkCyJUvDaU7q4goTu3E61uhLeOJjvv7YUus= X-Google-Smtp-Source: AGHT+IG1pX64iVcHBvRjhghD+pT2OaoFkAmw6b8bnet5SDDEvBV2yIiEcMLZqESX2yxzwT//jElybA== X-Received: by 2002:a05:6a00:cd1:b0:725:e444:2505 with SMTP id d2e1a72fcca58-7305d431970mr12792467b3a.4.1739074650717; Sat, 08 Feb 2025 20:17:30 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73073eba116sm1898410b3a.124.2025.02.08.20.17.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2025 20:17:30 -0800 (PST) From: Anup Patel To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: hpa@zytor.com, Marc Zyngier , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Palmer Dabbelt , Paul Walmsley , Atish Patra , Andrew Jones , Sunil V L , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel Subject: [PATCH v5 02/11] irqchip/irq-msi-lib: Optionally set default irq_eoi/irq_ack Date: Sun, 9 Feb 2025 09:46:46 +0530 Message-ID: <20250209041655.331470-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250209041655.331470-1-apatel@ventanamicro.com> References: <20250209041655.331470-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250208_201731_447644_5976CB60 X-CRM114-Status: GOOD ( 18.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thomas Gleixner Introduce chip_flags in struct msi_parent_ops. This allows msi_lib_init_dev_msi_info() set default irq_eoi/irq_ack callbacks only when the corresponding flags are set in the chip_flags. Signed-off-by: Thomas Gleixner Signed-off-by: Anup Patel --- drivers/irqchip/irq-gic-v2m.c | 1 + drivers/irqchip/irq-imx-mu-msi.c | 1 + drivers/irqchip/irq-msi-lib.c | 11 ++++++----- drivers/irqchip/irq-mvebu-gicp.c | 1 + drivers/irqchip/irq-mvebu-odmi.c | 1 + drivers/irqchip/irq-mvebu-sei.c | 1 + include/linux/msi.h | 11 +++++++++++ 7 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index be35c5349986..1e3476c335ca 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -255,6 +255,7 @@ static void __init gicv2m_teardown(void) static struct msi_parent_ops gicv2m_msi_parent_ops = { .supported_flags = GICV2M_MSI_FLAGS_SUPPORTED, .required_flags = GICV2M_MSI_FLAGS_REQUIRED, + .chip_flags = MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK, .bus_select_token = DOMAIN_BUS_NEXUS, .bus_select_mask = MATCH_PCI_MSI | MATCH_PLATFORM_MSI, .prefix = "GICv2m-", diff --git a/drivers/irqchip/irq-imx-mu-msi.c b/drivers/irqchip/irq-imx-mu-msi.c index 4342a21de1eb..69aacdfc8bef 100644 --- a/drivers/irqchip/irq-imx-mu-msi.c +++ b/drivers/irqchip/irq-imx-mu-msi.c @@ -214,6 +214,7 @@ static void imx_mu_msi_irq_handler(struct irq_desc *desc) static const struct msi_parent_ops imx_mu_msi_parent_ops = { .supported_flags = IMX_MU_MSI_FLAGS_SUPPORTED, .required_flags = IMX_MU_MSI_FLAGS_REQUIRED, + .chip_flags = MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK, .bus_select_token = DOMAIN_BUS_NEXUS, .bus_select_mask = MATCH_PLATFORM_MSI, .prefix = "MU-MSI-", diff --git a/drivers/irqchip/irq-msi-lib.c b/drivers/irqchip/irq-msi-lib.c index d8e29fc0d406..51464c6257f3 100644 --- a/drivers/irqchip/irq-msi-lib.c +++ b/drivers/irqchip/irq-msi-lib.c @@ -28,6 +28,7 @@ bool msi_lib_init_dev_msi_info(struct device *dev, struct irq_domain *domain, struct msi_domain_info *info) { const struct msi_parent_ops *pops = real_parent->msi_parent_ops; + struct irq_chip *chip = info->chip; u32 required_flags; /* Parent ops available? */ @@ -92,10 +93,10 @@ bool msi_lib_init_dev_msi_info(struct device *dev, struct irq_domain *domain, info->flags |= required_flags; /* Chip updates for all child bus types */ - if (!info->chip->irq_eoi) - info->chip->irq_eoi = irq_chip_eoi_parent; - if (!info->chip->irq_ack) - info->chip->irq_ack = irq_chip_ack_parent; + if (!chip->irq_eoi && (pops->chip_flags & MSI_CHIP_FLAG_SET_EOI)) + chip->irq_eoi = irq_chip_eoi_parent; + if (!chip->irq_ack && (pops->chip_flags & MSI_CHIP_FLAG_SET_ACK)) + chip->irq_ack = irq_chip_ack_parent; /* * The device MSI domain can never have a set affinity callback. It @@ -105,7 +106,7 @@ bool msi_lib_init_dev_msi_info(struct device *dev, struct irq_domain *domain, * device MSI domain aside of mask/unmask which is provided e.g. by * PCI/MSI device domains. */ - info->chip->irq_set_affinity = msi_domain_set_affinity; + chip->irq_set_affinity = msi_domain_set_affinity; return true; } EXPORT_SYMBOL_GPL(msi_lib_init_dev_msi_info); diff --git a/drivers/irqchip/irq-mvebu-gicp.c b/drivers/irqchip/irq-mvebu-gicp.c index 2b6183919ea4..d67f93f6d750 100644 --- a/drivers/irqchip/irq-mvebu-gicp.c +++ b/drivers/irqchip/irq-mvebu-gicp.c @@ -161,6 +161,7 @@ static const struct irq_domain_ops gicp_domain_ops = { static const struct msi_parent_ops gicp_msi_parent_ops = { .supported_flags = GICP_MSI_FLAGS_SUPPORTED, .required_flags = GICP_MSI_FLAGS_REQUIRED, + .chip_flags = MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK, .bus_select_token = DOMAIN_BUS_GENERIC_MSI, .bus_select_mask = MATCH_PLATFORM_MSI, .prefix = "GICP-", diff --git a/drivers/irqchip/irq-mvebu-odmi.c b/drivers/irqchip/irq-mvebu-odmi.c index ff19bfd258dc..28f7e81df94f 100644 --- a/drivers/irqchip/irq-mvebu-odmi.c +++ b/drivers/irqchip/irq-mvebu-odmi.c @@ -157,6 +157,7 @@ static const struct irq_domain_ops odmi_domain_ops = { static const struct msi_parent_ops odmi_msi_parent_ops = { .supported_flags = ODMI_MSI_FLAGS_SUPPORTED, .required_flags = ODMI_MSI_FLAGS_REQUIRED, + .chip_flags = MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK, .bus_select_token = DOMAIN_BUS_GENERIC_MSI, .bus_select_mask = MATCH_PLATFORM_MSI, .prefix = "ODMI-", diff --git a/drivers/irqchip/irq-mvebu-sei.c b/drivers/irqchip/irq-mvebu-sei.c index 065166ab5dbc..ebd4a9014e8d 100644 --- a/drivers/irqchip/irq-mvebu-sei.c +++ b/drivers/irqchip/irq-mvebu-sei.c @@ -356,6 +356,7 @@ static void mvebu_sei_reset(struct mvebu_sei *sei) static const struct msi_parent_ops sei_msi_parent_ops = { .supported_flags = SEI_MSI_FLAGS_SUPPORTED, .required_flags = SEI_MSI_FLAGS_REQUIRED, + .chip_flags = MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK, .bus_select_mask = MATCH_PLATFORM_MSI, .bus_select_token = DOMAIN_BUS_GENERIC_MSI, .prefix = "SEI-", diff --git a/include/linux/msi.h b/include/linux/msi.h index b10093c4d00e..9abef442c146 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -558,11 +558,21 @@ enum { MSI_FLAG_NO_AFFINITY = (1 << 21), }; +/* + * Flags for msi_parent_ops::chip_flags + */ +enum { + MSI_CHIP_FLAG_SET_EOI = (1 << 0), + MSI_CHIP_FLAG_SET_ACK = (1 << 1), +}; + /** * struct msi_parent_ops - MSI parent domain callbacks and configuration info * * @supported_flags: Required: The supported MSI flags of the parent domain * @required_flags: Optional: The required MSI flags of the parent MSI domain + * @chip_flags: Optional: Select MSI chip callbacks to update with defaults + * in msi_lib_init_dev_msi_info(). * @bus_select_token: Optional: The bus token of the real parent domain for * irq_domain::select() * @bus_select_mask: Optional: A mask of supported BUS_DOMAINs for @@ -575,6 +585,7 @@ enum { struct msi_parent_ops { u32 supported_flags; u32 required_flags; + u32 chip_flags; u32 bus_select_token; u32 bus_select_mask; const char *prefix; From patchwork Sun Feb 9 04:16:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13966631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 127F4C0219D for ; Sun, 9 Feb 2025 04:23:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=byPW6bNJR29pmHM6qNzPiiUHTFPpVNBWTNf2HlLXfG4=; b=sGw9uSum9rh6dfDnEwWGSnQyQG Cx0JmbZhUlmBqvghdXk0J8l3uacn1siGjgSOnTmxJ9dM9UFah59EpZhii2eEA4WUwyV5QtXtwbGBb Xl5hQ5irCwNUuc63cz9/qWJYhJpM8xNxn1Ei9S8LGj4vuCZ50bewSor2MWHdLU+izzXrCPxj+OOz2 hHVcDQnav8xgE1ZyoxTqfjO0vUmgTCddt3MGk2W9ZgFeiP+30a6TNOKIdJnTNfl63RT++1Lv10fIE Cgc9F9vwRjiGERgzvUnJ574D5CeU4JCD8qG+8XljbAKOnnHH3/G9l1efGqSTSsSJWJEu9c/IEmtRf KCq5pZkQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tgyqO-0000000E3Vo-3y0v; Sun, 09 Feb 2025 04:22:57 +0000 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tgylI-0000000E2Nf-1VzR for linux-arm-kernel@lists.infradead.org; Sun, 09 Feb 2025 04:17:41 +0000 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-21f7f03d7c0so7070455ad.3 for ; Sat, 08 Feb 2025 20:17:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1739074659; x=1739679459; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=byPW6bNJR29pmHM6qNzPiiUHTFPpVNBWTNf2HlLXfG4=; b=XB70fzpmLxHJQMIwdTzyY4ZxIlL84Ppk/QbOktOpmYC57Q9vEcbjdI30QCnsIoiyNU InevfyS60FdRDF5yBVfq5ndhaQZTVj2CBFprlpGzoNqnYfWt9mkwbnsrZvisB0UlE0kR rbUzQSZQNGFdO5MZFXEbgnvDSzPPbnECOqKfLVfqxfY2zZSQrGQrt+ihOlLzuio3+7W6 GKJuI/EnJcPwI1ad3jgk1BG1UWnFB0bZVvTeD3kB80MZiQgIY+B5tHc0AaHIBZpR7VA8 Huxp4y42yL4iHS0PH5NRLqDMlcgQY7f6moeb5So4LGkAHU8dRA/M+SpI9PPaZ1RghFCu t71Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739074659; x=1739679459; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=byPW6bNJR29pmHM6qNzPiiUHTFPpVNBWTNf2HlLXfG4=; b=KCKcjiKxJ0jCxz57cq326Y+oGYxqo/JiecmX4Fj1sfmIe/bweFiQbiVf07L9M+8pCN TPiqQ+iU8vf9kLNznWVkyHN/oi5XwQVbmxL23M+m0JMrmTcExMo2/67OWUf1LvqFONhy MQxUxLt7xN1gxnt8aN7kMdbUttaAvlAY1uGD0xeNU9dG2ZbcQjP23jv1T3BFBypbglT6 tbSC3sZvq2ObYqzsucm3vbfErJXNpUwRH3BujBIn9/N6Xl9Y8dFrgvU3Dh6KKFoHGU8r xjjc4dcdnsYUiEAPdRwJrQGQCrzPdoIUH6UGTWLmITAsDhQVZ5j38pRjXBXWVKkEhzWp O8Bg== X-Forwarded-Encrypted: i=1; AJvYcCX+Diu6y9F6ZItZbHv/989YygeCCFVJn2JPrlE9xeoBKNL26jfkVM/M9GFYFLHsI3yMxoTlAboStxFHcFkpuZyV@lists.infradead.org X-Gm-Message-State: AOJu0YxBVR5RYT53BlujqA9GidcUZaTeQD8IhJyqwqsiw+yGVvUsAIzo M4MRIi2hxoayjlGsDDxrM4++GKJ6TWoCI6xMwdBHyELCVN9cC202RwDuDIIAo0s= X-Gm-Gg: ASbGncvFdxO8PKBwCAddHxU/D8BuFTP7F97zhNdJ5rRJfymmbNbveR1wKw4Io3QKR9N eyK92/XeUTssbEqKrWwXyFx/TK5g+7NBbs7Y3dsEcbWc/0DjBiYxZzBGGGDbVanwNq/FQ/j0+Lw 7+U3YAsTszMZSyD9kk3g/DwFFGnqVsA6fzV/uw5ttE+Ydj/2YIn5SDrVtqtq08zulJzOQhXsjaZ RAQUY+BYT2oDwHySIc2GpF2PCGsIBng9NQGbeXpb9NlJvfk/yK0FYLTvair5njLv9BaMQVjSrwe +EEl62PVLmv255Sw7ZP57AWnEoUpHjX1h6Qdq8RmNSSNY4MENhuehJM= X-Google-Smtp-Source: AGHT+IH/ik3Ur8iKEEYDe9Hd4WVhXmYUsHE6OOkf8RhOk/pD00c5WvEJC3c0LK+040dao0sK2cXHKQ== X-Received: by 2002:a05:6a20:c6c6:b0:1db:dfc0:d342 with SMTP id adf61e73a8af0-1ee03a247admr16710991637.7.1739074659234; Sat, 08 Feb 2025 20:17:39 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73073eba116sm1898410b3a.124.2025.02.08.20.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2025 20:17:38 -0800 (PST) From: Anup Patel To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: hpa@zytor.com, Marc Zyngier , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Palmer Dabbelt , Paul Walmsley , Atish Patra , Andrew Jones , Sunil V L , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel Subject: [PATCH v5 03/11] irqchip/riscv-imsic: Move to common MSI lib Date: Sun, 9 Feb 2025 09:46:47 +0530 Message-ID: <20250209041655.331470-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250209041655.331470-1-apatel@ventanamicro.com> References: <20250209041655.331470-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250208_201740_515715_DEF1B04A X-CRM114-Status: GOOD ( 17.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thomas Gleixner Simplify the leaf MSI domain handling in the RISC-V IMSIC driver by using msi_lib_init_dev_msi_info() and msi_lib_irq_domain_select() provided by common MSI lib. Signed-off-by: Thomas Gleixner Signed-off-by: Andrew Jones Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 8 +- drivers/irqchip/irq-riscv-imsic-platform.c | 114 +-------------------- 2 files changed, 6 insertions(+), 116 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index be063bfb50c4..bc3f12af2dc7 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -589,13 +589,7 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_MATRIX_ALLOCATOR select GENERIC_MSI_IRQ - -config RISCV_IMSIC_PCI - bool - depends on RISCV_IMSIC - depends on PCI - depends on PCI_MSI - default RISCV_IMSIC + select IRQ_MSI_LIB config SIFIVE_PLIC bool diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index 5d7c30ad8855..9a5e7b4541f6 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -20,6 +20,7 @@ #include #include +#include "irq-msi-lib.h" #include "irq-riscv-imsic-state.h" static bool imsic_cpu_page_phys(unsigned int cpu, unsigned int guest_index, @@ -174,22 +175,6 @@ static void imsic_irq_domain_free(struct irq_domain *domain, unsigned int virq, irq_domain_free_irqs_parent(domain, virq, nr_irqs); } -static int imsic_irq_domain_select(struct irq_domain *domain, struct irq_fwspec *fwspec, - enum irq_domain_bus_token bus_token) -{ - const struct msi_parent_ops *ops = domain->msi_parent_ops; - u32 busmask = BIT(bus_token); - - if (fwspec->fwnode != domain->fwnode || fwspec->param_count != 0) - return 0; - - /* Handle pure domain searches */ - if (bus_token == ops->bus_select_token) - return 1; - - return !!(ops->bus_select_mask & busmask); -} - #ifdef CONFIG_GENERIC_IRQ_DEBUGFS static void imsic_irq_debug_show(struct seq_file *m, struct irq_domain *d, struct irq_data *irqd, int ind) @@ -206,110 +191,21 @@ static void imsic_irq_debug_show(struct seq_file *m, struct irq_domain *d, static const struct irq_domain_ops imsic_base_domain_ops = { .alloc = imsic_irq_domain_alloc, .free = imsic_irq_domain_free, - .select = imsic_irq_domain_select, + .select = msi_lib_irq_domain_select, #ifdef CONFIG_GENERIC_IRQ_DEBUGFS .debug_show = imsic_irq_debug_show, #endif }; -#ifdef CONFIG_RISCV_IMSIC_PCI - -static void imsic_pci_mask_irq(struct irq_data *d) -{ - pci_msi_mask_irq(d); - irq_chip_mask_parent(d); -} - -static void imsic_pci_unmask_irq(struct irq_data *d) -{ - irq_chip_unmask_parent(d); - pci_msi_unmask_irq(d); -} - -#define MATCH_PCI_MSI BIT(DOMAIN_BUS_PCI_MSI) - -#else - -#define MATCH_PCI_MSI 0 - -#endif - -static bool imsic_init_dev_msi_info(struct device *dev, - struct irq_domain *domain, - struct irq_domain *real_parent, - struct msi_domain_info *info) -{ - const struct msi_parent_ops *pops = real_parent->msi_parent_ops; - - /* MSI parent domain specific settings */ - switch (real_parent->bus_token) { - case DOMAIN_BUS_NEXUS: - if (WARN_ON_ONCE(domain != real_parent)) - return false; -#ifdef CONFIG_SMP - info->chip->irq_set_affinity = irq_chip_set_affinity_parent; -#endif - break; - default: - WARN_ON_ONCE(1); - return false; - } - - /* Is the target supported? */ - switch (info->bus_token) { -#ifdef CONFIG_RISCV_IMSIC_PCI - case DOMAIN_BUS_PCI_DEVICE_MSI: - case DOMAIN_BUS_PCI_DEVICE_MSIX: - info->chip->irq_mask = imsic_pci_mask_irq; - info->chip->irq_unmask = imsic_pci_unmask_irq; - break; -#endif - case DOMAIN_BUS_DEVICE_MSI: - /* - * Per-device MSI should never have any MSI feature bits - * set. It's sole purpose is to create a dumb interrupt - * chip which has a device specific irq_write_msi_msg() - * callback. - */ - if (WARN_ON_ONCE(info->flags)) - return false; - - /* Core managed MSI descriptors */ - info->flags |= MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS | - MSI_FLAG_FREE_MSI_DESCS; - break; - case DOMAIN_BUS_WIRED_TO_MSI: - break; - default: - WARN_ON_ONCE(1); - return false; - } - - /* Use hierarchial chip operations re-trigger */ - info->chip->irq_retrigger = irq_chip_retrigger_hierarchy; - - /* - * Mask out the domain specific MSI feature flags which are not - * supported by the real parent. - */ - info->flags &= pops->supported_flags; - - /* Enforce the required flags */ - info->flags |= pops->required_flags; - - return true; -} - -#define MATCH_PLATFORM_MSI BIT(DOMAIN_BUS_PLATFORM_MSI) - static const struct msi_parent_ops imsic_msi_parent_ops = { .supported_flags = MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX, .required_flags = MSI_FLAG_USE_DEF_DOM_OPS | - MSI_FLAG_USE_DEF_CHIP_OPS, + MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSI_MASK_PARENT, .bus_select_token = DOMAIN_BUS_NEXUS, .bus_select_mask = MATCH_PCI_MSI | MATCH_PLATFORM_MSI, - .init_dev_msi_info = imsic_init_dev_msi_info, + .init_dev_msi_info = msi_lib_init_dev_msi_info, }; int imsic_irqdomain_init(void) From patchwork Sun Feb 9 04:16:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13966636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BDAC2C02199 for ; Sun, 9 Feb 2025 04:24:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=muAXlG/uZk+Ut1w5NICM8ivKf832EJKGEf1Ht7zOCxs=; b=HQ5KwpYN6OQIMgyqEoK94LOL+v j3qAhGDu1UbaZH5/WCsIw/K663bVXINqtVC6mnEh1XYUTgz+I93PLazD855Tqcn6hXiaoK3W6CKoe j9OW1dGS3xNmPUqRh8xuAdntn9Ahns4YPlDRFBj01moRBz6HrWNDSfUomwh3HQEdiYGrDp+CiZYGW +ZxytJ9wwOJhO0z1+Few1Rx4DVs+Fc7utbM4P3MtTDRMFmFqGrJDxK5t6EHTDcIdSJXdg0fSUB3h4 8rEsBZkKi17rScYMARSBTLzAs9czshsdEtYswhCrCRdHd1LqxeLZwtpgs9xzlHpD2nukqbNyt9xhi ClpOW5QA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tgyrl-0000000E3lL-2P0y; Sun, 09 Feb 2025 04:24:21 +0000 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tgylQ-0000000E2Q4-2Ha0 for linux-arm-kernel@lists.infradead.org; Sun, 09 Feb 2025 04:17:50 +0000 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-2f9bac7699aso4843623a91.1 for ; Sat, 08 Feb 2025 20:17:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1739074668; x=1739679468; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=muAXlG/uZk+Ut1w5NICM8ivKf832EJKGEf1Ht7zOCxs=; b=PREU5bALDwFFP4FNFxSvx1z5LM3xcPGHfpX5tNUBQZZtT3ffytZSbkH9Hsu18AmQNt X5nlOj0U2XEyXZAwPsIjOGBp4ght/IXdp4cYYsM2rv6+BMRTSUS2SKUf7ZhgtTdoyPII vheefHGJPbuGICwkVR3wRIraHXOeuYD0FVD9jiQr2RdhtlWSUU0SPmRBYwN07Z//nMcr +BEP6MFG+qj6fJ4UPNpbJ9kBTrDi5/PdpYo9PpHZKdhk1wOHoEjVMSuyl4X3WcNrmBBw 1ipEr1ZXusodyQdhPU4CrgN2IaxEhgB0szm+ljDBIUWNZ+xlDKe5u7GDCdwTtLU314Nu cAKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739074668; x=1739679468; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=muAXlG/uZk+Ut1w5NICM8ivKf832EJKGEf1Ht7zOCxs=; b=KwSTc/tX45fUrmv+OyfaPrvMySzNA6DSCYlpBYzi+OqqlOV0Lr8qgn2EjwNmNLU1Yd Tk8ZW0F1kvFtfgCu/H15qT8xUs7kPObcHeEPNq8zZGahmmS3bq5WdkkoM3kzspFeS9hb PL5oUsvd9pl2CCPEcLdSXpr4kWuI7Yo7ZEBX0UiyWchk20RJQsl1PxRXNLlv9PMnAnjr 167l5DYZA0lUgBaWjGeqAqK2Gtb492gPuc2cjHtBXa/dYeApF8fEpnG3hv7W3Rj8qwDM R8Iq/Kn3L4XfXTTyVacN9nTeqnF+Cp6O/V6zrARa5WbjRVSH269YFGt72GlLK/YWbY12 kscQ== X-Forwarded-Encrypted: i=1; AJvYcCUsjt+E56t8kjgTVRcysytw8qtm+ktdIQgTbBMirBr0Oa0XfC0++EVQCO7nP7gLXjp2lx3WWcqRSVupLZA+2hO2@lists.infradead.org X-Gm-Message-State: AOJu0YzxN/SsM+DPn0ZTXNeCpxOiGGLJ5H5uuGdsiNq60D7lLV9lSXXJ UKUKNVYh/fQKVblx+WcnnqogL+Oaje5dc8xu3RXuACQu/sv/Bn4aQXXXp74YBsw= X-Gm-Gg: ASbGncsX3QXFD6MA5zvMuMoMhkJzDGXmiyhxhfYLXYum7x5G+/Ok1aWQYCxq5FJT4Hu I/4PYttgAbrGU7gANKkgtp7EVuZSr0LRjgtuq7aKlctjoNjEbu510EJUbaXB/0d1jBUykw0blgQ KOWuU0g5IK7IjLIxsTJQBALvJLwKScLTn7bHgzoj4NTFS8uLvjQqddUaHjqwlPqLPgyu1yT+c8L o0suzAufYe4jyPFZyKl3BHpA8ryCd19oN+clPc2KX3Jvk2gSdwjPq/ZSyYfkpNgOj5nml5XvVKN gjomM10xVKhEF8qDJGtU9YIyXDxjKNrC/mrN/gnZjQrwjA7z1Fg7pTM= X-Google-Smtp-Source: AGHT+IEZWcVRxpCJ2TdbHZSmXzLBoI3AvA6fXMBlEU2Ke4FpcCw0vGqhdEDkzoqwQdAILQxJgujX8g== X-Received: by 2002:a05:6a00:c86:b0:725:456e:76e with SMTP id d2e1a72fcca58-7305d44a459mr14381121b3a.6.1739074667815; Sat, 08 Feb 2025 20:17:47 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73073eba116sm1898410b3a.124.2025.02.08.20.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2025 20:17:47 -0800 (PST) From: Anup Patel To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: hpa@zytor.com, Marc Zyngier , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Palmer Dabbelt , Paul Walmsley , Atish Patra , Andrew Jones , Sunil V L , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel Subject: [PATCH v5 04/11] genirq: Introduce common irq_force_complete_move() implementation Date: Sun, 9 Feb 2025 09:46:48 +0530 Message-ID: <20250209041655.331470-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250209041655.331470-1-apatel@ventanamicro.com> References: <20250209041655.331470-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250208_201748_613400_529CBF29 X-CRM114-Status: GOOD ( 38.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thomas Gleixner The GENERIC_PENDING_IRQ requires an arch specific implementation of irq_force_complete_move(). At the moment, only x86 implements this but for RISC-V the irq_force_complete_move() is only needed when RISC-V IMSIC driver is in use and not needed otherwise. To address the above, introduce a common irq_force_complete_move() implementation in kernel irq migration which lets irqchip do the actual irq_force_complete_move() and also update x86 APIC to use this common implementation. Signed-off-by: Thomas Gleixner Signed-off-by: Anup Patel --- arch/x86/kernel/apic/vector.c | 231 ++++++++++++++++------------------ include/linux/irq.h | 5 +- kernel/irq/internals.h | 2 + kernel/irq/migration.c | 10 ++ 4 files changed, 123 insertions(+), 125 deletions(-) diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index 736f62812f5c..72fa4bb78f0a 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -888,8 +888,109 @@ static int apic_set_affinity(struct irq_data *irqd, return err ? err : IRQ_SET_MASK_OK; } +static void free_moved_vector(struct apic_chip_data *apicd) +{ + unsigned int vector = apicd->prev_vector; + unsigned int cpu = apicd->prev_cpu; + bool managed = apicd->is_managed; + + /* + * Managed interrupts are usually not migrated away + * from an online CPU, but CPU isolation 'managed_irq' + * can make that happen. + * 1) Activation does not take the isolation into account + * to keep the code simple + * 2) Migration away from an isolated CPU can happen when + * a non-isolated CPU which is in the calculated + * affinity mask comes online. + */ + trace_vector_free_moved(apicd->irq, cpu, vector, managed); + irq_matrix_free(vector_matrix, cpu, vector, managed); + per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; + hlist_del_init(&apicd->clist); + apicd->prev_vector = 0; + apicd->move_in_progress = 0; +} + +/* + * Called from fixup_irqs() with @desc->lock held and interrupts disabled. + */ +static void apic_force_complete_move(struct irq_data *irqd) +{ + unsigned int cpu = smp_processor_id(); + struct apic_chip_data *apicd; + unsigned int vector; + + guard(raw_spinlock)(&vector_lock); + apicd = apic_chip_data(irqd); + if (!apicd) + return; + + /* + * If prev_vector is empty or the descriptor is neither currently + * nor previously on the outgoing CPU no action required. + */ + vector = apicd->prev_vector; + if (!vector || (apicd->cpu != cpu && apicd->prev_cpu != cpu)) + return; + + /* + * This is tricky. If the cleanup of the old vector has not been + * done yet, then the following setaffinity call will fail with + * -EBUSY. This can leave the interrupt in a stale state. + * + * All CPUs are stuck in stop machine with interrupts disabled so + * calling __irq_complete_move() would be completely pointless. + * + * 1) The interrupt is in move_in_progress state. That means that we + * have not seen an interrupt since the io_apic was reprogrammed to + * the new vector. + * + * 2) The interrupt has fired on the new vector, but the cleanup IPIs + * have not been processed yet. + */ + if (apicd->move_in_progress) { + /* + * In theory there is a race: + * + * set_ioapic(new_vector) <-- Interrupt is raised before update + * is effective, i.e. it's raised on + * the old vector. + * + * So if the target cpu cannot handle that interrupt before + * the old vector is cleaned up, we get a spurious interrupt + * and in the worst case the ioapic irq line becomes stale. + * + * But in case of cpu hotplug this should be a non issue + * because if the affinity update happens right before all + * cpus rendezvous in stop machine, there is no way that the + * interrupt can be blocked on the target cpu because all cpus + * loops first with interrupts enabled in stop machine, so the + * old vector is not yet cleaned up when the interrupt fires. + * + * So the only way to run into this issue is if the delivery + * of the interrupt on the apic/system bus would be delayed + * beyond the point where the target cpu disables interrupts + * in stop machine. I doubt that it can happen, but at least + * there is a theoretical chance. Virtualization might be + * able to expose this, but AFAICT the IOAPIC emulation is not + * as stupid as the real hardware. + * + * Anyway, there is nothing we can do about that at this point + * w/o refactoring the whole fixup_irq() business completely. + * We print at least the irq number and the old vector number, + * so we have the necessary information when a problem in that + * area arises. + */ + pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", + irqd->irq, vector); + } + free_moved_vector(apicd); +} + #else -# define apic_set_affinity NULL +# define apic_set_affinity NULL +# define apic_force_complete_move NULL #endif static int apic_retrigger_irq(struct irq_data *irqd) @@ -923,39 +1024,16 @@ static void x86_vector_msi_compose_msg(struct irq_data *data, } static struct irq_chip lapic_controller = { - .name = "APIC", - .irq_ack = apic_ack_edge, - .irq_set_affinity = apic_set_affinity, - .irq_compose_msi_msg = x86_vector_msi_compose_msg, - .irq_retrigger = apic_retrigger_irq, + .name = "APIC", + .irq_ack = apic_ack_edge, + .irq_set_affinity = apic_set_affinity, + .irq_compose_msi_msg = x86_vector_msi_compose_msg, + .irq_force_complete_move = apic_force_complete_move, + .irq_retrigger = apic_retrigger_irq, }; #ifdef CONFIG_SMP -static void free_moved_vector(struct apic_chip_data *apicd) -{ - unsigned int vector = apicd->prev_vector; - unsigned int cpu = apicd->prev_cpu; - bool managed = apicd->is_managed; - - /* - * Managed interrupts are usually not migrated away - * from an online CPU, but CPU isolation 'managed_irq' - * can make that happen. - * 1) Activation does not take the isolation into account - * to keep the code simple - * 2) Migration away from an isolated CPU can happen when - * a non-isolated CPU which is in the calculated - * affinity mask comes online. - */ - trace_vector_free_moved(apicd->irq, cpu, vector, managed); - irq_matrix_free(vector_matrix, cpu, vector, managed); - per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; - hlist_del_init(&apicd->clist); - apicd->prev_vector = 0; - apicd->move_in_progress = 0; -} - static void __vector_cleanup(struct vector_cleanup *cl, bool check_irr) { struct apic_chip_data *apicd; @@ -1068,99 +1146,6 @@ void irq_complete_move(struct irq_cfg *cfg) __vector_schedule_cleanup(apicd); } -/* - * Called from fixup_irqs() with @desc->lock held and interrupts disabled. - */ -void irq_force_complete_move(struct irq_desc *desc) -{ - unsigned int cpu = smp_processor_id(); - struct apic_chip_data *apicd; - struct irq_data *irqd; - unsigned int vector; - - /* - * The function is called for all descriptors regardless of which - * irqdomain they belong to. For example if an IRQ is provided by - * an irq_chip as part of a GPIO driver, the chip data for that - * descriptor is specific to the irq_chip in question. - * - * Check first that the chip_data is what we expect - * (apic_chip_data) before touching it any further. - */ - irqd = irq_domain_get_irq_data(x86_vector_domain, - irq_desc_get_irq(desc)); - if (!irqd) - return; - - raw_spin_lock(&vector_lock); - apicd = apic_chip_data(irqd); - if (!apicd) - goto unlock; - - /* - * If prev_vector is empty or the descriptor is neither currently - * nor previously on the outgoing CPU no action required. - */ - vector = apicd->prev_vector; - if (!vector || (apicd->cpu != cpu && apicd->prev_cpu != cpu)) - goto unlock; - - /* - * This is tricky. If the cleanup of the old vector has not been - * done yet, then the following setaffinity call will fail with - * -EBUSY. This can leave the interrupt in a stale state. - * - * All CPUs are stuck in stop machine with interrupts disabled so - * calling __irq_complete_move() would be completely pointless. - * - * 1) The interrupt is in move_in_progress state. That means that we - * have not seen an interrupt since the io_apic was reprogrammed to - * the new vector. - * - * 2) The interrupt has fired on the new vector, but the cleanup IPIs - * have not been processed yet. - */ - if (apicd->move_in_progress) { - /* - * In theory there is a race: - * - * set_ioapic(new_vector) <-- Interrupt is raised before update - * is effective, i.e. it's raised on - * the old vector. - * - * So if the target cpu cannot handle that interrupt before - * the old vector is cleaned up, we get a spurious interrupt - * and in the worst case the ioapic irq line becomes stale. - * - * But in case of cpu hotplug this should be a non issue - * because if the affinity update happens right before all - * cpus rendezvous in stop machine, there is no way that the - * interrupt can be blocked on the target cpu because all cpus - * loops first with interrupts enabled in stop machine, so the - * old vector is not yet cleaned up when the interrupt fires. - * - * So the only way to run into this issue is if the delivery - * of the interrupt on the apic/system bus would be delayed - * beyond the point where the target cpu disables interrupts - * in stop machine. I doubt that it can happen, but at least - * there is a theoretical chance. Virtualization might be - * able to expose this, but AFAICT the IOAPIC emulation is not - * as stupid as the real hardware. - * - * Anyway, there is nothing we can do about that at this point - * w/o refactoring the whole fixup_irq() business completely. - * We print at least the irq number and the old vector number, - * so we have the necessary information when a problem in that - * area arises. - */ - pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", - irqd->irq, vector); - } - free_moved_vector(apicd); -unlock: - raw_spin_unlock(&vector_lock); -} - #ifdef CONFIG_HOTPLUG_CPU /* * Note, this is not accurate accounting, but at least good enough to diff --git a/include/linux/irq.h b/include/linux/irq.h index 8daa17f0107a..56f6583093d2 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -486,6 +486,7 @@ static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) * @ipi_send_mask: send an IPI to destination cpus in cpumask * @irq_nmi_setup: function called from core code before enabling an NMI * @irq_nmi_teardown: function called from core code after disabling an NMI + * @irq_force_complete_move: optional function to force complete pending irq move * @flags: chip specific flags */ struct irq_chip { @@ -537,6 +538,8 @@ struct irq_chip { int (*irq_nmi_setup)(struct irq_data *data); void (*irq_nmi_teardown)(struct irq_data *data); + void (*irq_force_complete_move)(struct irq_data *data); + unsigned long flags; }; @@ -619,11 +622,9 @@ static inline void irq_move_irq(struct irq_data *data) __irq_move_irq(data); } void irq_move_masked_irq(struct irq_data *data); -void irq_force_complete_move(struct irq_desc *desc); #else static inline void irq_move_irq(struct irq_data *data) { } static inline void irq_move_masked_irq(struct irq_data *data) { } -static inline void irq_force_complete_move(struct irq_desc *desc) { } #endif extern int no_irq_affinity; diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index a979523640d0..d4e190e690bd 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -442,6 +442,7 @@ static inline struct cpumask *irq_desc_get_pending_mask(struct irq_desc *desc) return desc->pending_mask; } bool irq_fixup_move_pending(struct irq_desc *desc, bool force_clear); +void irq_force_complete_move(struct irq_desc *desc); #else /* CONFIG_GENERIC_PENDING_IRQ */ static inline bool irq_can_move_pcntxt(struct irq_data *data) { @@ -467,6 +468,7 @@ static inline bool irq_fixup_move_pending(struct irq_desc *desc, bool fclear) { return false; } +static inline void irq_force_complete_move(struct irq_desc *desc) { } #endif /* !CONFIG_GENERIC_PENDING_IRQ */ #if !defined(CONFIG_IRQ_DOMAIN) || !defined(CONFIG_IRQ_DOMAIN_HIERARCHY) diff --git a/kernel/irq/migration.c b/kernel/irq/migration.c index eb150afd671f..e110300ad650 100644 --- a/kernel/irq/migration.c +++ b/kernel/irq/migration.c @@ -35,6 +35,16 @@ bool irq_fixup_move_pending(struct irq_desc *desc, bool force_clear) return true; } +void irq_force_complete_move(struct irq_desc *desc) +{ + for (struct irq_data *d = irq_desc_get_irq_data(desc); d; d = d->parent_data) { + if (d->chip && d->chip->irq_force_complete_move) { + d->chip->irq_force_complete_move(d); + return; + } + } +} + void irq_move_masked_irq(struct irq_data *idata) { struct irq_desc *desc = irq_data_to_desc(idata); From patchwork Sun Feb 9 04:16:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13966637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01A75C0219D for ; Sun, 9 Feb 2025 04:25:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3sE/PXdSSokJ0Zgm0Fk4Pk1jUj6qdWvd3FyfD/aEiAI=; b=YPOg40UqQRG/K9RwFJ8zFyUAlT yLsKlwifXNOwpKrRdj/gOXYxoKEQSym1WMgU+NU4hlrhUlhu46MnVXDl9diuZn+k0bPKb5kDWb2Tb mNZq2dkcvF4UM60i9oZEu27+hABfyBcf4KFyZFm4JbrZSwONHr/ElAdPIHENkGeLFK34/DeM8pvLq OfHdL4B/n9lx7IAWL2Yyqy6DItRJ98rcKmrWhwoYBXg3G1MpKmfXg/qr2Xv9xb2OusiIhuUKp4mh0 flVMeiCyj95RiNkFOzt06RkvZrso2wwx9BeEj9vCsyzXRqi/JHCJjYoY83wOr2KacTJ0Iicr/h0nV apxa+2Iw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tgyt8-0000000E3tH-0rat; Sun, 09 Feb 2025 04:25:46 +0000 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tgylY-0000000E2SB-3yEf for linux-arm-kernel@lists.infradead.org; Sun, 09 Feb 2025 04:17:58 +0000 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-2f9ba87f5d4so4708499a91.3 for ; Sat, 08 Feb 2025 20:17:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1739074676; x=1739679476; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3sE/PXdSSokJ0Zgm0Fk4Pk1jUj6qdWvd3FyfD/aEiAI=; b=S+IYvifu3RJKwJ64EqOFpzfssoHjWXjmzBUswhqINnDP6hPZDYORuUwMINRTayjECM 9ALJKzIBwXseW5eYWB0I7RbDEZh34iuq9B0j4jceX7CMNykSMElSkpO/pzzgqW2TZwiZ F32s0WvvOfJaiF2vE7R2jy2wuXfGOg0kw7cdTOjGu80uY0pgAR//6Pd4u1ijnCg/WPHS vtTs+DZPIOjD9Aa59uRfKuPmWSWwN6uwmOOPr1mJMGBU42QKBq933//Bp3yl7r2mQPd9 +NrRF1e9P6xka8PqyzIHRHGrBMtyIb6op2UVxzSOHNnZ8BOBdxDfj9RwFZnHLBprdeRH 7hmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739074676; x=1739679476; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3sE/PXdSSokJ0Zgm0Fk4Pk1jUj6qdWvd3FyfD/aEiAI=; b=Tg5yUD/mQNNKrVoU5Iy385hNFK+E2t3y0bUEooNAY6ThBTobcSTYyJzulkwWzZhKaW ICftummfW3TrBfhI+20irE0eZAS8Ky2vJD97YNRQrxmoFPWRuUxn23/zgaCDPZHipnnO NlYN5f107HX7n+sV7T21SvkCxIkn4+e8Yc3Ckzj8E0AqrI5/np6peU+qiBpKRK4dy4d9 LTUHuDe1axUAh9dj+1N3psgFXJ0aPOTAG+wf+All/lFtNAP7veVCIiElqgbXko9VzDBb 8aOeJQf0Q6pPiR/EXYUV9GQ5eTfa8PtHUAugcLba16qr9rOqGCwKnGVUj+hmc/DEDGQF msKA== X-Forwarded-Encrypted: i=1; AJvYcCUio9pVoUhShOyuajeTx78HDFJURjfKh5eVkw7Kh120X0NU1i/FzIQPDxe9tHzzsL6HMWUeoPdFMmCT58HD4D4P@lists.infradead.org X-Gm-Message-State: AOJu0YzsMU/6vjcPL6htcKFCKhzFiemLx+dNhYWq/8ymFFfPcR9F02bP gdaUcZW9RYozzBYlXiLfa9V1wX3tS3HB5Vqp7qA4VJ3yyDRUKNvjTMLl9wToSGk= X-Gm-Gg: ASbGncvfsJK5EmG5Qb6paiOKvZ7M2B67onbyqHRWJpxNAZqkZ/ZnKJvJgE9s+uHB5a6 bqBOoV+QMszmcVYuOBfC/83E8ZfljicsJP1M9v35unVzBd9w0F+wnOkc2yfJnTDeW2ZXskfa0JK 9JSwsMoMcMIM/C7TaaOcoDwzt5xNqo+J7tKknubdntJst8v5eHuzHncCdqvflmnDVJecfzFS9gU Whn/FTsY+KIhyW8TNqwtYwlt5Cs5U7X5ehYj1pGXAO5UaKdgdbzdgoUrikhI5SDDAZ5sXvDUFrL evMgQDZPbZrkg+uXOeYfGTq72ckccBFIFhfYmCyyLsKOYxQXAmgtM/I= X-Google-Smtp-Source: AGHT+IHDq8j70VgdWYD0/5rZSoa9FGuz2H9SOfW3ipfEG4foQkrNVKZyKea9+xF989Gz8oAitxsVGw== X-Received: by 2002:a05:6a00:a15:b0:727:d55e:4be3 with SMTP id d2e1a72fcca58-7305d463732mr13313591b3a.7.1739074676324; Sat, 08 Feb 2025 20:17:56 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73073eba116sm1898410b3a.124.2025.02.08.20.17.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2025 20:17:55 -0800 (PST) From: Anup Patel To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: hpa@zytor.com, Marc Zyngier , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Palmer Dabbelt , Paul Walmsley , Atish Patra , Andrew Jones , Sunil V L , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel Subject: [PATCH v5 05/11] genirq: Introduce irq_can_move_in_process_context() Date: Sun, 9 Feb 2025 09:46:49 +0530 Message-ID: <20250209041655.331470-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250209041655.331470-1-apatel@ventanamicro.com> References: <20250209041655.331470-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250208_201757_039446_3F70E7F5 X-CRM114-Status: GOOD ( 11.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The interrupt controller drivers which use GENERIC_PENDING_IRQ can move interrupts in process context for downstrean devices which support atomic MSI configuration. Introduce irq_can_move_in_process_context() which allows interrupt controller drivers to test whether a particular interrupt can be moved process context. Signed-off-by: Anup Patel --- include/linux/irq.h | 2 ++ kernel/irq/migration.c | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/include/linux/irq.h b/include/linux/irq.h index 56f6583093d2..dd5df1e2d032 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -615,6 +615,7 @@ extern int irq_affinity_online_cpu(unsigned int cpu); #endif #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) +bool irq_can_move_in_process_context(struct irq_data *data); void __irq_move_irq(struct irq_data *data); static inline void irq_move_irq(struct irq_data *data) { @@ -623,6 +624,7 @@ static inline void irq_move_irq(struct irq_data *data) } void irq_move_masked_irq(struct irq_data *data); #else +static inline bool irq_can_move_in_process_context(struct irq_data *data) { return true; } static inline void irq_move_irq(struct irq_data *data) { } static inline void irq_move_masked_irq(struct irq_data *data) { } #endif diff --git a/kernel/irq/migration.c b/kernel/irq/migration.c index e110300ad650..5acea2ac57be 100644 --- a/kernel/irq/migration.c +++ b/kernel/irq/migration.c @@ -127,3 +127,14 @@ void __irq_move_irq(struct irq_data *idata) if (!masked) idata->chip->irq_unmask(idata); } + +bool irq_can_move_in_process_context(struct irq_data *data) +{ + /* + * Get top level irq_data when CONFIG_IRQ_DOMAIN_HIERARCHY is enabled, + * and it should be optimized away when CONFIG_IRQ_DOMAIN_HIERARCHY is + * disabled. So we avoid an "#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY" here. + */ + data = irq_desc_get_irq_data(irq_data_to_desc(data)); + return irq_can_move_pcntxt(data); +} From patchwork Sun Feb 9 04:16:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13966638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B032C02199 for ; Sun, 9 Feb 2025 04:27:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+su7Pdf8Wu86Zcml4faTN2UwZ+oipeVYumq+PsYwErw=; b=KxJdNJdHWaH1Fxq1H5TDbcPnx3 bML0BxWDQuw752ingPzYoMdjDy98HoDVV0VEGPk/FLz+QvERbOwaaIzmDqkgRxC4U2ai0N3si8X5O kJmCEn9RKxwPkwBCWptK3J/STUda08yARvpmTU4fCJgeLCAw9Di/9yZGhAg6/HZQZck54kpSdlst4 6jFLL1/N9GwqVuyD1uMBg5j+6RJnzYFms29b6qoAZ3sb+uuQLt9VYwTgy6hBxPCx7Ws3DbUtpZk6H 7cTFEK/yir2y+EKVKuYVKc0+aHoqT3JuIVQju02KlwUE9txSVIH1DZVB7IF3fosRDqnRR0/3Tq12J I0m09GKA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tgyuV-0000000E4A9-1Y5Q; Sun, 09 Feb 2025 04:27:11 +0000 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tgylh-0000000E2Uq-1zW3 for linux-arm-kernel@lists.infradead.org; Sun, 09 Feb 2025 04:18:07 +0000 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2fa1d9fb990so4654471a91.2 for ; Sat, 08 Feb 2025 20:18:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1739074685; x=1739679485; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+su7Pdf8Wu86Zcml4faTN2UwZ+oipeVYumq+PsYwErw=; b=RyVhxtOk9yFTVa5fhH9FEoDTMNvWQ9pmZ45w9pGR8Pfa93CErKyNVQLdBwA2445bj7 yAQ2kpr1hkVcMVRkHsn6+cGHFNX9ShC0KaxSH8U/tGv2HqZdtfIZwEaNB8zYXHaH3Gm2 4hrhu5fIJN4/9aMLvCImleMkqs0bxjC5lPBucJjkdXki8lvw7kUKbpMsnFxDQauGVGDk EDGNhdqQWUSxqrXcvJdV7rC8Uum5aLEXP3QO/OT8hrsGoTFc9mHbvQ0BxIno5OqbnsqJ ryrKnjtoM47kQOjoX09qvXVTTOJJ11ONOovpC+x8PnPhx9/3wZt+2g6LI/7jwStLB9tF 8Fug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739074685; x=1739679485; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+su7Pdf8Wu86Zcml4faTN2UwZ+oipeVYumq+PsYwErw=; b=J9guRItTR2V8kqwytnsqRVQtiU3OrT//GkiZevZQmMwjSHqEqybVcR8DYXo2oBMR6M a89jwK+HpO/+J+vKRkyVgRESlcYyQxUI6baa5tZL3xC//+3YZT4PTKXIzbWnREiNTzBr 8JcU/br219AHr4Ed4LOksZxhfwtCGckweWcehEgR+0NbFNNpMDoJQ5hgZG/36LmG5SDy z1e/OG2MLP36KST5WmqQAK35TO+EV2H67I47Xwa41PCSjj0i5xydYTA+n1cR46eEdNzv uoUCV4i694XCR/VoWchqYl8M/j/WB2AVAGcCMvcIr30F7/goB7xn/F03mvwPaFhUTuXX /CIw== X-Forwarded-Encrypted: i=1; AJvYcCUH50lyQ3E2LnTxDMHeUsDyqMYKnsrvjjX8DMgmnuZDml5jfBi0L56ZNlNujmkCVwWFJnJ6GiSJXS06ZczTnXCo@lists.infradead.org X-Gm-Message-State: AOJu0YwdFat4uUXV81YV5N2EX5/KpJvGq76YBDZf2dJQB6ll2MaxIH/s MYyrJ95Y8MxRrn952t7GtXXWHGzWe6OKiUqtyVLKk/E0f4vX/lYFStP3QzT0kVs= X-Gm-Gg: ASbGnctXdQvSZumtKgKe7VsZmDgsoc6ckt6ZW0rH9YpVKSWxKLAp+947+3YYAxKpjxQ XgxASW0Ep7sA8eDqTH9EZE+Gc9psJWjMtztqXWYNbmkddZcsHnCcd/GDMO12zZOdUyGhrfMyjYX T+KwwzlE/9zed/o3uLjqgVfoaDNKJvJpfbdiRTgiSjFFNOH9jePcnQbTmI+a642WJSgGMPo+BdG nGYfOuaZjA8UxdgYbt9bCqiT40loIVNmwEMiYaBMP0hlOcxNwUGtQ/r3g+dI4Y3w8L91x91OGny 4RtegDWeHdsMpOqTz1rRzbJ0qptdGO0ZxV8FkGoDVyOxmtwJ/lT9gAU= X-Google-Smtp-Source: AGHT+IHplK1Odn1krUBJui9aJ3bXui5w4fG7ychKlkG3JoJ8qZ1jCX3WfSDt+grELpA1vaZRwG2+1g== X-Received: by 2002:a05:6a00:178c:b0:730:8a5b:6e61 with SMTP id d2e1a72fcca58-7308a5b7c17mr217952b3a.2.1739074684846; Sat, 08 Feb 2025 20:18:04 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73073eba116sm1898410b3a.124.2025.02.08.20.17.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2025 20:18:04 -0800 (PST) From: Anup Patel To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: hpa@zytor.com, Marc Zyngier , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Palmer Dabbelt , Paul Walmsley , Atish Patra , Andrew Jones , Sunil V L , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel Subject: [PATCH v5 06/11] genirq: Remove unused GENERIC_PENDING_IRQ_CHIPFLAGS kconfig option Date: Sun, 9 Feb 2025 09:46:50 +0530 Message-ID: <20250209041655.331470-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250209041655.331470-1-apatel@ventanamicro.com> References: <20250209041655.331470-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250208_201805_685007_C2329833 X-CRM114-Status: UNSURE ( 9.99 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The GENERIC_PENDING_IRQ_CHIPFLAGS kconfig option is no used anywhere hence remove it. Fixes: f94a18249b7f ("genirq: Remove IRQ_MOVE_PCNTXT and related code") Signed-off-by: Anup Patel --- kernel/irq/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/kernel/irq/Kconfig b/kernel/irq/Kconfig index 5432418c0fea..875f25ed6f71 100644 --- a/kernel/irq/Kconfig +++ b/kernel/irq/Kconfig @@ -31,10 +31,6 @@ config GENERIC_IRQ_EFFECTIVE_AFF_MASK config GENERIC_PENDING_IRQ bool -# Deduce delayed migration from top-level interrupt chip flags -config GENERIC_PENDING_IRQ_CHIPFLAGS - bool - # Support for generic irq migrating off cpu before the cpu is offline. config GENERIC_IRQ_MIGRATION bool From patchwork Sun Feb 9 04:16:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13966639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2F8EC02199 for ; Sun, 9 Feb 2025 04:28:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=JBZXTbuS/jzxIISJXLRWUHAJ1oANsva3E4CzlwWomJY=; b=YxjqoJYhZvbEBpm5Hrdyb8obZj XLqVgmRgh9na3gHtkAP//5veuXd3lI6rYJycmBRV/qUBkNc8tDx+l3HM3jaTKRfTIT8mFY1U5+LhU ytMhLJaRZZobSjzhmd3zpak9wHRBmacJSnpASwEtZDEMbP0Wtd8a8gutslBY9TQp3tPmdDevNsi59 LmMqkVbwg6NF7pX7K4EtiHZGzrMjH1ZesMn0PhrLivQ5K+xFj88Mm962eiwEPUXfoUNNKOYhrTyQo 9ecD+jLHeDJxcpRNfRgiZ0ptj3Jxy3hEqe7lByXOOvPgwMBqGoxvgxV1Pb0BXYmEHHbWSmqZKduSX 2Ji0toQw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tgyvr-0000000E4P1-3Oh1; Sun, 09 Feb 2025 04:28:35 +0000 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tgylr-0000000E2Xt-2eRw for linux-arm-kernel@lists.infradead.org; Sun, 09 Feb 2025 04:18:17 +0000 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-2fa286ea7e8so2780577a91.2 for ; Sat, 08 Feb 2025 20:18:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1739074695; x=1739679495; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JBZXTbuS/jzxIISJXLRWUHAJ1oANsva3E4CzlwWomJY=; b=H27wk9QWPks3qOJRzw9zAVDZV0byI+ZYSlJ9j9W1L9N7hblqCI3x/J80PFe6D1lKnb L3ezHGeugew3uGKjs95OmkFOA5iZFPj2TwhgxFGooitN6vB/cqWpjBHuigtzD+nGfOqa wLJAyDpXKdEBhUYqNOadgPNPsPhhjtgSos1BfIoBD+M+70jz/4+4Qds0fDHYktsIO6ze H4KOZZDxECif6FPSvOMWsMTNFCDrw8pgV19xWyRZmZWxYuJHd+wqq8QLhoe/x7sea1zK Kn9z4XCFG5YanELyGy+D/dN/vSlXTJCT/ni9U0aGk+/B/A3G6ex9Dz81mFhFJpNpuRnG iX7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739074695; x=1739679495; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JBZXTbuS/jzxIISJXLRWUHAJ1oANsva3E4CzlwWomJY=; b=Bx8jww1ZFAzpaIR0c2++NZSdKVaH/k0U2e96eYHI5njRIXeh4TxFg8quduVhD3Hy7m 8N0RAd1Hmj0/Jl5pJ3fBdYVzoqTzH+n7aYvKsfRCIi3yUHLAEX8QLHcqxx6XUISx8h1e yzqhcBy0igACRICeF4qccFsbjYrXUYea+ZKTP3R9hAc/fb+crEazQH1sRseSt9MY7rk9 7U2LLZqgEzk9vfj5ZA3xvQ0KlHIeB3Mww/IbiWbZMEX+DeM533c7vcLse9pLOdyDl2UB dk9GnagfzMQJZBlLyno7ixixQu4BCXzP86tihXyd7OIv0vhtHLt1KEUtQGOChW+QjmYE V96Q== X-Forwarded-Encrypted: i=1; AJvYcCVkL901QXXSgP/ymv+croA4gc0mFaDFnfINQM35fIw1JZzRTEgmXf4lswhXcs5McXQ0wo0Dv68YI1OAhHz+Da7D@lists.infradead.org X-Gm-Message-State: AOJu0Yx6CxtQxgxteUsfsYhZvwmoMEAQ6QYF6V5QXvmkWDrMxcJRFv7b kaWZSWv3wMDjOc8InH+0+FanEsY9lHp7NQ7ENMIv5NFLkIPQ7W0TLzu23C4rjGk= X-Gm-Gg: ASbGncvY7cCKEPAqu90K1KjZqTZFtPW9Rskzfu2D6kFDq10VFTJx/ZLM/qaIO1RUgfq pQY5il4NjmrZD132muh8hNQtt3AdZhC/7zu0zXVLTxC+t51MhIOIX1Z5Zq4GgQJd64dJ7X4jalm NgtRfnsllu6P10fK49MVFJlG5tKoksoC9tMaZjKHwtuvW7Z0HjvwF3bSWJNds9H1k+nhwS170yJ ZamHgMwbM5LluuM9fUq4VyH+KO/iIzNKUQS/sutYqVyGbh2xznoZQpw+AAX+IJcBPxQiLELk2wy segsmREw3wSsNsp60r84wl0C6YH93mAz4eTCyUaApWVFZ08oBq6qWAo= X-Google-Smtp-Source: AGHT+IHL0ZAy+b2/HWpMWPKyLFtjwNwqGOrHhxJ1k6glfU7lfaN1/yKHZr4v/qmnwtb+wj+/nQhb2w== X-Received: by 2002:a05:6a00:2289:b0:725:460e:6bc0 with SMTP id d2e1a72fcca58-7305d2ac0admr15896176b3a.0.1739074694598; Sat, 08 Feb 2025 20:18:14 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73073eba116sm1898410b3a.124.2025.02.08.20.18.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2025 20:18:14 -0800 (PST) From: Anup Patel To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: hpa@zytor.com, Marc Zyngier , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Palmer Dabbelt , Paul Walmsley , Atish Patra , Andrew Jones , Sunil V L , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel Subject: [PATCH v5 07/11] RISC-V: Select GENERIC_PENDING_IRQ Date: Sun, 9 Feb 2025 09:46:51 +0530 Message-ID: <20250209041655.331470-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250209041655.331470-1-apatel@ventanamicro.com> References: <20250209041655.331470-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250208_201815_665533_3CA5710B X-CRM114-Status: UNSURE ( 9.14 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable GENERIC_PENDING_IRQ for RISC-V so that RISC-V irqchips can support delayed irq mirgration in the interrupt context. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7612c52e9b1e..a32f39748775 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -111,6 +111,7 @@ config RISCV select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW_LEVEL select GENERIC_LIB_DEVMEM_IS_ALLOWED + select GENERIC_PENDING_IRQ if SMP select GENERIC_PCI_IOMAP select GENERIC_PTDUMP if MMU select GENERIC_SCHED_CLOCK From patchwork Sun Feb 9 04:16:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13966643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6CDF2C02199 for ; Sun, 9 Feb 2025 04:30:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=li309BKFytEFNs0s+UiLLaDTQ3aEtuOmqKESJ/Lkwhg=; b=QW9/ca6miEpjSL2T3mTIQF7i8/ pE/hoz+1rI0fiyEQBsvUGymslBeQdS6wW5otaw3VpU0ilJeIFwp/Hbc0MbLsGDcszoVlhQ2OH9trt X4CEE3TEB7ViIDPDLnPENdX8ZJzcrUGrR764298AattoABCMptksesUR+9lUBlWnMv5DIE8WV11te wbngx+G3dMQZ95uwvkl8jQZZTF3fhjUe7bmP+oBJ2dheULa9JxHqhi/UJYOCBUPnx6n9PkAzAkE4M wA+tav54kjZjeY74xQEIfHM/l2GH3ZBdxrr0Lovpp9i/hyB/DPhJHS1BdEDlItzUtFOrKLv7p9/iT 75IQgQiA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tgyxE-0000000E4ae-2RhA; Sun, 09 Feb 2025 04:30:00 +0000 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tgym0-0000000E2bZ-0KpT for linux-arm-kernel@lists.infradead.org; Sun, 09 Feb 2025 04:18:25 +0000 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2fa40c0bab2so2049494a91.0 for ; Sat, 08 Feb 2025 20:18:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1739074703; x=1739679503; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=li309BKFytEFNs0s+UiLLaDTQ3aEtuOmqKESJ/Lkwhg=; b=dvtA7pYzZ+WkmQ3YX09lX6k5O7kAW2WP7M9U84KMyCOpWMN8RLClFpc3Oq2VUyfXKt vw3K3RZEvIocEa4xaSKebMKIUIHJVVzEWbMhqgLL3P2lVcLYwqYVfZPCwmKnQ3hyjrOt SAIprxdyE23sZtJMx98aZOb8yTpAN61vgrLur+zZWdNMzdl9Is0xIXG4cLNhVNhexNjV ygW+IspCo2k6hlsC+19BOAnBrjiImKRggNe5pCh+PzasoygbA5bH3UcgLy+GF8gDJpl0 MvYVnNuQRUQJf0P4DB8Uj6lFFfTk69R1spMKOndqVsW9PVmERE4rpy/2RpBoSUeP0x3i AhFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739074703; x=1739679503; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=li309BKFytEFNs0s+UiLLaDTQ3aEtuOmqKESJ/Lkwhg=; b=E3/GODgjjy/tblggCnzOzT+O3vTNoux7yy7Ep5y8f/5XNc7QDFDcDmSWcaSFC5KF80 d3HG8mMmXARPYJUt2jtgEPcgj0HQvaC8Lu29rWQvutAFGltA/xC3Pxdd5i6UKw1ZSvoZ y23HC2zlNxDryhbr4k/U0XY2b/FaO5OVFIwBO5GrIW4rm0hRa5GKq2bp9laHIsb0Tdc1 BH2zFqRttjZAAN+qYHo3XlgITLS61NkzeuCWLLloJciezzYIsgYziNsPsyF+NGt8HBsq 3VOdK2hfi7XBLGBley9Pu8D83NKIomcB+spimhIGB8sjuUSlVlLyGtbZ5PxUTJCxEE/L FaTg== X-Forwarded-Encrypted: i=1; AJvYcCXnw6FUYfpTUlg7kvR2QirERHvgGsjkcVKJ4UuKU/B2aQsHnkq3AnRxBmz1Cut+OjUac4tV6IID1ynUrcWhGGm1@lists.infradead.org X-Gm-Message-State: AOJu0Yy30FDqK2oWBW9HLbxBp1dzeOF2WtxBlKoCdsirdTam/WenotgL JEYfDJWPQNrqpuRN6L8E1ePdWLgLpf/LTMyPltcVKFVOK0L1+JHmRXl4s0Y/wk4= X-Gm-Gg: ASbGnctV4ikwvYpXchpWyorT/TQ04X4N/qSMLTO9nLSw1Otdy0lw8RDEa8gYuZ1/pG3 euEADcImmvCFjrMGYbPpXdr8Ns9qMzmcvfmg/H6JNZOWAmR/OMPBC4a/wZuZYapo7trN/VhP7P0 DwmoXzpH8QXQQZVdNtoXz37cLaSJobPh1dIpuKWYYaPkmc580n6pc+837cbK08RSONjCLSinqiM qb8JG5y4F617Mqbur/t634M6nU5pou6CExnzPwwjEyUn6QlBoD7Pa4MteXaIfnKEgCy/z0O5YAU 8DZPAChrJmAnbsK50KjC/lUxxMIuwVywDjVf5Zfgk9p29qjj9sKulwc= X-Google-Smtp-Source: AGHT+IGr8DIP/za6PXLubagaC8HrCh4Chcf3SqtLF6bJLforSFiwf8+xl00IhhTWFSgMBoJHAPJZQw== X-Received: by 2002:a05:6a20:6f91:b0:1dc:2365:4d7d with SMTP id adf61e73a8af0-1ee03a4744fmr14841962637.16.1739074703102; Sat, 08 Feb 2025 20:18:23 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73073eba116sm1898410b3a.124.2025.02.08.20.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2025 20:18:22 -0800 (PST) From: Anup Patel To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: hpa@zytor.com, Marc Zyngier , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Palmer Dabbelt , Paul Walmsley , Atish Patra , Andrew Jones , Sunil V L , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel Subject: [PATCH v5 08/11] irqchip/riscv-imsic: Separate next and previous pointers in IMSIC vector Date: Sun, 9 Feb 2025 09:46:52 +0530 Message-ID: <20250209041655.331470-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250209041655.331470-1-apatel@ventanamicro.com> References: <20250209041655.331470-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250208_201824_128138_DA300FE8 X-CRM114-Status: GOOD ( 25.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently, there is only one "move" pointer in the struct imsic_vector so during vector movement the old vector points to the new vector and new vector points to itself. To support force cleanup of old vector, add separate "move_next" and "move_prev" pointers in the struct imsic_vector where during vector movement the "move_next" pointer of the old vector points to the new vector and the "move_prev" pointer of the new vector points to the old vector. Both "move_next" and "move_prev" pointers are cleared separately by __imsic_local_sync() with a restriction that "move_prev" on the new CPU is cleared only after old CPU has cleared "move_next". Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-imsic-early.c | 8 ++- drivers/irqchip/irq-riscv-imsic-state.c | 96 +++++++++++++++++-------- drivers/irqchip/irq-riscv-imsic-state.h | 7 +- 3 files changed, 78 insertions(+), 33 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c index c5c2e6929a2f..b5def6268936 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -77,6 +77,12 @@ static void imsic_handle_irq(struct irq_desc *desc) struct imsic_vector *vec; unsigned long local_id; + /* + * Process pending local synchronization instead of waiting + * for per-CPU local timer to expire. + */ + imsic_local_sync_all(false); + chained_irq_enter(chip, desc); while ((local_id = csr_swap(CSR_TOPEI, 0))) { @@ -120,7 +126,7 @@ static int imsic_starting_cpu(unsigned int cpu) * Interrupts identities might have been enabled/disabled while * this CPU was not running so sync-up local enable/disable state. */ - imsic_local_sync_all(); + imsic_local_sync_all(true); /* Enable local interrupt delivery */ imsic_local_delivery(true); diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c index b97e6cd89ed7..96e994443fc7 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -124,10 +124,11 @@ void __imsic_eix_update(unsigned long base_id, unsigned long num_id, bool pend, } } -static void __imsic_local_sync(struct imsic_local_priv *lpriv) +static bool __imsic_local_sync(struct imsic_local_priv *lpriv) { struct imsic_local_config *mlocal; struct imsic_vector *vec, *mvec; + bool ret = true; int i; lockdep_assert_held(&lpriv->lock); @@ -143,35 +144,75 @@ static void __imsic_local_sync(struct imsic_local_priv *lpriv) __imsic_id_clear_enable(i); /* - * If the ID was being moved to a new ID on some other CPU - * then we can get a MSI during the movement so check the - * ID pending bit and re-trigger the new ID on other CPU - * using MMIO write. + * Clear the pervious vector pointer of the new vector only + * after the movement is complete on the old CPU. */ - mvec = READ_ONCE(vec->move); - WRITE_ONCE(vec->move, NULL); - if (mvec && mvec != vec) { + mvec = READ_ONCE(vec->move_prev); + if (mvec) { + /* + * If the old vector has not been updated then + * try again in the next sync-up call. + */ + if (READ_ONCE(mvec->move_next)) { + ret = false; + continue; + } + + WRITE_ONCE(vec->move_prev, NULL); + } + + /* + * If a vector was being moved to a new vector on some other + * CPU then we can get a MSI during the movement so check the + * ID pending bit and re-trigger the new ID on other CPU using + * MMIO write. + */ + mvec = READ_ONCE(vec->move_next); + if (mvec) { if (__imsic_id_read_clear_pending(i)) { mlocal = per_cpu_ptr(imsic->global.local, mvec->cpu); writel_relaxed(mvec->local_id, mlocal->msi_va); } + WRITE_ONCE(vec->move_next, NULL); imsic_vector_free(&lpriv->vectors[i]); } skip: bitmap_clear(lpriv->dirty_bitmap, i, 1); } + + return ret; } -void imsic_local_sync_all(void) +#ifdef CONFIG_SMP +static void __imsic_local_timer_start(struct imsic_local_priv *lpriv) +{ + lockdep_assert_held(&lpriv->lock); + + if (!timer_pending(&lpriv->timer)) { + lpriv->timer.expires = jiffies + 1; + add_timer_on(&lpriv->timer, smp_processor_id()); + } +} +#else +static inline void __imsic_local_timer_start(struct imsic_local_priv *lpriv) +{ +} +#endif + +void imsic_local_sync_all(bool force_all) { struct imsic_local_priv *lpriv = this_cpu_ptr(imsic->lpriv); unsigned long flags; raw_spin_lock_irqsave(&lpriv->lock, flags); - bitmap_fill(lpriv->dirty_bitmap, imsic->global.nr_ids + 1); - __imsic_local_sync(lpriv); + + if (force_all) + bitmap_fill(lpriv->dirty_bitmap, imsic->global.nr_ids + 1); + if (!__imsic_local_sync(lpriv)) + __imsic_local_timer_start(lpriv); + raw_spin_unlock_irqrestore(&lpriv->lock, flags); } @@ -190,12 +231,7 @@ void imsic_local_delivery(bool enable) #ifdef CONFIG_SMP static void imsic_local_timer_callback(struct timer_list *timer) { - struct imsic_local_priv *lpriv = this_cpu_ptr(imsic->lpriv); - unsigned long flags; - - raw_spin_lock_irqsave(&lpriv->lock, flags); - __imsic_local_sync(lpriv); - raw_spin_unlock_irqrestore(&lpriv->lock, flags); + imsic_local_sync_all(false); } static void __imsic_remote_sync(struct imsic_local_priv *lpriv, unsigned int cpu) @@ -216,14 +252,11 @@ static void __imsic_remote_sync(struct imsic_local_priv *lpriv, unsigned int cpu */ if (cpu_online(cpu)) { if (cpu == smp_processor_id()) { - __imsic_local_sync(lpriv); - return; + if (__imsic_local_sync(lpriv)) + return; } - if (!timer_pending(&lpriv->timer)) { - lpriv->timer.expires = jiffies + 1; - add_timer_on(&lpriv->timer, cpu); - } + __imsic_local_timer_start(lpriv); } } #else @@ -278,8 +311,9 @@ void imsic_vector_unmask(struct imsic_vector *vec) raw_spin_unlock(&lpriv->lock); } -static bool imsic_vector_move_update(struct imsic_local_priv *lpriv, struct imsic_vector *vec, - bool new_enable, struct imsic_vector *new_move) +static bool imsic_vector_move_update(struct imsic_local_priv *lpriv, + struct imsic_vector *vec, bool is_old_vec, + bool new_enable, struct imsic_vector *move_vec) { unsigned long flags; bool enabled; @@ -289,7 +323,10 @@ static bool imsic_vector_move_update(struct imsic_local_priv *lpriv, struct imsi /* Update enable and move details */ enabled = READ_ONCE(vec->enable); WRITE_ONCE(vec->enable, new_enable); - WRITE_ONCE(vec->move, new_move); + if (is_old_vec) + WRITE_ONCE(vec->move_next, move_vec); + else + WRITE_ONCE(vec->move_prev, move_vec); /* Mark the vector as dirty and synchronize */ bitmap_set(lpriv->dirty_bitmap, vec->local_id, 1); @@ -322,8 +359,8 @@ void imsic_vector_move(struct imsic_vector *old_vec, struct imsic_vector *new_ve * interrupt on the old vector while device was being moved * to the new vector. */ - enabled = imsic_vector_move_update(old_lpriv, old_vec, false, new_vec); - imsic_vector_move_update(new_lpriv, new_vec, enabled, new_vec); + enabled = imsic_vector_move_update(old_lpriv, old_vec, true, false, new_vec); + imsic_vector_move_update(new_lpriv, new_vec, false, enabled, old_vec); } #ifdef CONFIG_GENERIC_IRQ_DEBUGFS @@ -386,7 +423,8 @@ struct imsic_vector *imsic_vector_alloc(unsigned int hwirq, const struct cpumask vec = &lpriv->vectors[local_id]; vec->hwirq = hwirq; vec->enable = false; - vec->move = NULL; + vec->move_next = NULL; + vec->move_prev = NULL; return vec; } diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h index 391e44280827..f02842b84ed5 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -23,7 +23,8 @@ struct imsic_vector { unsigned int hwirq; /* Details accessed using local lock held */ bool enable; - struct imsic_vector *move; + struct imsic_vector *move_next; + struct imsic_vector *move_prev; }; struct imsic_local_priv { @@ -74,7 +75,7 @@ static inline void __imsic_id_clear_enable(unsigned long id) __imsic_eix_update(id, 1, false, false); } -void imsic_local_sync_all(void); +void imsic_local_sync_all(bool force_all); void imsic_local_delivery(bool enable); void imsic_vector_mask(struct imsic_vector *vec); @@ -87,7 +88,7 @@ static inline bool imsic_vector_isenabled(struct imsic_vector *vec) static inline struct imsic_vector *imsic_vector_get_move(struct imsic_vector *vec) { - return READ_ONCE(vec->move); + return READ_ONCE(vec->move_prev); } void imsic_vector_move(struct imsic_vector *old_vec, struct imsic_vector *new_vec); From patchwork Sun Feb 9 04:16:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13966644 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30740C02199 for ; Sun, 9 Feb 2025 04:31:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=RoqQmmMLZnhmH7e8y5iCPOfAA2UjM+1/YD5gOA06f3E=; b=4LBw486Oroj6LHyWXiBYHkj83L K0BKkzmxtk28BOv0CRHJSgL9Vpgqz5bzKPQs0+ip32eA6dlQ6wOrWLo1GRLWRc4VHRo1ahC4i8ftm OJe5lFyIUeTxIDMh7d1t2eTmcMu7hpmTsJcqiQZwvL2bQXUWRl7UWtQM1zIUZ39xJmuvK2pzW/T7X O0VtOATFt0hyJFjqTc2pHfPknk/DlR22WWdu2CGgAFwtDCIuCxbaGsS5Z6u60i1sH7FshORw4uKa5 y3ntnyO1nMX+tgIgJVmTLJQug5CUjFENid06NhQLJ7r383cXuji3j3g0k/M8vzSx1inhbGRXzp+69 xQtR3pFA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tgyyb-0000000E4tE-436X; Sun, 09 Feb 2025 04:31:26 +0000 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tgym8-0000000E2eS-2CpQ for linux-arm-kernel@lists.infradead.org; Sun, 09 Feb 2025 04:18:33 +0000 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-21f5268cf50so26802235ad.1 for ; Sat, 08 Feb 2025 20:18:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1739074712; x=1739679512; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RoqQmmMLZnhmH7e8y5iCPOfAA2UjM+1/YD5gOA06f3E=; b=GbtDVINbpEfX8FglJJetZ8ZfLA/+Sf8zkwhN8rL4+Za8TsXPOsM3IPokkgpKAWGuL8 U6OAiEVDGia0Wr5GA6yxGdVaOZbtbLVa8yu5k/wa3yuvOgJ/WXXC3JM8Mp4BayhCCOlj yoZ21NXDFPsuHqE+/6X4tcUOkSUw9bNq/TM2r/wwGHZg9u7wkWM0XjGuejKoLn+UKe3J uH+E5clDWfqS5KgFrFJE3oHj1xz2KGzM00VA6SLrYvQWTJavKOjA3isrhoPTHIJuWcQc ijjIaHZJ/95PFFBE/keBI3zYaWTpE03B/lDd/0KJ+k/Ipeu1I6lCvfGcXIVYCwacdHjN oNoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739074712; x=1739679512; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RoqQmmMLZnhmH7e8y5iCPOfAA2UjM+1/YD5gOA06f3E=; b=g3+Pi5umQ4X3bKVabCSAY6oitig9OQEZyomI0decjgxoq+NpJ0Me2aS+jNYpIcaRPe VwAyK4gTrTsrHUJXu6l/No1KxM18FTfF6mJQpfny2BLyMN6pEa2bkUg6rOEIkKvk+pe5 ruaD6UfcZ8MW3cV8GNHG4MZT2ichDRD9TtNMzl0V8gww/S2dwid/TvyE75JScnvSgTYv D2UGu+OGbJsme6tDx3/LBao7uI8VfKnFwAc2RMhpTlEn0g6go3NB5iaZsyHil15Y2YOE hsHEI37Ih3RCJCI71mycSBTjq58dY5Su6242EXy6XP59KIV2tbVLNxctdppo8bRE7ba3 7q0A== X-Forwarded-Encrypted: i=1; AJvYcCVsaEIQ5CZaKWKMGihNRsuE77nret+RuSIEaZF3r0XGRstGPWYTRn6mi8JcB4XvOk5+r4C7EH9J3vTpFNYlACWP@lists.infradead.org X-Gm-Message-State: AOJu0YwyklSsGAEwZDbEXb52SPMzOe+Gy/gADluxYzj78LkjYr93NFx4 C6M+XukbXJAUzFX01ZFIV50/Ajty4NX+wphYJ5IgzqEkajRWw6kIrKyKhqv4lOg= X-Gm-Gg: ASbGncvnt6joBvCnT1KeOkZP/a5SRLIndaqMdtdy5+mvzV91L5TcVGxHEt0kIb//Sem tM04EDW3MSHL7uGlUizl8xDMXu64YDiKBbyJiT3oz+XQyYpQ5CUkHWrrMFI869tEXH+oubfafIN +2+eOZu0X7shrVsPPDMmNEZGXppB//AihJw52kxO/hLKBXdARGKe+14Cm6ifroJN8Dvt5/SM4As 9ko4WEm7tES1UDUrSQ6Akt0bvWbnf2aZJjpv2M7/IVkWttW8RX3rWuZoJY4oOuFFu3CzzqmNxzY eHXLs99X/3zwEGFor7l4isDRX3HvBzt+1pcJ72rVYaQMAgvRCkbYRJg= X-Google-Smtp-Source: AGHT+IGE4yR6cgBkkvQcZ0IHX6BsNq+H8UInEThSWisvqbLPPoF9w9oT5fD4cZTzd5CMtWIib7XuTw== X-Received: by 2002:a05:6300:6f82:b0:1ee:1910:803f with SMTP id adf61e73a8af0-1ee191082f5mr4625773637.42.1739074711624; Sat, 08 Feb 2025 20:18:31 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73073eba116sm1898410b3a.124.2025.02.08.20.18.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2025 20:18:31 -0800 (PST) From: Anup Patel To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: hpa@zytor.com, Marc Zyngier , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Palmer Dabbelt , Paul Walmsley , Atish Patra , Andrew Jones , Sunil V L , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel Subject: [PATCH v5 09/11] irqchip/riscv-imsic: Implement irq_force_complete_move() for IMSIC Date: Sun, 9 Feb 2025 09:46:53 +0530 Message-ID: <20250209041655.331470-10-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250209041655.331470-1-apatel@ventanamicro.com> References: <20250209041655.331470-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250208_201832_604540_5D960EC8 X-CRM114-Status: GOOD ( 15.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Implement irq_force_complete_move() for IMSIC driver so that in-flight vector movements on a CPU can be cleaned-up when the CPU goes down. Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-imsic-platform.c | 32 ++++++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-state.c | 17 ++++++++++++ drivers/irqchip/irq-riscv-imsic-state.h | 1 + 3 files changed, 50 insertions(+) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index 9a5e7b4541f6..b9e3f9030bdf 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -129,6 +129,37 @@ static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask return IRQ_SET_MASK_OK_DONE; } + +static void imsic_irq_force_complete_move(struct irq_data *d) +{ + struct imsic_vector *mvec, *vec = irq_data_get_irq_chip_data(d); + unsigned int cpu = smp_processor_id(); + + if (WARN_ON(!vec)) + return; + + /* Do nothing if there is no in-flight move */ + mvec = imsic_vector_get_move(vec); + if (!mvec) + return; + + /* Do nothing if the old IMSIC vector does not belong to current CPU */ + if (mvec->cpu != cpu) + return; + + /* + * The best we can do is force cleanup the old IMSIC vector. + * + * The challenges over here are same as x86 vector domain so + * refer to the comments in irq_force_complete_move() function + * implemented at arch/x86/kernel/apic/vector.c. + */ + + /* Force cleanup in-flight move */ + pr_info("IRQ fixup: irq %d move in progress, old vector cpu %d local_id %d\n", + d->irq, mvec->cpu, mvec->local_id); + imsic_vector_force_move_cleanup(vec); +} #endif static struct irq_chip imsic_irq_base_chip = { @@ -137,6 +168,7 @@ static struct irq_chip imsic_irq_base_chip = { .irq_unmask = imsic_irq_unmask, #ifdef CONFIG_SMP .irq_set_affinity = imsic_irq_set_affinity, + .irq_force_complete_move = imsic_irq_force_complete_move, #endif .irq_retrigger = imsic_irq_retrigger, .irq_compose_msi_msg = imsic_irq_compose_msg, diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c index 96e994443fc7..5ec2b6bdffb2 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -311,6 +311,23 @@ void imsic_vector_unmask(struct imsic_vector *vec) raw_spin_unlock(&lpriv->lock); } +void imsic_vector_force_move_cleanup(struct imsic_vector *vec) +{ + struct imsic_local_priv *lpriv; + struct imsic_vector *mvec; + unsigned long flags; + + lpriv = per_cpu_ptr(imsic->lpriv, vec->cpu); + raw_spin_lock_irqsave(&lpriv->lock, flags); + + mvec = READ_ONCE(vec->move_prev); + WRITE_ONCE(vec->move_prev, NULL); + if (mvec) + imsic_vector_free(mvec); + + raw_spin_unlock_irqrestore(&lpriv->lock, flags); +} + static bool imsic_vector_move_update(struct imsic_local_priv *lpriv, struct imsic_vector *vec, bool is_old_vec, bool new_enable, struct imsic_vector *move_vec) diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h index f02842b84ed5..19dea0c77738 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -91,6 +91,7 @@ static inline struct imsic_vector *imsic_vector_get_move(struct imsic_vector *ve return READ_ONCE(vec->move_prev); } +void imsic_vector_force_move_cleanup(struct imsic_vector *vec); void imsic_vector_move(struct imsic_vector *old_vec, struct imsic_vector *new_vec); struct imsic_vector *imsic_vector_from_local_id(unsigned int cpu, unsigned int local_id); From patchwork Sun Feb 9 04:16:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13966645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E8ABC02199 for ; Sun, 9 Feb 2025 04:32:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2uqH0LlhZdZ1/ZJgerOy14gnMEDsVqG8t0Fz3f/FUy8=; b=b83DQE/nQDG2fEovCTUrOwKlww 210yeGWiRicAm9OudVLyCXMdiLjPVdnECAdjX7BymgyveIVUxlyJ6/CZG+px8VE/piYVAPj3bgN9C 5wZ8HoV7IXzG5QFOhtzIka9oSJaddSoaojfIhAx9nk1u/W3c0F9wA4zi+AVR+q9lRmXIGRK/Yy6q3 0ZPlPVcVjnww2pl8yq6t/qw1Nix4gPW6Y+TQv8rxaOq1ezwnQoU0dgN9xBpGuyCavli4towXgVC82 bQ7OSOER1T1nmfIBZnvjn7W14S2bezWu+z5UHneNTSTOVUpZRURM383HRRjsvXUEcFWSsF2UMAVX5 /Q+XdP3w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tgyzx-0000000E504-3Joe; Sun, 09 Feb 2025 04:32:49 +0000 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tgymG-0000000E2hG-3ock for linux-arm-kernel@lists.infradead.org; Sun, 09 Feb 2025 04:18:42 +0000 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-2fa1a3c88c5so3873385a91.3 for ; Sat, 08 Feb 2025 20:18:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1739074720; x=1739679520; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2uqH0LlhZdZ1/ZJgerOy14gnMEDsVqG8t0Fz3f/FUy8=; b=TOi2f7YvdDCI1YjIVnHfKIIF8HkLUwjeIIZnsYt1FpeMDq8GS8dYcnqKnRrIxxllmv RV2RecWq4oSy5K+GfVEBYzmlw5t2YUzxVbU6XVk2e9zghV2XPoMr9WGwuBYdabjJ7p80 Ww+phkPZCVkPhxdJoOE+/JqMKb1t70Kk9KIdZymLjV/WotyoLAaYiL01a9smS6DEn5zy qn6StW9LEDnkurjITnRdEMxJhC3CieCsW/a6F3rxGiCwO0TdWStFBS55ihQU1X1C2E9Q mIS/y7NvaXCRXhLPPfJlKDnbiDMMKrIrI7MALnXC6nteANOJRbIkc9EenfLs4/KDjsmC VQ8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739074720; x=1739679520; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2uqH0LlhZdZ1/ZJgerOy14gnMEDsVqG8t0Fz3f/FUy8=; b=g+gc72xKnFQcWmWHwqGHPhbul+mRslQyIjoDhMzGvOhYg1iIRdkzaQniLseppP6Y6l i0osYwqaZpB79JelbSxPhIL4ZWvZHeDNszHpo8o/UxrWwc+uIpRANOc+zW2j5Up2/ubs /xvWP6EWDESYG4MosqFVe8SYiXukLttp2kdK6ASTJIspCPrTKw7KEEMpUefl0pyeSE6G Q2GKbfazTf6Fwt+uKn0DdJczOkou2Myb051xU1QgIRPV9kHFO7RERVss73wKE489Lt+0 vtTnIwE655JMZQh0pWBcAguNkfatqdCfoDzglAr2VTX0VHTG8OjnQq3A9BwrX0/iptth lMgw== X-Forwarded-Encrypted: i=1; AJvYcCWe7XavAzDlFbw2a+XHWnIEhA28Juqjce2dehE847lkPsWd3Pfy1QDOfFENWwafpWUFUNsg3rJnWt1dPEpJmn3h@lists.infradead.org X-Gm-Message-State: AOJu0Yxin+HLrs8N0ePzLZ5yIX0N01FfcO2+aC4SVYC3w5FbR0N4sUlc VVKDEBp+rkk+PCUmwnnG36neChh12UhMlC3O+TdGdVJTgmU5P5KfjULmlZE91ko= X-Gm-Gg: ASbGnctH4KJ035B1pcqTz+OsyHyheZeJYM8s02YCaq57NrqUVf8g/mSym1ifxizQhhS f18zahs5Ofk1exWux5OT73mNe3rsYxQMXNhaQ0/0TD+8U9riiez3atwaJamMpmDnw7gk1HpCbms VVNqVU1OBvel1iVBOo7jfUCJ1qEuJIEKqNi0VK223P2Z4CE8vP6wLmdElUv6bBzIo+r4MUC0MSu 8Auc5hlzx27YnkfGPJbV2SJdSKsgTf9R8XB3k4N6lULP2aJigjOJV0rNVjVrIK3EX26vuXUx+uv 9zunG8ABW5bdK2hKKySU2kAxck5TMfwagfhSu2W+IdtvAWkAEYsGJxM= X-Google-Smtp-Source: AGHT+IHUzy54yYs2fS4vJemZHOHOIs8APlSMaPpVV2klzUoQAT+FU5F1TyPBFlToppvPWeQiJJcXfw== X-Received: by 2002:a05:6a00:949a:b0:730:75b1:720a with SMTP id d2e1a72fcca58-73075b1752dmr5977536b3a.23.1739074719968; Sat, 08 Feb 2025 20:18:39 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73073eba116sm1898410b3a.124.2025.02.08.20.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2025 20:18:39 -0800 (PST) From: Anup Patel To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: hpa@zytor.com, Marc Zyngier , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Palmer Dabbelt , Paul Walmsley , Atish Patra , Andrew Jones , Sunil V L , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel Subject: [PATCH v5 10/11] irqchip/riscv-imsic: Replace hwirq with irq in the IMSIC vector Date: Sun, 9 Feb 2025 09:46:54 +0530 Message-ID: <20250209041655.331470-11-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250209041655.331470-1-apatel@ventanamicro.com> References: <20250209041655.331470-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250208_201840_950938_8B236B15 X-CRM114-Status: GOOD ( 17.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently, the imsic_handle_irq() uses generic_handle_domain_irq() to handle the irq which internally has an extra step of resolving hwirq using domain. This extra step can be avoided by replacing hwirq with irq in the IMSIC vector and directly calling generic_handle_irq(). Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-imsic-early.c | 6 ++---- drivers/irqchip/irq-riscv-imsic-platform.c | 2 +- drivers/irqchip/irq-riscv-imsic-state.c | 8 ++++---- drivers/irqchip/irq-riscv-imsic-state.h | 4 ++-- 4 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c index b5def6268936..d2e8ed70d396 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -73,7 +73,7 @@ static int __init imsic_ipi_domain_init(void) { return 0; } static void imsic_handle_irq(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); - int err, cpu = smp_processor_id(); + int cpu = smp_processor_id(); struct imsic_vector *vec; unsigned long local_id; @@ -103,9 +103,7 @@ static void imsic_handle_irq(struct irq_desc *desc) continue; } - err = generic_handle_domain_irq(imsic->base_domain, vec->hwirq); - if (unlikely(err)) - pr_warn_ratelimited("hwirq 0x%x mapping not found\n", vec->hwirq); + generic_handle_irq(vec->irq); } chained_irq_exit(chip, desc); diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index b9e3f9030bdf..6bf5d63f614e 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -111,7 +111,7 @@ static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask return -EBUSY; /* Get a new vector on the desired set of CPUs */ - new_vec = imsic_vector_alloc(old_vec->hwirq, mask_val); + new_vec = imsic_vector_alloc(old_vec->irq, mask_val); if (!new_vec) return -ENOSPC; diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c index 5ec2b6bdffb2..d0148e48ab05 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -422,7 +422,7 @@ struct imsic_vector *imsic_vector_from_local_id(unsigned int cpu, unsigned int l return &lpriv->vectors[local_id]; } -struct imsic_vector *imsic_vector_alloc(unsigned int hwirq, const struct cpumask *mask) +struct imsic_vector *imsic_vector_alloc(unsigned int irq, const struct cpumask *mask) { struct imsic_vector *vec = NULL; struct imsic_local_priv *lpriv; @@ -438,7 +438,7 @@ struct imsic_vector *imsic_vector_alloc(unsigned int hwirq, const struct cpumask lpriv = per_cpu_ptr(imsic->lpriv, cpu); vec = &lpriv->vectors[local_id]; - vec->hwirq = hwirq; + vec->irq = irq; vec->enable = false; vec->move_next = NULL; vec->move_prev = NULL; @@ -451,7 +451,7 @@ void imsic_vector_free(struct imsic_vector *vec) unsigned long flags; raw_spin_lock_irqsave(&imsic->matrix_lock, flags); - vec->hwirq = UINT_MAX; + vec->irq = 0; irq_matrix_free(imsic->matrix, vec->cpu, vec->local_id, false); raw_spin_unlock_irqrestore(&imsic->matrix_lock, flags); } @@ -510,7 +510,7 @@ static int __init imsic_local_init(void) vec = &lpriv->vectors[i]; vec->cpu = cpu; vec->local_id = i; - vec->hwirq = UINT_MAX; + vec->irq = 0; } } diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h index 19dea0c77738..3202ffa4e849 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -20,7 +20,7 @@ struct imsic_vector { unsigned int cpu; unsigned int local_id; /* Details saved by driver in the vector */ - unsigned int hwirq; + unsigned int irq; /* Details accessed using local lock held */ bool enable; struct imsic_vector *move_next; @@ -96,7 +96,7 @@ void imsic_vector_move(struct imsic_vector *old_vec, struct imsic_vector *new_ve struct imsic_vector *imsic_vector_from_local_id(unsigned int cpu, unsigned int local_id); -struct imsic_vector *imsic_vector_alloc(unsigned int hwirq, const struct cpumask *mask); +struct imsic_vector *imsic_vector_alloc(unsigned int irq, const struct cpumask *mask); void imsic_vector_free(struct imsic_vector *vector); void imsic_vector_debug_show(struct seq_file *m, struct imsic_vector *vec, int ind); From patchwork Sun Feb 9 04:16:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13966684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C7F8C02199 for ; Sun, 9 Feb 2025 05:46:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=KEjndyBD35lV6nr6NSLWRRyly4db2axy7koFOHZTKsQ=; b=k3x7qT/Iqo9+EXzlyioTYLxuJv ysI2/cZHVGg5muNtFy9ZkTgQFXOPk+iOUdwCkQL07z3pslBttJthhK2HZNWkYvj11KP3NM4LcmJiR cjyttQc50l+2JDdaJLSFQDNLHnJN6tvTh0u87kaLBJCiJe0QU5gg5bAfZQetRFpLEbhtkIfrSkHzo wlNzSUAqjndqnwcygQr36SU4FrwA/+Rug67X4TbOQl6G+64f0trEgXxA5AQjoT5PudnPqvICreZa6 0rCqf2a472mWezfzubCGDpdpcVgKgWwl5BjUP/LCwnKeAZ/dlbG6ohZqBYZBAkPz4wDuN9AA0LhY0 wzo7N+Cw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1th09S-0000000EAm3-1ItJ; Sun, 09 Feb 2025 05:46:42 +0000 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tgymP-0000000E2lY-396E for linux-arm-kernel@lists.infradead.org; Sun, 09 Feb 2025 04:18:51 +0000 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-2f44353649aso4859293a91.0 for ; Sat, 08 Feb 2025 20:18:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1739074729; x=1739679529; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KEjndyBD35lV6nr6NSLWRRyly4db2axy7koFOHZTKsQ=; b=CrX4FJud+8PLqilHcLMUJvGFX7l5ypDZVsamK/wbsufkTHijrWP/+DSRasNrGY5zbm geBTq639QkwYl6YLUvOJnqZi0RaZAI8jcGQfCoInMN+awl6ox/kfDiXJXh/jlcxMfW5S 799Jr+cBnYbVffEC1R3ANniIB4qUFpDH0FEV2WEJTqAkFFRFfFbREr/qSFaovQfMmHF1 cPriR6IVo+abpImm1YLLctjhSXqtxmG3TZvAnQeuWxTrw2UYWVMzlDau5+Xg1Hk3cYAx IN0JybrYii/v4L8iu19vngNVrVzUxitkwqY7gBIvHs2iFc/Ur0fdBincBFXluy/Dtb5d VYCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739074729; x=1739679529; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KEjndyBD35lV6nr6NSLWRRyly4db2axy7koFOHZTKsQ=; b=rTswRc8ReyOLFck5n0lVyHOLTBJ0SoBvnSPyZrz06KrBBh/a/ReRKNbyk5R7kJehOY pHK2Hulw3FOJ0qaFjc9y7LTMjbXsx2TArSh/1w9KlthGs3OfqX2lz8kxXkrLdaY3b1pL tasSZRtjH9/GWXmcscMhrH8+NjZR8JzYQMaAuhmc0tOxt4aBU8BAN2YakuiXuDMHmN6K UqnVx6F8MWw2bVS2GHayjQdJ/dZjSQm+ZARuAXKL8RoJyeP0bIdgbqtt8kDtyjLQdvUO B9M/+Cf5HlZPI2npZ5PbVWKgTEWeAcItxbk/EFBKdyvY4Gl54jGVUG71StZnQOylMRWz W7RQ== X-Forwarded-Encrypted: i=1; AJvYcCUKd07p0tOaPciQz9Ieul3+BMPHTLXDR0ZBYEIsyAXaFwq+tdm3hG8rLCPv5aAt2pelXmXG8NW+WzFhb5SjM1mb@lists.infradead.org X-Gm-Message-State: AOJu0YxHAzZvVU8eygpXwL6T01nqPYz5dSwK4cSvXK9gpKTPcaPolXR+ ule5fCdf5+6sr6t45x1Z1sHdE4nbK7upYZAv7HXyUPtjJ8frjW7dEIr2dRMDW9k= X-Gm-Gg: ASbGncv8+P1+uP1aNygm6GQhHWAbmU9HP4RXvn6shRKtaVnjt8LFHOTsIg+YdZz3b/X p1GPouliyHrPQNT1WE9vjjAf5exgR0RWRnV9gMcgPMeYP2FS3oc37xFdHgVxBi/rjahhF9jYpzi DfG62uozXzrouVNeQhZ+y8WrDwwLQtwEzVq3DCdxGVZe+CQeN0CaKHoEwPvR82NSwdjXj/3Sl6M 8Y83rVedkLyVzWhPP7Pb8L/1tnrchOOOvpctLwd+aBhsWkPeWOARGru1F1RxNTXDmPx8R/pMmQk t0a4jhci+RKp8BmW/Q8FXuzKSdLfbOiAsnZzlhtj6uV4RBXWeTOZWZ0= X-Google-Smtp-Source: AGHT+IFzlqSdIaYHLSZI599cWVBA7dW7jlgFu/OL/NbLRylvBc/ItMiequCd7pzuj7u4ZD8d08JvJw== X-Received: by 2002:a05:6a00:2342:b0:730:7d3f:8c70 with SMTP id d2e1a72fcca58-7307d3f9339mr5011190b3a.21.1739074728662; Sat, 08 Feb 2025 20:18:48 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73073eba116sm1898410b3a.124.2025.02.08.20.18.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2025 20:18:48 -0800 (PST) From: Anup Patel To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: hpa@zytor.com, Marc Zyngier , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Palmer Dabbelt , Paul Walmsley , Atish Patra , Andrew Jones , Sunil V L , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel Subject: [PATCH v5 11/11] irqchip/riscv-imsic: Special handling for non-atomic device MSI update Date: Sun, 9 Feb 2025 09:46:55 +0530 Message-ID: <20250209041655.331470-12-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250209041655.331470-1-apatel@ventanamicro.com> References: <20250209041655.331470-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250208_201849_784009_38A9F752 X-CRM114-Status: GOOD ( 23.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Device having non-atomic MSI update might see an intermediate state when changing target IMSIC vector from one CPU to another. To avoid losing interrupt to such intermediate state, do the following (just like x86 APIC): 1) First write a temporary IMSIC vector to the device which has MSI address same as the old IMSIC vector but with MSI data matches the new IMSIC vector. 2) Next write the new IMSIC vector to the device. Based on the above, the __imsic_local_sync() must check pending status of both old MSI data and new MSI data on the old CPU. In addition, the movement of IMSIC vector for non-atomic device MSI update must be done in interrupt context using IRQCHIP_MOVE_DEFERRED. Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-imsic-platform.c | 73 +++++++++++++++++++++- drivers/irqchip/irq-riscv-imsic-state.c | 31 +++++++-- 2 files changed, 98 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index 6bf5d63f614e..828102c46f51 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -64,6 +64,11 @@ static int imsic_irq_retrigger(struct irq_data *d) return 0; } +static void imsic_irq_ack(struct irq_data *d) +{ + irq_move_irq(d); +} + static void imsic_irq_compose_vector_msg(struct imsic_vector *vec, struct msi_msg *msg) { phys_addr_t msi_addr; @@ -97,6 +102,21 @@ static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask bool force) { struct imsic_vector *old_vec, *new_vec; + struct imsic_vector tmp_vec; + + /* + * Requirements for the downstream irqdomains (or devices): + * + * 1) Downstream irqdomains (or devices) with atomic MSI update can + * happily do imsic_irq_set_affinity() in the process-context on + * any CPU so the irqchip of such irqdomains must not set the + * IRQCHIP_MOVE_DEFERRED flag. + * + * 2) Downstream irqdomains (or devices) with non-atomic MSI update + * must do imsic_irq_set_affinity() in the interrupt-context upon + * next interrupt so the irqchip of such irqdomains must set the + * IRQCHIP_MOVE_DEFERRED flag. + */ old_vec = irq_data_get_irq_chip_data(d); if (WARN_ON(!old_vec)) @@ -115,6 +135,33 @@ static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask if (!new_vec) return -ENOSPC; + /* + * Device having non-atomic MSI update might see an intermediate + * state when changing target IMSIC vector from one CPU to another. + * + * To avoid losing interrupt to such intermediate state, do the + * following (just like x86 APIC): + * + * 1) First write a temporary IMSIC vector to the device which + * has MSI address same as the old IMSIC vector but MSI data + * matches the new IMSIC vector. + * + * 2) Next write the new IMSIC vector to the device. + * + * Based on the above, the __imsic_local_sync() must check pending + * status of both old MSI data and new MSI data on the old CPU. + */ + + if (!irq_can_move_in_process_context(d) && + new_vec->local_id != old_vec->local_id) { + /* Setup temporary vector */ + tmp_vec.cpu = old_vec->cpu; + tmp_vec.local_id = new_vec->local_id; + + /* Point device to the temporary vector */ + imsic_msi_update_msg(irq_get_irq_data(d->irq), &tmp_vec); + } + /* Point device to the new vector */ imsic_msi_update_msg(irq_get_irq_data(d->irq), new_vec); @@ -171,6 +218,7 @@ static struct irq_chip imsic_irq_base_chip = { .irq_force_complete_move = imsic_irq_force_complete_move, #endif .irq_retrigger = imsic_irq_retrigger, + .irq_ack = imsic_irq_ack, .irq_compose_msi_msg = imsic_irq_compose_msg, .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, @@ -190,7 +238,7 @@ static int imsic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, return -ENOSPC; irq_domain_set_info(domain, virq, virq, &imsic_irq_base_chip, vec, - handle_simple_irq, NULL, NULL); + handle_edge_irq, NULL, NULL); irq_set_noprobe(virq); irq_set_affinity(virq, cpu_online_mask); irq_data_update_effective_affinity(irq_get_irq_data(virq), cpumask_of(vec->cpu)); @@ -229,15 +277,36 @@ static const struct irq_domain_ops imsic_base_domain_ops = { #endif }; +static bool imsic_init_dev_msi_info(struct device *dev, + struct irq_domain *domain, + struct irq_domain *real_parent, + struct msi_domain_info *info) +{ + if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) + return false; + + switch (info->bus_token) { + case DOMAIN_BUS_PCI_DEVICE_MSI: + case DOMAIN_BUS_PCI_DEVICE_MSIX: + info->chip->flags |= IRQCHIP_MOVE_DEFERRED; + break; + default: + break; + } + + return true; +} + static const struct msi_parent_ops imsic_msi_parent_ops = { .supported_flags = MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX, .required_flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_PCI_MSI_MASK_PARENT, + .chip_flags = MSI_CHIP_FLAG_SET_ACK, .bus_select_token = DOMAIN_BUS_NEXUS, .bus_select_mask = MATCH_PCI_MSI | MATCH_PLATFORM_MSI, - .init_dev_msi_info = msi_lib_init_dev_msi_info, + .init_dev_msi_info = imsic_init_dev_msi_info, }; int imsic_irqdomain_init(void) diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c index d0148e48ab05..3a2a381e4fa1 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -126,8 +126,8 @@ void __imsic_eix_update(unsigned long base_id, unsigned long num_id, bool pend, static bool __imsic_local_sync(struct imsic_local_priv *lpriv) { - struct imsic_local_config *mlocal; - struct imsic_vector *vec, *mvec; + struct imsic_local_config *tlocal, *mlocal; + struct imsic_vector *vec, *tvec, *mvec; bool ret = true; int i; @@ -169,13 +169,36 @@ static bool __imsic_local_sync(struct imsic_local_priv *lpriv) */ mvec = READ_ONCE(vec->move_next); if (mvec) { - if (__imsic_id_read_clear_pending(i)) { + /* + * Device having non-atomic MSI update might see an + * intermediate state so check both old ID and new ID + * for pending interrupts. + * + * For details, refer imsic_irq_set_affinity(). + */ + + tvec = vec->local_id == mvec->local_id ? + NULL : &lpriv->vectors[mvec->local_id]; + if (tvec && + !irq_can_move_in_process_context(irq_get_irq_data(vec->irq)) && + __imsic_id_read_clear_pending(tvec->local_id)) { + /* Retrigger temporary vector if it was already in-use */ + if (READ_ONCE(tvec->enable)) { + tlocal = per_cpu_ptr(imsic->global.local, tvec->cpu); + writel_relaxed(tvec->local_id, tlocal->msi_va); + } + + mlocal = per_cpu_ptr(imsic->global.local, mvec->cpu); + writel_relaxed(mvec->local_id, mlocal->msi_va); + } + + if (__imsic_id_read_clear_pending(vec->local_id)) { mlocal = per_cpu_ptr(imsic->global.local, mvec->cpu); writel_relaxed(mvec->local_id, mlocal->msi_va); } WRITE_ONCE(vec->move_next, NULL); - imsic_vector_free(&lpriv->vectors[i]); + imsic_vector_free(vec); } skip: