From patchwork Sun Feb 9 18:05:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13967033 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mout-p-201.mailbox.org (mout-p-201.mailbox.org [80.241.56.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30DE31DED7B; Sun, 9 Feb 2025 18:06:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739124411; cv=none; b=h2OdgASFhz1pIEuHnX+D27Yv7tKa6TxdhFErGiyR+RF1mrxTzooVfgJTEZqrngTq8oXOA7FWxmLYwgBNQax3Gw+cBUQUQMqISKtOG32efPO/A/nYZMZ8SiNNGi8nmLkNc+AUkkq0Abs3oma+UYa6WmYytAoDksyCh8I6quHPPX8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739124411; c=relaxed/simple; bh=wROsXHBZE2aYv+GIrY4VjtMCQniSAtS385enm4ggRIw=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=VAvjVWvuNunvZwsZLYiP5E3tkC6ls1t5/yzqnZ4fv0F4JwYJHw6t9ipVF+/7j4kVu8AnYzoK21VEe+R96MdCc3P7JAnxJTy1/T+Q46S9+2CEWu4Ks8mKIY46qXbYZxaur/FpNzr0j6fAxIP3bI9gC5YunV/IWo8VeGVyellvDsk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=LT0YSKEO; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=CbxD3MUm; arc=none smtp.client-ip=80.241.56.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="LT0YSKEO"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="CbxD3MUm" Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:b231:465::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-201.mailbox.org (Postfix) with ESMTPS id 4YrbJ70hSXz9sT9; Sun, 9 Feb 2025 19:06:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1739124407; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=nm11C/vSYVh8GDGZHfUDlNWNTOIXtOIJnLqiD9TfA30=; b=LT0YSKEO3djex7KccBfSv4i9sBZRBCpbZulGIXRWB//eIALQSvu+jXYJ6t2nLYxtU9LY+o QlY+HYZeIaSqKAFWhyUJ3H/tMDyNcCyHqnemZPgd0z1Jn58J3qmDPJ2/5Pglfdxa0Ajz1h ryy8X3XZizY4oZ46SqLaVMiDvPPNMF1TRLD1aLHmvAu3SUFeQ/EeXYu9ktjSlGj4BMVXFg kSEjHVmNedOHGzMLFmc+tkHM12bzDNMyS+E7g5dx3qscuvTyqnZGScVcziTZTH45u+xaNO EkPqJydcaZEO6r7kIYcCJ+wddtVYY3WfZYp41keoDf51YReFZAulGynXuUWDgw== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1739124405; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=nm11C/vSYVh8GDGZHfUDlNWNTOIXtOIJnLqiD9TfA30=; b=CbxD3MUmPHTnrpZ3WCNsog2yv5L1Bl4V7TcfZ58C5Xz5KqPU9pRuXwJVhGI2x4qbtCgt88 B3aPlZJ9kmlrGGnWiWpoUU+dRM9EO00ihmsQgx0Rt1TX/+49tGw8B7LRFFnG/NsfZR+9I2 yk0Woz80IsOhjv/VX1qkUhgepFo1cVGL6w4li76kihQeFpV7sWLn/YJsiXZEtHMkgOZ6tA iGF88JsoG6K+7NiwD3OEYq7wWwi7lWIloy0KgsO3fTCKejkWYVFaEN3zm8T1lMay0BpjRy B1rpKEZFhs3a+JM7nDxdfO+wjJyPXe2hvG9iUvO/aD6Cx5xeyy5FsOG51dp4hQ== To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Magnus Damm , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH 1/3] ARM: dts: renesas: Add boot phase tags marking to Renesas R-Car Gen2 Date: Sun, 9 Feb 2025 19:05:04 +0100 Message-ID: <20250209180616.160253-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MBO-RS-ID: 8782ec19eb1986f3ac3 X-MBO-RS-META: eipw4xkzyxtdpo8sx8gou768iuz3unnu X-Rspamd-Queue-Id: 4YrbJ70hSXz9sT9 bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Add bootph-all for all nodes that are used in the bootloader on Renesas R-Car SoC. All SoC require CPG clock and its input clock, RST Reset, PFC pin control and PRR ID register access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains these IP. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven --- Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Magnus Damm Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- arch/arm/boot/dts/renesas/r8a7790-lager.dts | 1 + arch/arm/boot/dts/renesas/r8a7790-stout.dts | 1 + arch/arm/boot/dts/renesas/r8a7790.dtsi | 7 +++++++ arch/arm/boot/dts/renesas/r8a7791-koelsch.dts | 1 + arch/arm/boot/dts/renesas/r8a7791-porter.dts | 1 + arch/arm/boot/dts/renesas/r8a7791.dtsi | 7 +++++++ arch/arm/boot/dts/renesas/r8a7792-blanche.dts | 1 + arch/arm/boot/dts/renesas/r8a7792-wheat.dts | 1 + arch/arm/boot/dts/renesas/r8a7792.dtsi | 6 ++++++ arch/arm/boot/dts/renesas/r8a7793-gose.dts | 1 + arch/arm/boot/dts/renesas/r8a7793.dtsi | 7 +++++++ arch/arm/boot/dts/renesas/r8a7794-alt.dts | 1 + arch/arm/boot/dts/renesas/r8a7794-silk.dts | 1 + arch/arm/boot/dts/renesas/r8a7794.dtsi | 7 +++++++ 14 files changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r8a7790-lager.dts b/arch/arm/boot/dts/renesas/r8a7790-lager.dts index 3bce5876a9d81..4f002aa7fbafc 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-lager.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-lager.dts @@ -754,6 +754,7 @@ partition@440000 { &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7790-stout.dts b/arch/arm/boot/dts/renesas/r8a7790-stout.dts index d7c0a9574ce83..b1e20579e0710 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-stout.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-stout.dts @@ -268,6 +268,7 @@ partition@100000 { &scifa0 { pinctrl-0 = <&scifa0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7790.dtsi b/arch/arm/boot/dts/renesas/r8a7790.dtsi index f746f0b9e686b..4f97c09dbc9fe 100644 --- a/arch/arm/boot/dts/renesas/r8a7790.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7790.dtsi @@ -227,6 +227,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -265,6 +266,7 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -374,6 +376,7 @@ gpio5: gpio@e6055000 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7790"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; tpu: pwm@e60f0000 { @@ -395,6 +398,7 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6151000 { @@ -412,6 +416,7 @@ apmu@e6152000 { rst: reset-controller@e6160000 { compatible = "renesas,r8a7790-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1948,6 +1953,7 @@ lvds1_out: endpoint { prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -2018,5 +2024,6 @@ usb_extal_clk: usb_extal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts index e4e1d9c98c617..e9f90fa44d551 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts @@ -679,6 +679,7 @@ &sata0 { &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791-porter.dts b/arch/arm/boot/dts/renesas/r8a7791-porter.dts index 08381498350aa..f518eadd8b9cd 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-porter.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-porter.dts @@ -312,6 +312,7 @@ audio_clk_pins: audio_clk { &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791.dtsi b/arch/arm/boot/dts/renesas/r8a7791.dtsi index e57567adff558..5023b41c28b36 100644 --- a/arch/arm/boot/dts/renesas/r8a7791.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7791.dtsi @@ -125,6 +125,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -152,6 +153,7 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -291,6 +293,7 @@ gpio7: gpio@e6055800 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7791"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; tpu: pwm@e60f0000 { @@ -312,6 +315,7 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -323,6 +327,7 @@ apmu@e6152000 { rst: reset-controller@e6160000 { compatible = "renesas,r8a7791-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1875,6 +1880,7 @@ lvds0_out: endpoint { prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1945,5 +1951,6 @@ usb_extal_clk: usb_extal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts index a3986076d8e3e..23ec0f8a66510 100644 --- a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts @@ -301,6 +301,7 @@ &rwdt { &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts index bfc780f7e396b..93bd81723c8fb 100644 --- a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts @@ -183,6 +183,7 @@ &rwdt { &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi index 08cbe6c13cee4..7513afc1c9585 100644 --- a/arch/arm/boot/dts/renesas/r8a7792.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi @@ -82,6 +82,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; lbsc: bus { @@ -109,6 +110,7 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -308,6 +310,7 @@ gpio11: gpio@e6055600 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7792"; reg = <0 0xe6060000 0 0x144>; + bootph-all; }; cpg: clock-controller@e6150000 { @@ -318,6 +321,7 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -329,6 +333,7 @@ apmu@e6152000 { rst: reset-controller@e6160000 { compatible = "renesas,r8a7792-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -947,6 +952,7 @@ du_out_rgb1: endpoint { prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { diff --git a/arch/arm/boot/dts/renesas/r8a7793-gose.dts b/arch/arm/boot/dts/renesas/r8a7793-gose.dts index 2c05d7c2b3776..45b267ec26794 100644 --- a/arch/arm/boot/dts/renesas/r8a7793-gose.dts +++ b/arch/arm/boot/dts/renesas/r8a7793-gose.dts @@ -642,6 +642,7 @@ &rwdt { &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7793.dtsi b/arch/arm/boot/dts/renesas/r8a7793.dtsi index e48e43cc6b03d..fc6d3bcca2961 100644 --- a/arch/arm/boot/dts/renesas/r8a7793.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7793.dtsi @@ -117,6 +117,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; pmu { @@ -137,6 +138,7 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -276,6 +278,7 @@ gpio7: gpio@e6055800 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7793"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; /* Special CPG clocks */ @@ -287,6 +290,7 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -298,6 +302,7 @@ apmu@e6152000 { rst: reset-controller@e6160000 { compatible = "renesas,r8a7793-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1454,6 +1459,7 @@ lvds0_out: endpoint { prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1524,5 +1530,6 @@ usb_extal_clk: usb_extal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794-alt.dts b/arch/arm/boot/dts/renesas/r8a7794-alt.dts index f70e26aa83a0a..3f06a7f67d62a 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-alt.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-alt.dts @@ -479,6 +479,7 @@ vin0ep: endpoint { &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794-silk.dts b/arch/arm/boot/dts/renesas/r8a7794-silk.dts index 2a0819311a3c4..3428256057680 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-silk.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-silk.dts @@ -394,6 +394,7 @@ audio_clk_pins: audio_clk { &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi index bc16c896c0f9b..92010d09f6c40 100644 --- a/arch/arm/boot/dts/renesas/r8a7794.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7794.dtsi @@ -99,6 +99,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; pmu { @@ -119,6 +120,7 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -243,6 +245,7 @@ gpio6: gpio@e6055400 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7794"; reg = <0 0xe6060000 0 0x11c>; + bootph-all; }; cpg: clock-controller@e6150000 { @@ -253,6 +256,7 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6151000 { @@ -264,6 +268,7 @@ apmu@e6151000 { rst: reset-controller@e6160000 { compatible = "renesas,r8a7794-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1440,6 +1445,7 @@ du_out_rgb1: endpoint { prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1491,5 +1497,6 @@ usb_extal_clk: usb_extal { compatible = "fixed-clock"; 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dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="Hkw5AEJb" Received: from smtp2.mailbox.org (smtp2.mailbox.org [10.196.197.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 4YrbJ95QwQz9tSR; Sun, 9 Feb 2025 19:06:49 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1739124409; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=njWNxD93LiZzgdoClk+Taq8PHVuP66MHoc2qhaqa6+0=; b=euk5EVPSl4Ml2wO5WUCXh2UP2AFyId4nODoLs28jRzY3tu1lgMlh1yPQHEINjAUodPE3un ZOloq5wTIuLClHR0IMYziiuKuByjM9EhIaEMPgPHpIUrUODWoIJm+UbdY0Zh+t96AEN9we DGT7vn7KCMBBl8cA2TauSovI8qUOBb6l2BNGy6jwRj1eWb60pX0K4rRIoulgI4/8on7wTS ++TaellwpvrRNbYEO4qANIOJjf7fYI0sZ0pTiZfPzLHLddocyb6AkD2je83meJd1uR1+Ld cAMXwyaYrdKiRJmxTEGegz4eyGWWrJmcNu7BEitvJ+ScOl+Ki0kKtZrRtXYx9Q== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1739124407; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=njWNxD93LiZzgdoClk+Taq8PHVuP66MHoc2qhaqa6+0=; b=Hkw5AEJbfqRvo9gLpQ31b8o4r2rJcNDrW7u/xoCu91iFBmvhSQomeN7yY/0QnctIZt3u5O xa7Zt3E6+oMTXTy55R1vNX/N0o6UDBynGsDMcrXKAEXg0r/34wGh5v0ULvLcBzLG41QlTt BayE7nJ/FSiIWNzHEwKURKmAMoie2ZIgx95j0Kyv6oFQP4Zw4aV+KL4e7wE2zys8umfE+m J9PNSd+T9DcUXZ8JqVT6jtF5XcQoi0KRa6b7L1hgHdgJyX9ugAd1WLhFOFjRCWk/i8H0rC NMP57QrFkjqLVwUK4q/Y3mhAgci54IEtZGLpGJTGLRZujH6RD2Rtn94Hd09o5w== To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Magnus Damm , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH 2/3] arm64: dts: renesas: Add boot phase tags marking to Renesas R-Car Gen3 and Gen4 Date: Sun, 9 Feb 2025 19:05:05 +0100 Message-ID: <20250209180616.160253-2-marek.vasut+renesas@mailbox.org> In-Reply-To: <20250209180616.160253-1-marek.vasut+renesas@mailbox.org> References: <20250209180616.160253-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MBO-RS-ID: 49541a8469b0a801d4d X-MBO-RS-META: bcmjzj3isfhauryr1ty8x49ef44dg538 bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Add bootph-all for all nodes that are used in the bootloader on Renesas R-Car SoC. All SoC require CPG clock and its input clock, RST Reset, PFC pin control and PRR ID register access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains these IP. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven --- Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Magnus Damm Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- arch/arm64/boot/dts/renesas/condor-common.dtsi | 1 + arch/arm64/boot/dts/renesas/draak.dtsi | 1 + arch/arm64/boot/dts/renesas/ebisu.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77951.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a77960.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a77961.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 1 + arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 1 + arch/arm64/boot/dts/renesas/r8a77970.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 1 + arch/arm64/boot/dts/renesas/r8a77980.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts | 1 + arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts | 1 + arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 1 + arch/arm64/boot/dts/renesas/ulcb.dtsi | 1 + arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi | 1 + 25 files changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi index 375a56b20f267..a105841505718 100644 --- a/arch/arm64/boot/dts/renesas/condor-common.dtsi +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -544,6 +544,7 @@ &rwdt { &scif0 { pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index 05712cd96d28b..380b857fd273e 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -695,6 +695,7 @@ &rwdt { &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index ab82836566600..4f38b01ae18de 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -786,6 +786,7 @@ &rwdt { &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 96f3b5fe7e92c..6ee9cdeb5a3ab 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -292,6 +292,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -299,6 +300,7 @@ extalr_clk: extalr { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -347,6 +349,7 @@ scif_clk: scif { soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -485,6 +488,7 @@ gpio7: gpio@e6055800 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7795"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -565,11 +569,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a7795-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -3398,6 +3404,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index ee80f52dc7cf4..a323ac47ca70f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -264,6 +264,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -271,6 +272,7 @@ extalr_clk: extalr { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -311,6 +313,8 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -449,6 +453,7 @@ gpio7: gpio@e6055800 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7796"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -529,11 +534,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a7796-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2996,6 +3003,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 3b9066043a71e..49f6d31c5903b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -264,6 +264,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -271,6 +272,7 @@ extalr_clk: extalr { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -311,6 +313,8 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -449,6 +453,7 @@ gpio7: gpio@e6055800 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77961"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -529,11 +534,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77961-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2817,6 +2824,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 557bdf8fab179..136a22ca50b78 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -143,6 +143,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -150,6 +151,7 @@ extalr_clk: extalr { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -182,6 +184,8 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -320,6 +324,7 @@ gpio7: gpio@e6055800 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77965"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -400,11 +405,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77965-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2828,6 +2835,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 32f07aa273167..8b594e9e9dc10 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -409,6 +409,7 @@ &rwdt { &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 118e77f4477e3..445f5dd7c983f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -296,6 +296,7 @@ user@1bc0000 { &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 38145fd6acf02..01744496805c3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -60,6 +60,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -67,6 +68,7 @@ extalr_clk: extalr { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a53 { @@ -91,6 +93,7 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -200,6 +203,7 @@ gpio5: gpio@e6055000 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77970"; reg = <0 0xe6060000 0 0x504>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -280,11 +284,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77970-rst"; reg = <0 0xe6160000 0 0x200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1196,6 +1202,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index b409a8d1737e6..c2692d6fd00d7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -282,6 +282,7 @@ &rwdt { &scif0 { pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 55a6c622f8732..f7e506ad7a211 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -80,6 +80,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -87,6 +88,7 @@ extalr_clk: extalr { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -120,6 +122,7 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -229,6 +232,7 @@ gpio5: gpio@e6055000 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77980"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -309,11 +313,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77980-rst"; reg = <0 0xe6160000 0 0x200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1579,6 +1585,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 233af3081e84a..5fa6aee50c114 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -118,6 +118,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -149,6 +150,8 @@ scif_clk: scif { soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -272,6 +275,7 @@ gpio6: gpio@e6055400 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77990"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; i2c_dvfs: i2c@e60b0000 { @@ -368,11 +372,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77990-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2117,6 +2123,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 5f0828a4675b6..b66cd7c90d53f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -65,6 +65,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a53 { @@ -86,6 +87,8 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -209,6 +212,7 @@ gpio6: gpio@e6055400 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77995"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -289,11 +293,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77995-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1448,6 +1454,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index e8c8fca48b696..0916fd57d1f1a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -348,6 +348,7 @@ &rwdt { &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 905285b83f0c4..f1613bfd16320 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -47,6 +47,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -54,6 +55,7 @@ extalr_clk: extalr { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a76 { @@ -71,6 +73,8 @@ scif_clk: scif { soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -93,6 +97,7 @@ pfc: pinctrl@e6050000 { <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>, <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6058180 { @@ -331,11 +336,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779a0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2973,6 +2980,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index e03baefb6a98b..1781bb79a6196 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -101,6 +101,7 @@ &extalr_clk { &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index fdc466b84d510..b496495c59a6d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -253,6 +253,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -260,6 +261,7 @@ extalr_clk: extalr { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -296,6 +298,8 @@ scif_clk: scif { soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -315,6 +319,7 @@ pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a779f0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -463,11 +468,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779f0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1283,6 +1290,7 @@ gic: interrupt-controller@f1000000 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts index df652e7b85c95..67b18f2bffbd0 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts @@ -68,6 +68,7 @@ &extalr_clk { &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 550e7dabd1da1..1760720b71287 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -166,6 +166,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -173,6 +174,7 @@ extalr_clk: extalr { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -215,6 +217,8 @@ scif_clk2: scif2 { soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -237,6 +241,7 @@ pfc: pinctrl@e6050000 { <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, <0 0xe6068000 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -452,11 +457,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779g0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2496,6 +2503,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index 99bbb8a1b7b54..4d890e0617aff 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -361,6 +361,7 @@ audio-power-hog { &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 196b433bf82c8..8524a1e7205ea 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -138,6 +138,7 @@ extal_clk: extal-clk { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr-clk { @@ -145,6 +146,7 @@ extalr_clk: extalr-clk { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -180,6 +182,8 @@ scif_clk2: scif-clk2 { soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -201,6 +205,7 @@ pfc: pinctrl@e6050000 { <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -401,11 +406,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779h0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2158,6 +2165,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 06c7e9746304f..68971c870d172 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -940,6 +940,7 @@ &scif1 { &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 0c58d816c375f..fcab957b54f70 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -448,6 +448,7 @@ &rwdt { &scif2 { pinctrl-0 = <&scif2_pins>; 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bh=wJKDfculBOHtXbp+LXdjmesbR5G8ZOrp7jrKY9ENQi4=; b=C/LILRsIo4dn0sV0YEBvXKWd63dW8wArQmfM5MR2bkiPaZ2zpowEm6hEw4uGtbW8WL3YMH AkQWG9eAp2Em/MMUla1K7lx/CNj+04oEIp3/vJ2H+ST3TSR/p4hgtN3VjzTPE2vBVoIljl rZC/yXcSmuTrq9vQwH+QRQdPNu98WLYCH5jl89WzrCCulofrG3tl5nOdoizb8t02k0IdFC 904lwsU7DPgjgZvqyP2DnrUUCwW85NIn6hEOJDFdk3Gud9PAjCQG1tyZeMiJ74tleNxYfO 3xdAYCZwryqxIATOB7u/xXltFTjKphWgxZZalu5kbGd9Jq5apvK3Gg24/bltvA== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1739124409; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wJKDfculBOHtXbp+LXdjmesbR5G8ZOrp7jrKY9ENQi4=; b=TgbRXOdyeSH5qbAx71L2kv3/YuzH+TxoPwQilILZWAtFiwcJ2tuNH7/HTC3qL9AwNAIH8O SeYfdiOq2hxPp3FumQJt7dUz1KbnGpYcaneYVLRkpb0xlsA7OmPbNyXr4hoOxpA1Zky8yP nUWe22aQa44ro/0ICOBP3yvjSZNQIJE76kPKqIN1pk4vR/7XLTe10TPbSMTcb8DWiahuZp Nx4iVKUU+hz5fZ77GxSA2OKDOmeRZI+j2li6flIUd7fGxkMNoo5Cg2rlDGqA28SspHW4BO nLAduO0x3za4X919eqq8SONI3YUNeGLaWHKscbEhg4A9BgWUHDrvVCTRdPvBNA== To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Magnus Damm , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH 3/3] arm64: dts: renesas: Add boot phase tags marking to Renesas RZ/G2 Date: Sun, 9 Feb 2025 19:05:06 +0100 Message-ID: <20250209180616.160253-3-marek.vasut+renesas@mailbox.org> In-Reply-To: <20250209180616.160253-1-marek.vasut+renesas@mailbox.org> References: <20250209180616.160253-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MBO-RS-ID: c7858d5b6611a482886 X-MBO-RS-META: sswwhmetmsnqycbsxqobmkbrftm115ge bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Add bootph-all for all nodes that are used in the bootloader on Renesas RZ/G2 SoC. All SoC require CPG clock and its input clock, RST Reset, PFC pin control and PRR ID register access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains these IP. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven --- Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Magnus Damm Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 1 + arch/arm64/boot/dts/renesas/hihope-common.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 1 + arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi | 1 + 8 files changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 43f88c199b788..1489bc8d2f4e6 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -282,6 +282,7 @@ &scif_clk { &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi index 659ae1fed2faa..4e78139d52f6c 100644 --- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi @@ -289,6 +289,7 @@ &rwdt { &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index f065ee90649a4..c8b87aed92a36 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -215,6 +215,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -222,6 +223,7 @@ extalr_clk: extalr { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -262,6 +264,8 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -400,6 +404,7 @@ gpio7: gpio@e6055800 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774a1"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -480,11 +485,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774a1-rst"; reg = <0 0xe6160000 0 0x018c>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2785,6 +2792,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 117cb6950f91f..f2fc2a2035a1d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -108,6 +108,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -115,6 +116,7 @@ extalr_clk: extalr { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -146,6 +148,8 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -284,6 +288,7 @@ gpio7: gpio@e6055800 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774b1"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -364,11 +369,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774b1-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2661,6 +2668,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts index b78dbd807d155..57a281fc49775 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -378,6 +378,7 @@ &rwdt { &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 7655d5e3a0341..cc7f7e13c664f 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -103,6 +103,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -134,6 +135,8 @@ scif_clk: scif { soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -257,6 +260,7 @@ gpio6: gpio@e6055400 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774c0"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -337,11 +341,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774c0-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1953,6 +1959,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index f845ca604de06..e4dbda8c34d9e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -277,6 +277,7 @@ extal_clk: extal { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -284,6 +285,7 @@ extalr_clk: extalr { #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -326,6 +328,8 @@ scif_clk: scif { soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -464,6 +468,7 @@ gpio7: gpio@e6055800 { pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774e1"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -544,11 +549,13 @@ cpg: clock-controller@e6150000 { #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774e1-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2917,6 +2924,7 @@ port@1 { prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index 63fa5cf1061b3..b9746ee99ba80 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -136,6 +136,7 @@ &phyrst { &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; };