From patchwork Mon Feb 10 07:30:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13967405 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AE9A1A4F22 for ; Mon, 10 Feb 2025 07:30:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739172627; cv=none; b=iNAUVTcaUWDCRvNF4rn7sJqvU/PU+3AY3W6oMNwkMm26yok16B3hPslBVZ7AZqiZgF+C1JZOq6h9U2ILU84FKq6lSEoYuvrcX+ljEaHukUK6rR9BLTVsnw2yc1hCnO0DProHLAeZmqS6onEeSkurRBT0z9An+Oh7Q4/LZp6tLWo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739172627; c=relaxed/simple; bh=gMfLPv9UUnIIr3ePCONcx6NmkEgm/zgCqiGlQYseZ88=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AhfWMce09YUswZ+mnD6Yf69UI7d4ukOQcKsr/ZG/GAo9avz8PmfkaiDoguBfcs7fQcfbtzet3YJMKG17edeo8ILvWWkd+DJnbqTrjLx/h5BtSbhL5gPF9oGctjtAqoKprxCNCddqaZwfc6w32LMSK+T89IueF3Tm3kBlkirxZm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ZoweThxE; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ZoweThxE" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 519Fuolh026431 for ; Mon, 10 Feb 2025 07:30:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= BJmMNfxRFNQoAHOf8dBIWpMupTDw8D14/mVeDwq2G8I=; b=ZoweThxEqPL75PU5 9NY0JRMd4N5tfowzfko2aY9FnKxIjYpi0DxvI++rCuylxVPgyz+99wyOLgiCwPSK cS87l2Gk0Wuq8rt3HE9yJooWLWEsSMjGA51FtLB2BxWFs/12jKNLOjwyLeHeN5Of UQDE7pCV5S8owKqnum90hRxWcAFvM+bn4E9a5PZD53GWVO5vJAcpYNJosPivkUPe twcZb/n7S31YAFrYt/eJzn3cyZ0uiblcr9qq8ZLsITya2FGBBOLK4E+RP2Ka+2sB 0xq/o9OAYNnY0VRx0mHhBnwQYyWfJtloDRY0doBhfbzGSWnvPqM/cy6hnkAhINYt p6dkHA== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44p0esbeme-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Mon, 10 Feb 2025 07:30:23 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-2fa480350a5so3058816a91.3 for ; Sun, 09 Feb 2025 23:30:23 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739172622; x=1739777422; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BJmMNfxRFNQoAHOf8dBIWpMupTDw8D14/mVeDwq2G8I=; b=H+WCgGZlxyeX38wOBlACyi/d0Zq0Eb3D81rixoaH6rGiRIFBQDha45EviZnDxMkeJC cmbjW1s4H4ShYjxRfrLrHYaWjoqhZvqi8Zf+6OPGhfFSxD07RRdXPdL0wSG55c11nr1R QryR8AqC6+iccNjGemcbkc/xTpItPEL15/+p8T246Bn3LlZkZ7FjvuFuv4mOsnx/kjmt lJQQQinBGVJUsJ+y7R8qoa7v3jYqK927HjMYavWFKL7OeeTFzgb07pMM6GBdrA2pon5p QZUVk1va/DrNW7nXovT0lAF1qgbXYx4sfkL744mUu1iPWUMfj6M3/Q2NtOtjpBRkBbfw j6Pw== X-Gm-Message-State: AOJu0Yy6R6z39e9PIc47Noy06vLgsInhM2lCW4gmmqSXbtq5GCvG2/9/ 6tCgbsu4vlfZX2NhF/Ry56v05Wez0oOoVLefNwsohyX76xdZrxkPbR9NLbn1B20wqwd15IoVFWn qBp1XDkpuCG46dmkF6RIqIZDRjTxqgP8Yj0PB8BuzyBVk30XK4SurQgZVgz6ajo74 X-Gm-Gg: ASbGncto8cikN/eO7dDsWVdAMWn5XA4IbRH0AtII5BRwyKfeGO0dckVWS5eCm4xYlHI hVmG4NbbohK15eB7N2h4mbE2eNepWXsgH8/hlAU/ombW1auSHmgAj2eEf9/I93mLeNL1XxX5e5Y vnIlSKVbnYxwS2RIiRUy9MPPyPrFqF4YehrMqcPx9IKAv/h3//bew4fs1gF+8qXdZ2B8YZErlD7 3qH12X2PYUkJu2O6KJdwyo6sUZ7ZFL7bFxAlmk5mydWxTaNO/Rk1hgH3PqZa6YASLo/lEL1DmLp o93BFxOM3+5fGEuOOUStWPqKXNPi6ZtW2JqBCrCt X-Received: by 2002:a17:90a:f94e:b0:2f2:a664:df19 with SMTP id 98e67ed59e1d1-2fa23f436d6mr20237503a91.7.1739172622560; Sun, 09 Feb 2025 23:30:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IHhS63tBINw5qq8xbtvKGNc9R5wmcpR9u/pn2/Pg/C4zsy3eLmGArmBCeuoVXU5ZpUJxHLshA== X-Received: by 2002:a17:90a:f94e:b0:2f2:a664:df19 with SMTP id 98e67ed59e1d1-2fa23f436d6mr20237461a91.7.1739172622184; Sun, 09 Feb 2025 23:30:22 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a6fe28sm7918507a91.26.2025.02.09.23.30.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 23:30:21 -0800 (PST) From: Krishna Chaitanya Chundru Date: Mon, 10 Feb 2025 13:00:00 +0530 Subject: [PATCH v6 1/4] arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250210-preset_v6-v6-1-cbd837d0028d@oss.qualcomm.com> References: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> In-Reply-To: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739172612; l=1811; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=gMfLPv9UUnIIr3ePCONcx6NmkEgm/zgCqiGlQYseZ88=; b=5BiNxVQWdPVGWgiP8dsIzGFr3CmnOisZPiF9dT5F+KUJfHqe1FNdshFpEA0uUcg1yT/Vufs6y NmQQ9g3z8N/AoEEbBJ7yd+CaIPGFCzuhNXI+KvR4kS2Z9HpiJ6Q3GH5 X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: vEixc8gL8UZLDRVYPVY-cXP3UQFLlt2p X-Proofpoint-ORIG-GUID: vEixc8gL8UZLDRVYPVY-cXP3UQFLlt2p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_04,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 mlxscore=0 adultscore=0 spamscore=0 mlxlogscore=953 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100062 Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data rates used in lane equalization procedure. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio --- This patch depends on the this dt binding pull request which got recently merged: https://github.com/devicetree-org/dt-schema/pull/146 --- --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 4936fa5b98ff..1b815d4eed5c 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie3_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>, + /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + operating-points-v2 = <&pcie3_opp_table>; status = "disabled"; @@ -3411,6 +3416,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie6a_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + status = "disabled"; }; @@ -3538,6 +3547,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie5_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; }; @@ -3662,6 +3673,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie4_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; pcie4_port0: pcie@0 { From patchwork Mon Feb 10 07:30:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13967407 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF26D1BBBF4 for ; Mon, 10 Feb 2025 07:30:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739172631; cv=none; b=p9o6UlGG2uXoBGH908vzfaFajm9jzO3G9lhzouOD9zc10uYtU9bppLFUMCpT4TmpizSLpAdP7pBKOEqQNDp4dxvKMCo5GDESR+GhidoWCGgUxnXCJxm1bgqt6dfsoPdBixSFpxf1xFeivIk0SilGhb0Fj9kHKuGYCB4xlA8Cyzg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739172631; c=relaxed/simple; bh=Cl4JFaJxDzryIs/mN/kRhxhJFn3c+jBU5lxYfvGD3Bo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qRvRg0lFWmzs7D7jn8pBlntrHtEeQQSYp4wTxn0zQY4s8pc3DEPEMnxNvmCYQKuxb5oii5x5A7xuuYyx9Gmxc7k040LX3IQkTs2wyqNdamS4PJqSUbR9yqD5rpRnNGyfmoLVY2wY+itBZJTTDjIP6ieEcasxljcTmV29eWYLmKU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=PYGjOplb; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="PYGjOplb" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 519LsY9v010451 for ; Mon, 10 Feb 2025 07:30:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= iVMR37ilbhZdZuNg7cIw79Nb+gL8nScpY3WJEBixtSY=; b=PYGjOplbIa5psQWX eklcHhcoaaE0w3AavcD11n/kgYB81dOG/A04n6famm8st0EY319HV2FXh8I0iYgr xiWG9EfEA1SefObAHyiu+JabyyoJDvzgo4Av1As+lhyqTnfFQ4qdXtB0MprCuQWl UfFUlbBTJfzQb4kDUFLa1k0hLZemQ9KDDRDefrL4j1Ur+qdo21DZC3y3O+TQM0H5 56eQMr9hUkodZVLb+2KlaUqCKotTbnIPBkp+SwMo4f5fkYGKwBRgnxGBXGKXh2+R 8pE/OHAuaX983JRb0xvkspLHWW/qTBdEeEdANMALJnaF4kg24SvkZRURcbKWCDOH XbXZ+w== Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44p0dqbe00-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Mon, 10 Feb 2025 07:30:28 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-2ef35de8901so8733723a91.3 for ; Sun, 09 Feb 2025 23:30:28 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739172628; x=1739777428; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iVMR37ilbhZdZuNg7cIw79Nb+gL8nScpY3WJEBixtSY=; b=Eag3opthSs9cT7UG62Om7K65XFhlRsbmzy2xjhtYqayiZYKJCIrWL3JAKCgrXsBtoA A92oofL10nOI7KezDQYd3SvJksNdwMf1tENm+J8JiyffextdRmEnjX1Is1v2Pw+dx8tB 2VibW3PdeOQdXgg+5+tBfTsRRQh81Tq4YGhv1mA0FskCsWi+z3PYmuEEkSbrJPjJzdX8 9CYdvLXp0oBd0x5VtGutZN+V6lMR48s2XnsBOsuKGUeIxXTPLHOJO5Gj6rl/9Iwkwykg I8hV3vX5evVftPRzYokZ/CcZquoIk+sFZ/RlbZcrYwIxohsY7L5J++x07YEmMoXvzO5P NWUw== X-Gm-Message-State: AOJu0Yyygz5wGjQNCd5UH8MwT/lbY3S1HYMLSUadpwUXzolyf+byUSY2 +/3H8kDunSAM0FC9JLi8tHffSLwkCHiI0Jrrs549BNEPFaR6mDeRiG94xOApy1i2bLClwa2ayGb 55UST8qz0vNn8E8YTwLE6C2UVwDGe6ggXh273eIg75nB+51UT9wX/+DeyaOTA8z7J X-Gm-Gg: ASbGncuiiFN74EaixwPGVQM0N9N/s5flAYsqKZgZCaFrBZ0DZ1l/2t7SX2GdfnrzGaa pRM6iIhqZ5Bkfkkgl54ZgRo/ePDvJzwscgbDGAlrtOOvLScKCTaQ6FIhXRKZ/dPuk9euYBzKx4Q wbNGUlkwYKkIQLk61/HE2fagehc4/AoUhTOdLGZ5WntGn+2tnA0ZQpVMs9ARFYdYSLQUSYqAOFe kyMwYdIu73bP0A0OfUYAO80VVoNXMkqausyNMjPK3rAvuqLi8R+I9v1cAP+cfc/A1ICTCcqbsbi Q+m7VGizmP2usp6iYek3gssNk+wGhPeE3pynxuxM X-Received: by 2002:a17:90b:510e:b0:2ef:67c2:4030 with SMTP id 98e67ed59e1d1-2fa242e5c6amr17844348a91.27.1739172627551; Sun, 09 Feb 2025 23:30:27 -0800 (PST) X-Google-Smtp-Source: AGHT+IFSOpMpC2e4JGafXI8GZYwAZg2RfKrZm6bHipHYV3z7/cDG/+8TkM7I1j7eP7ZF+MkJdktefQ== X-Received: by 2002:a17:90b:510e:b0:2ef:67c2:4030 with SMTP id 98e67ed59e1d1-2fa242e5c6amr17844322a91.27.1739172627161; Sun, 09 Feb 2025 23:30:27 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a6fe28sm7918507a91.26.2025.02.09.23.30.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 23:30:26 -0800 (PST) From: Krishna Chaitanya Chundru Date: Mon, 10 Feb 2025 13:00:01 +0530 Subject: [PATCH v6 2/4] PCI: of: Add API to retrieve equalization presets from device tree Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250210-preset_v6-v6-2-cbd837d0028d@oss.qualcomm.com> References: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> In-Reply-To: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739172612; l=4565; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=Cl4JFaJxDzryIs/mN/kRhxhJFn3c+jBU5lxYfvGD3Bo=; b=29acobT21vTWtDtjMxRnTSFmbSUHMbJZyioTJp4qz/b6uRVPm11tg9ouLcyZnkmet8EY4ZcTf 2XtE1M/RIdsBeT/swGo4AFIdkaL81UHJdRL/eIV6dCSK0tofIkcln6R X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: uWQaX-L65-mEuptlhKuKYS2XrYCQQQFa X-Proofpoint-ORIG-GUID: uWQaX-L65-mEuptlhKuKYS2XrYCQQQFa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_04,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100062 PCIe equalization presets are predefined settings used to optimize signal integrity by compensating for signal loss and distortion in high-speed data transmission. As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to configure lane equalization presets for each lane to enhance the PCIe link reliability. Each preset value represents a different combination of pre-shoot and de-emphasis values. For each data rate, different registers are defined: for 8.0 GT/s, registers are defined in section 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has an extra receiver preset hint, requiring 16 bits per lane, while the remaining data rates use 8 bits per lane. Based on the number of lanes and the supported data rate, this function reads the device tree property and stores in the presets structure. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/of.c | 43 +++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 27 ++++++++++++++++++++++++++- 2 files changed, 69 insertions(+), 1 deletion(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 7a806f5c0d20..705d5529fa95 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -851,3 +851,46 @@ u32 of_pci_get_slot_power_limit(struct device_node *node, return slot_power_limit_mw; } EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); + +/** + * of_pci_get_equalization_presets - Parses the "eq-presets-ngts" property. + * + * @dev: Device containing the properties. + * @presets: Pointer to store the parsed data. + * @num_lanes: Maximum number of lanes supported. + * + * If the property is present read and store the data in the preset structure + * assign default value 0xff to indicate property is not present. + * + * Return: 0 if the property is not available or successfully parsed; errno otherwise. + */ +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + char name[20]; + int ret; + + presets->eq_presets_8gts[0] = PCI_EQ_RESV; + ret = of_property_read_u16_array(dev->of_node, "eq-presets-8gts", + presets->eq_presets_8gts, num_lanes); + if (ret && ret != -EINVAL) { + dev_err(dev, "Error reading eq-presets-8gts %d\n", ret); + return ret; + } + + for (int i = 0; i < EQ_PRESET_TYPE_MAX; i++) { + presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV; + snprintf(name, sizeof(name), "eq-presets-%dgts", 8 << (i + 1)); + ret = of_property_read_u8_array(dev->of_node, name, + presets->eq_presets_Ngts[i], + num_lanes); + if (ret && ret != -EINVAL) { + dev_err(dev, "Error reading %s %d\n", name, ret); + return ret; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_get_equalization_presets); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 01e51db8d285..e87c2ffd1e85 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -9,6 +9,8 @@ struct pcie_tlp_log; /* Number of possible devfns: 0.0 to 1f.7 inclusive */ #define MAX_NR_DEVFNS 256 +#define MAX_NR_LANES 16 + #define PCI_FIND_CAP_TTL 48 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ @@ -808,6 +810,20 @@ static inline u64 pci_rebar_size_to_bytes(int size) struct device_node; +#define PCI_EQ_RESV 0xff + +enum equalization_preset_type { + EQ_PRESET_TYPE_16GTS, + EQ_PRESET_TYPE_32GTS, + EQ_PRESET_TYPE_64GTS, + EQ_PRESET_TYPE_MAX +}; + +struct pci_eq_presets { + u16 eq_presets_8gts[MAX_NR_LANES]; + u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX][MAX_NR_LANES]; +}; + #ifdef CONFIG_OF int of_get_pci_domain_nr(struct device_node *node); int of_pci_get_max_link_speed(struct device_node *node); @@ -822,7 +838,9 @@ void pci_release_bus_of_node(struct pci_bus *bus); int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); bool of_pci_supply_present(struct device_node *np); - +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes); #else static inline int of_get_pci_domain_nr(struct device_node *node) @@ -867,6 +885,13 @@ static inline bool of_pci_supply_present(struct device_node *np) { return false; } + +static inline int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + return 0; +} #endif /* CONFIG_OF */ struct of_changeset; From patchwork Mon Feb 10 07:30:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13967408 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E294B1B425A for ; Mon, 10 Feb 2025 07:30:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739172638; cv=none; b=QLDAGnE8mpJogo70qa9Bxt5cOFdvtQgukXMloMpuRBVtOVi9HzPq0HnsrDQuWwhmgYRmCnZ/ykFf4CekocAsRSTS8adgoJy2Qj887zo9oz20Pglfu4xEBprqbgtpuK5JRyormCIP3PLNbYeoNcVIYxFR3vsal3ST1EtDQnscIRs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739172638; c=relaxed/simple; bh=aQRQ6+sri+2FjvUvhS/l1+zsbikTMl/4NyNhdlh4S5Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YGjUuoyYTw1KA8lUOmALOhuC869eJwdk1OtO8a/Ruk8A2iJoEwGOI+j9frrlzrHPX8hvFF5J7/pGIcHQh4PH0HuvXhrkqh+bO21KO3FuRrP6oCs3jUNdtFndmxFJrDeYuImGQw3MB3aWb6h26JZTtygKBIcP8XStkx3vAsetuQU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=QLnkEjvt; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="QLnkEjvt" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 519KTGUj032157 for ; Mon, 10 Feb 2025 07:30:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wRrOHyip7ZbNQ8lQZNrcx41SX8ZDA1DYAx7l+sPi8FQ=; b=QLnkEjvtShF4yQUQ 59LbxklTXLrVeURi78b4YdSZtR0aRY+HWGSDr8ous2OcFH2KA4sBGtghCJF+obVQ fvwerthjtbQ7QG4Q+h+UiW1JQukHY9geConVce1YcPGreop1rMyx8v/4HnoBaK4J 5r26vMorQDX5clIIlUcIQw31Q4HNz1PqicK82zid5CUCm3ZnfV4zW8SqY4ZHW3ST tcLRke4ZqPWvdgQadR/+DwEaI5UqayB3ndNbAEahLaLC1S+IT3bVrrOBr8QOsmXR RCO3S1sq0fFtXSMrgHsgHN9NML8u1wsB6UIXsU7twxrPzRMhcLbaR12kT/mdu17t CWUfzA== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44p0esben6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Mon, 10 Feb 2025 07:30:35 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-2f46b7851fcso12694004a91.1 for ; Sun, 09 Feb 2025 23:30:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739172632; x=1739777432; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wRrOHyip7ZbNQ8lQZNrcx41SX8ZDA1DYAx7l+sPi8FQ=; b=xIr7/AHiJVslCZO5zHpLHkrv2GS3yLBAXTCkdW9p7LQ/QE1gSnloFl/NJ+V3PxBWlN BHIWJqA8TQ5HzrQR+H/MnXEfYhHK6pUlayABVfuHo8Vx5/fLoH671wfq2LRVVDZeDgsE aDsk6LcSA9p3jmINNAU4WsMBIMpEhILxgPuoFjJ0O9YNDRl7Nz+rcnHWUQ7AWV3mLk/b YlulFCWt/xO0LrrEeY7iA9/4tHEvH/4lb+/vXGSixOokto4QrfZeAVd+RP4yZ26KVnCA IckMAJS/Vps2TUbnF2IPJiD1xcQm0dB95ijinBvNc6hrnirnOwVfrgHZcdCxhOrad8Ro kHbw== X-Gm-Message-State: AOJu0YwaUJDnLjUb+eR25IQCb2uRb6OuYu3J50z2RAkHnKBvP1Hrp72a eOcSFsh7lbxfe5rgJzwYzSSM3LVaFBlY/lX0IWwx1WtP2aL3vx4bGSt1oWMIYfEp4h/Ph0qWa8I ATU/ccPXoibFAfQ1EFSV2UXxFTqgvkgGk+br89ce6spK/HKWJkoT+wZOU8qdbwiKY X-Gm-Gg: ASbGncsRY2Rx7D73keHqpnQDbVfZotZgv7+pCszReY5rHF1LAy2qBGx+k43xKhEpoc3 I+kq5Kj4fKVRlHXhZrXKiPcabjF+ejkE3pehH0icb1cTA7/Cfy3Bc3EwaIAOPb7VbhqQYnmBu+x BLR1ibK2jdhJBPykyr4R0H4c3UgXXT3I4NOq9J525M+KngvlvL10wSsS6XnIYQJS8msV5XE4WWw q5+t4sxSzsDNO+rmp/VJMSlNJooDNWDFenupF5O6jUQWnEl479O9bCPaWzFkMQ+WaGtN44S8nKZ IEtrBkwXku/ZGyNZOIlR1rDiZPwuc4Qn0tmMK7mb X-Received: by 2002:a17:90b:2ec5:b0:2fa:2252:f438 with SMTP id 98e67ed59e1d1-2fa2450cf33mr18714844a91.30.1739172632478; Sun, 09 Feb 2025 23:30:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IGC4mFsdhr14elczMdgif0tIJ9T32NQVRA86UAwGYhm7aRYQ7hdqOUHt+ZP3HEWgDqCFnMgDg== X-Received: by 2002:a17:90b:2ec5:b0:2fa:2252:f438 with SMTP id 98e67ed59e1d1-2fa2450cf33mr18714812a91.30.1739172632097; Sun, 09 Feb 2025 23:30:32 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a6fe28sm7918507a91.26.2025.02.09.23.30.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 23:30:31 -0800 (PST) From: Krishna Chaitanya Chundru Date: Mon, 10 Feb 2025 13:00:02 +0530 Subject: [PATCH v6 3/4] PCI: dwc: Improve handling of PCIe lane configuration Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250210-preset_v6-v6-3-cbd837d0028d@oss.qualcomm.com> References: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> In-Reply-To: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739172612; l=3073; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=aQRQ6+sri+2FjvUvhS/l1+zsbikTMl/4NyNhdlh4S5Y=; b=VCnpoykv6zQRuJNMbEm6VdCa9AY6fq++JhPDYFwoMtavGyTSlIFAEqHNlne4oCwsJ2w9Dw0a0 /v3Lv2XJzR1DAxjBZMQrUAUVCbu6ncBtGcIvRRjc/DYwqXY2GU1QVwy X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: _vCPTBQKxujHYGgl-QcoVbraOhXoUj3T X-Proofpoint-ORIG-GUID: _vCPTBQKxujHYGgl-QcoVbraOhXoUj3T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_04,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 mlxscore=0 adultscore=0 spamscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100062 Currently even if the number of lanes hardware supports is equal to the number lanes provided in the devicetree, the driver is trying to configure again the maximum number of lanes which is not needed. Update number of lanes only when it is not equal to hardware capability. And also if the num-lanes property is not present in the devicetree update the num_lanes with the maximum hardware supports. Introduce dw_pcie_link_get_max_link_width() to get the maximum lane width the hardware supports. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.c | 11 ++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index ffaded8f2df7..dd56cc02f4ef 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -504,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_iatu_detect(pci); + if (pci->num_lanes < 1) + pci->num_lanes = dw_pcie_link_get_max_link_width(pci); + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 145e7f579072..967c62cf3db0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -737,12 +737,21 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) } +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) +{ + u8 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + + return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); +} + static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) { + int max_lanes = dw_pcie_link_get_max_link_width(pci); u32 lnkcap, lwsc, plc; u8 cap; - if (!num_lanes) + if (!num_lanes || max_lanes == num_lanes) return; /* Set the number of lanes */ diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 501d9ddfea16..61d1fb6b437b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -488,6 +488,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); void dw_pcie_upconfig_setup(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci); int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, const struct dw_pcie_ob_atu_cfg *atu); int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, From patchwork Mon Feb 10 07:30:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13967409 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 544F01BE23E for ; Mon, 10 Feb 2025 07:30:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739172641; cv=none; b=lwONce5B7aljKlw4bSHx+Bb8lVFdVlyPDkTVm5I6bc8N5I+PZIilomMpBE4zskQMRLAuQ7atlQtDQe/PL0a5naRl2U/avugyhxxTcJzp8+Hle4uAaLctZrwUqY+tHQjJsjIOs/rjpk5psy4rGMjqW4Srn5jOSzxDZM4iO+zV/OI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739172641; c=relaxed/simple; bh=CjcIoMuWyC0rjQWAhfahtHdPtxVNXgXdr00cki07ZIg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fLyJ8CQSOuYSQtBRxzDI2HZ7+M73yo1HehK2mV9LSdUit+Coj0YwR5ebNfbAj4Qh0BfoymbaoGCyzMGlXdCxMkN76ONkbhu8Pj+aJgHKPMwYH3P/BV6Tjq9U3DSuwop0zir+WBQV3Y6kPwtZPDraVAHphzAv7uNDTfeEP27mCKk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=eyrJ3WEa; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="eyrJ3WEa" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 519L20u8020492 for ; Mon, 10 Feb 2025 07:30:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= zHhumTqGiC9SFx6j+TjMU9C+4s+ppWJX8DmHw2DIZew=; b=eyrJ3WEaYSjb0Qsy Az03gffoqBvKBtrPmMSam9OjivgMr/5zT5uV/YW91N/P//I7emzsj2554eZJLwA5 X+JAgnYh2HQSn+n/8yYwCH9csyGQv8luvRCqLeIewoKBvvKkYE+jiG2TXKM0O6al tnu3vli7a6RciLvB8OBNtY+v7RzwUy2ndVUKe+dMga1bJphCY7BGhkZEgHlzV6qA h45WFmCsPCwrNS6TrVmFxIvIy5MtCGqjneL5nYo2s9XeBlf6hZOQovZW+eVyN/XC fwKDEcilYvFqs7u5RcuucLg9OfWWabEsMjyg1WRBWELcbFP6uLhfFzzGWYmr6Myq DKRKyw== Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44p0guudd9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Mon, 10 Feb 2025 07:30:39 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-2fa228b4143so5962374a91.0 for ; Sun, 09 Feb 2025 23:30:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739172638; x=1739777438; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zHhumTqGiC9SFx6j+TjMU9C+4s+ppWJX8DmHw2DIZew=; b=vvl8uhA/byVCoHVd8PQVkoK1XelFLx1iTQJo58iec1vp/+LwcifvFNsDPxlqY0NmdE vu1Et3Euxu+rSBnq/Gx+Zi0+jlUTSJIJD3QmLolMYbYj40sBmWVEHl6/fofSIWHHV6tN guUWUqARQ8vhTtcs3bI6MXECxzVQQqhW6TQCcpiN+SiZo7WpwDAMjFz0yr6i51YDdDke Fw0XaIC25nep8+QB7tp+i3Y1cyDtyaN0sB1e0aVVU49IKs7vMYUozDZIvMu9LDFfc2Wi xSCexYKG+7YgO1u1EyPwslGGPOWS/NkpL7qAn1Ei7i8bC0WtbhmSTb/Jm2ZCgNHIrHgY 7O4A== X-Gm-Message-State: AOJu0YxaaagCI1ECrlESk77Muy7K1T4jnrf5Lu9wwbexe4u+1SHBFnae y3TL80DWFRRnnDcFc0DEs24wnMXdglbUEPKUD2cX+EbKt1PefYvm8LPbSn/f12VKbmH90zFHjlO UBzdCOuyuBgAUltXGplT5vFAFs6X/f6fHgtFlTg1uC418PWh6eYQVu6yeh3mc+FkN X-Gm-Gg: ASbGncuGtcO+RtRCI1TNaGbFy2whYNaf7R6HdMV2lRdeAdE1goWDYaCXbAHKFrSFS8i Ds5E1XcAia4GsFztoPi7y7UD+VeZnNo3Uj3YSZ6Q1pkbTNFGg3Ht6tkQtq9Y8P59MD0TRl0OShS IlgA+eWfB+ja6dlJ33aIcGSeFJPN/Qqf0e10cgmz6jdHj0uaGoRcB0XFxSt3fACp/CCdzbDCi5Y 1rz1bnDEQ9KPue+F/7MvkBIPQja4HI6Mw6xpfMx5OdflHmjx2Y/zdPl3IENh8fne0L6xN+qGF4R XSDF7OwhMWviLAifkrKDANv2icwSPrunv/Iuaseu X-Received: by 2002:a17:90a:d44d:b0:2ee:8253:9a9f with SMTP id 98e67ed59e1d1-2f9ffb38478mr27370637a91.11.1739172637480; Sun, 09 Feb 2025 23:30:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IGBoMPJCr9G0sVDjZr31KH5I4trCwBw8lTPD73GBYRG0dc62HbkoqDzG06kQVfThE+IO0v0Zg== X-Received: by 2002:a17:90a:d44d:b0:2ee:8253:9a9f with SMTP id 98e67ed59e1d1-2f9ffb38478mr27370599a91.11.1739172637066; Sun, 09 Feb 2025 23:30:37 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a6fe28sm7918507a91.26.2025.02.09.23.30.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 23:30:36 -0800 (PST) From: Krishna Chaitanya Chundru Date: Mon, 10 Feb 2025 13:00:03 +0530 Subject: [PATCH v6 4/4] PCI: dwc: Add support for configuring lane equalization presets Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250210-preset_v6-v6-4-cbd837d0028d@oss.qualcomm.com> References: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> In-Reply-To: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739172612; l=4696; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=CjcIoMuWyC0rjQWAhfahtHdPtxVNXgXdr00cki07ZIg=; b=KVgBviQ7UiRSel1hjYer6GXaCC7nOQtup6xnnSKAfaMXd9KBuTWru2Ckp73BEOBzb3SfFHDgX ypw1tnP+2usDf3EeTh7g5GH5VSe5gP77S4tvvyToIsNTX4xbA0E717l X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: BPYfGq-CydqozG05deps9jceKr8d5Lfr X-Proofpoint-GUID: BPYfGq-CydqozG05deps9jceKr8d5Lfr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_04,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 mlxscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100061 PCIe equalization presets are predefined settings used to optimize signal integrity by compensating for signal loss and distortion in high-speed data transmission. Based upon the number of lanes and the data rate supported, write the preset data read from the device tree in to the lane equalization control registers. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 53 +++++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 3 ++ include/uapi/linux/pci_regs.h | 3 ++ 3 files changed, 59 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index dd56cc02f4ef..7d5f16f77e2f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -507,6 +507,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pci->num_lanes < 1) pci->num_lanes = dw_pcie_link_get_max_link_width(pci); + ret = of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes); + if (ret) + goto err_free_msi; + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends @@ -808,6 +812,54 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) return 0; } +static void dw_pcie_program_presets(struct dw_pcie_rp *pp, enum pci_bus_speed speed) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + u8 lane_eq_offset, lane_reg_size, cap_id; + u8 *presets; + u32 cap; + int i; + + if (speed == PCIE_SPEED_8_0GT) { + presets = (u8 *)pp->presets.eq_presets_8gts; + lane_eq_offset = PCI_SECPCI_LE_CTRL; + cap_id = PCI_EXT_CAP_ID_SECPCI; + /* For data rate of 8 GT/S each lane equalization control is 16bits wide*/ + lane_reg_size = 0x2; + } else if (speed == PCIE_SPEED_16_0GT) { + presets = pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS]; + lane_eq_offset = PCI_PL_16GT_LE_CTRL; + cap_id = PCI_EXT_CAP_ID_PL_16GT; + lane_reg_size = 0x1; + } + + if (presets[0] == PCI_EQ_RESV) + return; + + cap = dw_pcie_find_ext_capability(pci, cap_id); + if (!cap) + return; + + /* + * Write preset values to the registers byte-by-byte for the given + * number of lanes and register size. + */ + for (i = 0; i < pci->num_lanes * lane_reg_size; i++) + dw_pcie_writeb_dbi(pci, cap + lane_eq_offset + i, presets[i]); +} + +static void dw_pcie_config_presets(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + enum pci_bus_speed speed = pcie_link_speed[pci->max_link_speed]; + + if (speed >= PCIE_SPEED_8_0GT) + dw_pcie_program_presets(pp, PCIE_SPEED_8_0GT); + + if (speed >= PCIE_SPEED_16_0GT) + dw_pcie_program_presets(pp, PCIE_SPEED_16_0GT); +} + int dw_pcie_setup_rc(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -861,6 +913,7 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) PCI_COMMAND_MASTER | PCI_COMMAND_SERR; dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + dw_pcie_config_presets(pp); /* * If the platform provides its own child bus config accesses, it means * the platform uses its own address translation component rather than diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 61d1fb6b437b..30ae8d3f4282 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -25,6 +25,8 @@ #include #include +#include "../../pci.h" + /* DWC PCIe IP-core versions (native support since v4.70a) */ #define DW_PCIE_VER_365A 0x3336352a #define DW_PCIE_VER_460A 0x3436302a @@ -381,6 +383,7 @@ struct dw_pcie_rp { int msg_atu_index; struct resource *msg_res; bool use_linkup_irq; + struct pci_eq_presets presets; }; struct dw_pcie_ep_ops { diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 3445c4970e4d..2cd20170adb4 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1140,6 +1140,9 @@ #define PCI_DLF_CAP 0x04 /* Capabilities Register */ #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ +/* Secondary PCIe Capability 8.0 GT/s */ +#define PCI_SECPCI_LE_CTRL 0x0c /* Lane Equalization Control Register */ + /* Physical Layer 16.0 GT/s */ #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F