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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF000023D4.mail.protection.outlook.com (10.167.244.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8466.0 via Frontend Transport; Mon, 10 Feb 2025 11:36:34 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 10 Feb 2025 05:36:31 -0600 Received: from xsjssw-mmedia4.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Mon, 10 Feb 2025 05:36:30 -0600 From: Rohit Visavalia To: , , , CC: , , , , , , "Rohit Visavalia" Subject: [PATCH v3 1/2] clk: xilinx: vcu: unregister pll_post only if registered correctly Date: Mon, 10 Feb 2025 03:36:13 -0800 Message-ID: <20250210113614.4149050-2-rohit.visavalia@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250210113614.4149050-1-rohit.visavalia@amd.com> References: <20250210113614.4149050-1-rohit.visavalia@amd.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: rohit.visavalia@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D4:EE_|PH7PR12MB6811:EE_ X-MS-Office365-Filtering-Correlation-Id: 139f6cfe-2bd9-4286-86a0-08dd49c72c03 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: zDZusRy2CQN2ZlIM4IrK1zs+T0VJDFl9RqEdDoSEOr1AOPkMBqQoOKOzyiI4N1MwpQR55Zg9MLDgW8lej5bbCnryXPI4hYRczwvgWoPg7tdS4sxZ0AqY1ch8q1GZ6ik/3KKX5c3Zx7bZRGAXjoEGRaM4Tb2L3PiVSTZKUqUWiifBNaM3Nvs+mQiUvejM2Uqx7EegAO3F4cT4ZvQLaLrv7QFSKyLAguWwUuxWaTofb8YFFPlbODeBiQwqJIz6OaFOEEHETMTulmsp140maNlI7tylrmYzQEeDVzd9BHqqfTZ7PfNIkRAh47NWsCBBF2cOuShQ674ihVVC6+f0OjjANeR0d89hOwUAuWyzcE+hKmrW21XyuJ5mXJ7EIpL6Jj3Axbb62TbnzRkxAt4JumapXQK/NM4zCHiX/VicFl/LfcBlDKdDltLyYNyD2Qb3fDYwGgELDm0Qu6IXB/bTfPOu2zxX0cbixXa07OIvFOlM9ngWGS+nZiFo6sqi92QAqUj/IQqr6kBEWi5s86XQKwv5bOR6HsGhR2f5Xje0ORm7rDLwwlKlIcxst16KvQJAIzfBnDPauZmuDwD89/oiAMdZIZZRzi2+l/jIuC8QBbpsxtzAZ1Cdt2Q4dZh/+UDRh/5qTaDTpMv/gsB4+yRJmZD3cqWy64dCTgdWzcBIn+mBlcj5xocPdnpK/BB73KF0dyRG2HzmgUq+IE7z7Ip4qw8XsQNyoIQCtlJ2YFQXKEdnhyzE+U8zSUusMBiJYruJkFhJUnBKJUPOUrEXchUUPsNz6tT7ahpyNqRGe9KT4uagCOQZCo3WcK3C/RThrxQSRtsMg4lIrn774pzu5k7P1Oi12dGBNBzTkYivBZOuKREn39UioaqQIX1Rpm1weC/nA9DuTnUZK9jVZcqCJ1apcl2eOGXxZmz+vVQA885r60bZjtN6kM1UB5sHwOPnQu+srbvFGQkmYAgg9JGnccFfwo6Re5mADZ0NP7tw2t7JGBEjHJ286GuKsYi0dpGhhP0UVj6jU6KjtxYUOnw988tjlYR/vYw4uv1fsmHB8RGGag98ca/1rOlIwFTyYu6TrQ7U2bjk4DirmbHDsrrQzMYT3rCEkDY3cG3QMzbZX6vRDfhDQccqTjEBWzhZGHaGRTsoNPCg2q6dIUeIkPhM3CjBGQUiOzgmxTahOEUVu8BY03JmzXsIN4yJio4sOBu+pUJWDh5TNGBNNwtKBoH3HylnUyzcvengY86EhAMlFONddg8svzmKbcxo5amYvy7DJqIADT5p/M70ODUnKoyag88LdMbq5E6smbqvjCh2TzHWDhrQRtg0vG0sSDwLqO1TwJOXIaXouoNV+EO2kX+VBzFr5GAVwNCMJx3Y3wSn6a7OUHoai/UJWbRagsGtZw83piAy2pHw8mvH4FfTdXQqJ+ZBYCfMYoAH6S4L0KMItd1GxdgWvYFEcTwKItj/cvLrbeNoL4hB2sF7hMxEw3Uj66NybaYgsVr2FbN8n7Wgg+HhEhhWcd8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Feb 2025 11:36:34.0664 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 139f6cfe-2bd9-4286-86a0-08dd49c72c03 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D4.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6811 If registration of pll_post is failed, it will be set to NULL or ERR, unregistering same will fail with following call trace: Unable to handle kernel NULL pointer dereference at virtual address 008 pc : clk_hw_unregister+0xc/0x20 lr : clk_hw_unregister_fixed_factor+0x18/0x30 sp : ffff800011923850 ... Call trace: clk_hw_unregister+0xc/0x20 clk_hw_unregister_fixed_factor+0x18/0x30 xvcu_unregister_clock_provider+0xcc/0xf4 [xlnx_vcu] xvcu_probe+0x2bc/0x53c [xlnx_vcu] Fixes: 4472e1849db7 ("soc: xilinx: vcu: make pll post divider explicit") Signed-off-by: Rohit Visavalia --- drivers/clk/xilinx/xlnx_vcu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/xilinx/xlnx_vcu.c b/drivers/clk/xilinx/xlnx_vcu.c index 81501b48412e..88b3fd8250c2 100644 --- a/drivers/clk/xilinx/xlnx_vcu.c +++ b/drivers/clk/xilinx/xlnx_vcu.c @@ -587,8 +587,8 @@ static void xvcu_unregister_clock_provider(struct xvcu_device *xvcu) xvcu_clk_hw_unregister_leaf(hws[CLK_XVCU_ENC_MCU]); if (!IS_ERR_OR_NULL(hws[CLK_XVCU_ENC_CORE])) xvcu_clk_hw_unregister_leaf(hws[CLK_XVCU_ENC_CORE]); - - clk_hw_unregister_fixed_factor(xvcu->pll_post); + if (!IS_ERR_OR_NULL(xvcu->pll_post)) + clk_hw_unregister_fixed_factor(xvcu->pll_post); } /** From patchwork Mon Feb 10 11:36:14 2025 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Feb 2025 11:36:35.5351 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b6c366a-7d34-4e37-a438-08dd49c72ce3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D4.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7120 Updated vcu init/reset sequence as per design changes. If VCU reset GPIO is available then do assert and de-assert it before enabling/disabling gasket isolation. This GPIO is added because gasket isolation will be removed during startup that requires access to SLCR register space. Post startup, the ownership of the register interface lies with logiCORE IP. Signed-off-by: Rohit Visavalia --- drivers/clk/xilinx/xlnx_vcu.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/clk/xilinx/xlnx_vcu.c b/drivers/clk/xilinx/xlnx_vcu.c index 88b3fd8250c2..1ded67bee06c 100644 --- a/drivers/clk/xilinx/xlnx_vcu.c +++ b/drivers/clk/xilinx/xlnx_vcu.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -51,6 +52,7 @@ * @dev: Platform device * @pll_ref: pll ref clock source * @aclk: axi clock source + * @reset_gpio: vcu reset gpio * @logicore_reg_ba: logicore reg base address * @vcu_slcr_ba: vcu_slcr Register base address * @pll: handle for the VCU PLL @@ -61,6 +63,7 @@ struct xvcu_device { struct device *dev; struct clk *pll_ref; struct clk *aclk; + struct gpio_desc *reset_gpio; struct regmap *logicore_reg_ba; void __iomem *vcu_slcr_ba; struct clk_hw *pll; @@ -676,6 +679,24 @@ static int xvcu_probe(struct platform_device *pdev) * Bit 0 : Gasket isolation * Bit 1 : put VCU out of reset */ + xvcu->reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(xvcu->reset_gpio)) { + ret = PTR_ERR(xvcu->reset_gpio); + dev_err_probe(&pdev->dev, ret, "failed to get reset gpio for vcu.\n"); + goto error_get_gpio; + } + + if (xvcu->reset_gpio) { + gpiod_set_value(xvcu->reset_gpio, 0); + /* min 2 clock cycle of vcu pll_ref, slowest freq is 33.33KHz */ + usleep_range(60, 120); + gpiod_set_value(xvcu->reset_gpio, 1); + usleep_range(60, 120); + } else { + dev_dbg(&pdev->dev, "No reset gpio info found in dts for VCU. This may result in incorrect functionality if VCU isolation is removed after initialization in designs where the VCU reset is driven by gpio.\n"); + } + regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, VCU_GASKET_VALUE); ret = xvcu_register_clock_provider(xvcu); @@ -690,6 +711,7 @@ static int xvcu_probe(struct platform_device *pdev) error_clk_provider: xvcu_unregister_clock_provider(xvcu); +error_get_gpio: clk_disable_unprepare(xvcu->aclk); return ret; } @@ -711,6 +733,13 @@ static void xvcu_remove(struct platform_device *pdev) xvcu_unregister_clock_provider(xvcu); /* Add the Gasket isolation and put the VCU in reset. */ + if (xvcu->reset_gpio) { + gpiod_set_value(xvcu->reset_gpio, 0); + /* min 2 clock cycle of vcu pll_ref, slowest freq is 33.33KHz */ + usleep_range(60, 120); + gpiod_set_value(xvcu->reset_gpio, 1); + usleep_range(60, 120); + } regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0); clk_disable_unprepare(xvcu->aclk);