From patchwork Mon Feb 10 16:44:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13968229 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E9F52580D4; Mon, 10 Feb 2025 16:45:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739205927; cv=none; b=F6SqSJvd2kRHkUqDZWfcrkgWbmkZvt5QPYxj1t6AnPLfLW864I2mFZA+DSqlw5Ql0xCTcmmY7ac+H7OiXaeOvYo9mNfq6MPe5pip16tGjF99I0OcXMKX+4+UV8Fuu9cCDKIkYHqcdPKineK2jMnlYj/GX5A4KXwWRQuCgOHUdLc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739205927; c=relaxed/simple; bh=ls5z6yKtjpDimhSK7my0ZfFh65dMvJQB5T49MSYmQLY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WWpte8MTW/IO2nba5alSa+V3WtfbKQJqSCGM9MndDfm/WBI8GI6T4b2+NB7iZz1oSGZJLw8xBrmpjVGUdbVGwjJGy2TTScfLMkXPAc7ed9G4OjtCo9RpUTTs90xJXJujUg6UGBfW8wyKhfcbQcuOaHYsGo0JS9l3bXUgYkARXow= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com; spf=pass smtp.mailfrom=thorsis.com; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b=M8zTLMLo; arc=none smtp.client-ip=217.92.40.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thorsis.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b="M8zTLMLo" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 85B061480320; Mon, 10 Feb 2025 17:45:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1739205916; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=p59kS6BgnDtLm2RBmPDFSxO8EjcssSjUIbakAXnj8oY=; b=M8zTLMLoc4D5DvNZU+oxhDSzqwcZ+Rt1xIPKEzcXnqo+rkk0uPE079v4tFKly210tV3/iD H33MAdHt0yc5PO9pF0N6qDHZ82Fy1EoUtc87ymhVhb4dtGmvG649uGqQW1G2e8bcOnZGhc a9zvbvC5/9vDCF97BkAW0vWqpKKFdd6OxcoCQkGL/Zh8nhvr47YG33SwgSJJCaK3ElsvMU qRljw57U1Av6tyHo2+/lHE0nFu6xUsQl8DKJ4eD8QT+gkXpd+zlAha/sHrBvDOUE1HzhkY T49pgK+ics1ztVZfA5AiMIosXyBk0NIkI5nv/DOE+JPuk5ce67lSpdd+ZzOyzw== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 01/16] dt-bindings: clock: at91: Split up per SoC partially Date: Mon, 10 Feb 2025 17:44:51 +0100 Message-Id: <20250210164506.495747-2-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210164506.495747-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Before adding even more new indexes creating more holes in the clk at91 drivers pmc_data->chws arrays, split this up. This is a partial split up only for SoCs affected by upcoming changes and by that PMC_MAIN + x hack, others could follow by the same scheme. Binding splitup was proposed for several reasons: 1) keep the driver code simple, readable, and efficient 2) avoid accidental array index duplication 3) avoid memory waste by creating more and more unused array members. Old values are kept to not break dts, and to maintain dt ABI. Link: https://lore.kernel.org/linux-devicetree/20250207-jailbird-circus-bcc04ee90e05@thorsis.com/T/#u Signed-off-by: Alexander Dahl --- Notes: v2: - new patch, not present in v1 .../dt-bindings/clock/microchip,sam9x60-pmc.h | 19 +++++++++++ .../dt-bindings/clock/microchip,sam9x7-pmc.h | 25 +++++++++++++++ .../clock/microchip,sama7d65-pmc.h | 32 +++++++++++++++++++ .../dt-bindings/clock/microchip,sama7g5-pmc.h | 24 ++++++++++++++ 4 files changed, 100 insertions(+) create mode 100644 include/dt-bindings/clock/microchip,sam9x60-pmc.h create mode 100644 include/dt-bindings/clock/microchip,sam9x7-pmc.h create mode 100644 include/dt-bindings/clock/microchip,sama7d65-pmc.h create mode 100644 include/dt-bindings/clock/microchip,sama7g5-pmc.h diff --git a/include/dt-bindings/clock/microchip,sam9x60-pmc.h b/include/dt-bindings/clock/microchip,sam9x60-pmc.h new file mode 100644 index 0000000000000..e01e867e8c4da --- /dev/null +++ b/include/dt-bindings/clock/microchip,sam9x60-pmc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * The constants defined in this header are being used in dts and in + * at91 sam9x60 clock driver. + */ + +#ifndef _DT_BINDINGS_CLOCK_MICROCHIP_SAM9X60_PMC_H +#define _DT_BINDINGS_CLOCK_MICROCHIP_SAM9X60_PMC_H + +#include + +/* old from before bindings splitup */ +#define SAM9X60_PMC_MCK PMC_MCK /* 1 */ +#define SAM9X60_PMC_UTMI PMC_UTMI /* 2 */ +#define SAM9X60_PMC_MAIN PMC_MAIN /* 3 */ + +#define SAM9X60_PMC_PLLACK PMC_PLLACK /* 7 */ + +#endif diff --git a/include/dt-bindings/clock/microchip,sam9x7-pmc.h b/include/dt-bindings/clock/microchip,sam9x7-pmc.h new file mode 100644 index 0000000000000..2df1ff97a5b18 --- /dev/null +++ b/include/dt-bindings/clock/microchip,sam9x7-pmc.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * The constants defined in this header are being used in dts and in + * at91 sam9x7 clock driver. + */ + +#ifndef _DT_BINDINGS_CLOCK_MICROCHIP_SAM9X7_PMC_H +#define _DT_BINDINGS_CLOCK_MICROCHIP_SAM9X7_PMC_H + +#include + +/* old from before bindings splitup */ +#define SAM9X7_PMC_MCK PMC_MCK /* 1 */ +#define SAM9X7_PMC_UTMI PMC_UTMI /* 2 */ +#define SAM9X7_PMC_MAIN PMC_MAIN /* 3 */ + +#define SAM9X7_PMC_PLLACK PMC_PLLACK /* 7 */ + +#define SAM9X7_PMC_AUDIOPMCPLL PMC_AUDIOPMCPLL /* 9 */ +#define SAM9X7_PMC_AUDIOIOPLL PMC_AUDIOIOPLL /* 10 */ + +#define SAM9X7_PMC_PLLADIV2 PMC_PLLADIV2 /* 14 */ +#define SAM9X7_PMC_LVDSPLL PMC_LVDSPLL /* 15 */ + +#endif diff --git a/include/dt-bindings/clock/microchip,sama7d65-pmc.h b/include/dt-bindings/clock/microchip,sama7d65-pmc.h new file mode 100644 index 0000000000000..f5be643be9b36 --- /dev/null +++ b/include/dt-bindings/clock/microchip,sama7d65-pmc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * The constants defined in this header are being used in dts and in + * at91 sama7d65 clock driver. + */ + +#ifndef _DT_BINDINGS_CLOCK_MICROCHIP_SAMA7D65_PMC_H +#define _DT_BINDINGS_CLOCK_MICROCHIP_SAMA7D65_PMC_H + +#include + +/* old from before bindings splitup */ +#define SAMA7D65_PMC_MCK0 PMC_MCK /* 1 */ +#define SAMA7D65_PMC_UTMI PMC_UTMI /* 2 */ +#define SAMA7D65_PMC_MAIN PMC_MAIN /* 3 */ +#define SAMA7D65_PMC_CPUPLL PMC_CPUPLL /* 4 */ +#define SAMA7D65_PMC_SYSPLL PMC_SYSPLL /* 5 */ + +#define SAMA7D65_PMC_BAUDPLL PMC_BAUDPLL /* 8 */ +#define SAMA7D65_PMC_AUDIOPMCPLL PMC_AUDIOPMCPLL /* 9 */ +#define SAMA7D65_PMC_AUDIOIOPLL PMC_AUDIOIOPLL /* 10 */ +#define SAMA7D65_PMC_ETHPLL PMC_ETHPLL /* 11 */ + +#define SAMA7D65_PMC_MCK1 PMC_MCK1 /* 13 */ + +#define SAMA7D65_PMC_LVDSPLL PMC_LVDSPLL /* 15 */ +#define SAMA7D65_PMC_MCK3 PMC_MCK3 /* 16 */ +#define SAMA7D65_PMC_MCK5 PMC_MCK5 /* 17 */ + +#define SAMA7D65_PMC_INDEX_MAX 25 + +#endif diff --git a/include/dt-bindings/clock/microchip,sama7g5-pmc.h b/include/dt-bindings/clock/microchip,sama7g5-pmc.h new file mode 100644 index 0000000000000..ad69ccdf9dc78 --- /dev/null +++ b/include/dt-bindings/clock/microchip,sama7g5-pmc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * The constants defined in this header are being used in dts and in + * at91 sama7g5 clock driver. + */ + +#ifndef _DT_BINDINGS_CLOCK_MICROCHIP_SAMA7G5_PMC_H +#define _DT_BINDINGS_CLOCK_MICROCHIP_SAMA7G5_PMC_H + +#include + +/* old from before bindings splitup */ +#define SAMA7G5_PMC_MCK0 PMC_MCK /* 1 */ +#define SAMA7G5_PMC_UTMI PMC_UTMI /* 2 */ +#define SAMA7G5_PMC_MAIN PMC_MAIN /* 3 */ +#define SAMA7G5_PMC_CPUPLL PMC_CPUPLL /* 4 */ +#define SAMA7G5_PMC_SYSPLL PMC_SYSPLL /* 5 */ + +#define SAMA7G5_PMC_AUDIOPMCPLL PMC_AUDIOPMCPLL /* 9 */ +#define SAMA7G5_PMC_AUDIOIOPLL PMC_AUDIOIOPLL /* 10 */ + +#define SAMA7G5_PMC_MCK1 PMC_MCK1 /* 13 */ + +#endif From patchwork Mon Feb 10 16:44:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13968230 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D4EF156C6A; Mon, 10 Feb 2025 16:45:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739205928; cv=none; b=GSm7oAYNgkNNtFrecAClmNFZBoEwv4pyH8k1nVfk3FCM67eVKWuvQNONyRnQrn21+eW+qbPZ1QaUnJPd/Pstu6h25yIbQq1TtZhADVG8hdt43TcWAhQ9RWygS4HGEF7fnIa42EFK9B3Knbuz9HTWh/yTKWgGSZfnmNGaF1g1M2Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739205928; c=relaxed/simple; bh=y6LipfjiP70lz0iIolxkGo+eWwABy7qHeLboHDDSDOA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Hj56KwebpN6XGnBuKjWQdp/IarDDK2xpqwW2OdnPzjoCbS6Mp8czXCOmbwYokKxzRU+K6Ibx3vWS2f1HghcbRjeNcmu+hOttn6qHZPWrLZ+7u7ih53U639RY8BPTSrSP1Dpu56YJCl/kPSQNuKH9C+0yUvTjtOgQ5gKnqmaD+P4= ARC-Authentication-Results: i=1; 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bh=AJq/DbnAu7CYKu8ZlgeZYkydXunGRVZL6/T78Qy7bPY=; b=FXzt1v/NGV9VVrv9XiPdMs5VuLSW6s8lDJixS5p1hVswr91HxKVEiUWtOEKMyH1PdeIE8q 3wz2izQofSjcTYsbz6vDxuX/3b4ZPN1ZnuQ8JxIdx1LcRrhbgfCWZz38DNMR+FJpSzJXh/ 5ZUltJvfrripaYoax872kJg1REvx34vyETQu7VGp5BjlY7uU2JI8YOQjrOff+IeTLyrYuH 7SEOZ/8SZl4LOO45U3b3afSdMpz+8LWj/QXHOzNxfrD8Z0rVIWrfpjUqwlc4kpn0S8m+FF JrJyZ9A37UEoTg7E1Oi+siFAVlnoy4XBMrXTzs5VW+krBrr/ll7ktQW9MyxB8A== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 02/16] ARM: dts: microchip: Use new PMC bindings Date: Mon, 10 Feb 2025 17:44:52 +0100 Message-Id: <20250210164506.495747-3-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210164506.495747-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The bindings were split up per SoC before adding new members for missing clocks. Signed-off-by: Alexander Dahl --- Notes: v2: - new patch, not present in v1 arch/arm/boot/dts/microchip/sam9x60.dtsi | 15 ++++++++------- arch/arm/boot/dts/microchip/sam9x7.dtsi | 11 ++++++----- arch/arm/boot/dts/microchip/sama7d65.dtsi | 5 +++-- arch/arm/boot/dts/microchip/sama7g5.dtsi | 23 ++++++++++++----------- 4 files changed, 29 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi index b8b2c1ddf3f1e..1724b79967a17 100644 --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -81,9 +82,9 @@ usb0: gadget@500000 { reg = <0x00500000 0x100000 0xf803c000 0x400>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE SAM9X60_PMC_UTMI>; clock-names = "pclk", "hclk"; - assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_UTMI>; assigned-clock-rates = <480000000>; status = "disabled"; }; @@ -101,9 +102,9 @@ usb2: ehci@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; + clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "usb_clk", "ehci_clk"; - assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_UTMI>; assigned-clock-rates = <480000000>; status = "disabled"; }; @@ -121,7 +122,7 @@ ebi: ebi@10000000 { 0x3 0x0 0x40000000 0x10000000 0x4 0x0 0x50000000 0x10000000 0x5 0x0 0x60000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_MCK>; status = "disabled"; nand_controller: nand-controller { @@ -1063,7 +1064,7 @@ hlcdc: hlcdc@f8038000 { clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; clock-names = "periph_clk","sys_clk", "slow_clk"; assigned-clocks = <&pmc PMC_TYPE_GCK 25>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAM9X60_PMC_MCK>; status = "disabled"; hlcdc-display-controller { @@ -1369,7 +1370,7 @@ pit: timer@fffffe40 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_MCK>; }; clk32k: clock-controller@fffffe50 { diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi index b217a908f5253..458cfb81f8bcf 100644 --- a/arch/arm/boot/dts/microchip/sam9x7.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -477,9 +478,9 @@ can0: can@f8000000 { interrupt-names = "int0", "int1"; clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; clock-names = "hclk", "cclk"; - assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>; + assigned-clocks = <&pmc PMC_TYPE_CORE SAM9X7_PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>; assigned-clock-rates = <480000000>, <40000000>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAM9X7_PMC_UTMI>, <&pmc PMC_TYPE_CORE SAM9X7_PMC_UTMI>; bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; status = "disabled"; }; @@ -493,9 +494,9 @@ can1: can@f8004000 { interrupt-names = "int0", "int1"; clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; clock-names = "hclk", "cclk"; - assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>; + assigned-clocks = <&pmc PMC_TYPE_CORE SAM9X7_PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>; assigned-clock-rates = <480000000>, <40000000>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAM9X7_PMC_UTMI>, <&pmc PMC_TYPE_CORE SAM9X7_PMC_UTMI>; bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; status = "disabled"; }; @@ -1100,7 +1101,7 @@ pmecc: ecc-engine@ffffe000 { mpddrc: mpddrc@ffffe800 { compatible = "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc"; reg = <0xffffe800 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE SAM9X7_PMC_MCK>; clock-names = "ddrck", "mpddr"; }; diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 854b30d15dcd4..111a6a6ef0e00 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -29,7 +30,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a7"; reg = <0x0>; device_type = "cpu"; - clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; + clocks = <&pmc PMC_TYPE_CORE SAMA7D65_PMC_CPUPLL>; clock-names = "cpu"; }; }; @@ -91,7 +92,7 @@ sdmmc1: mmc@e1208000 { clock-names = "hclock", "multclk"; assigned-clocks = <&pmc PMC_TYPE_GCK 76>; assigned-clock-rates = <200000000>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7D65_PMC_MCK1>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi index 17bcdcf0cf4a0..f68c2eb8edd54 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -34,7 +35,7 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; - clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; + clocks = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_CPUPLL>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -189,7 +190,7 @@ ebi: ebi@40000000 { 0x1 0x0 0x48000000 0x8000000 0x2 0x0 0x50000000 0x8000000 0x3 0x0 0x58000000 0x8000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>; + clocks = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_MCK1>; status = "disabled"; nand_controller: nand-controller { @@ -372,7 +373,7 @@ can0: can@e0828000 { clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; clock-names = "hclk", "cclk"; assigned-clocks = <&pmc PMC_TYPE_GCK 61>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>; assigned-clock-rates = <40000000>; bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; status = "disabled"; @@ -388,7 +389,7 @@ can1: can@e082c000 { clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; clock-names = "hclk", "cclk"; assigned-clocks = <&pmc PMC_TYPE_GCK 62>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>; assigned-clock-rates = <40000000>; bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; status = "disabled"; @@ -404,7 +405,7 @@ can2: can@e0830000 { clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; clock-names = "hclk", "cclk"; assigned-clocks = <&pmc PMC_TYPE_GCK 63>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>; assigned-clock-rates = <40000000>; bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; status = "disabled"; @@ -420,7 +421,7 @@ can3: can@e0834000 { clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; clock-names = "hclk", "cclk"; assigned-clocks = <&pmc PMC_TYPE_GCK 64>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>; assigned-clock-rates = <40000000>; bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; status = "disabled"; @@ -436,7 +437,7 @@ can4: can@e0838000 { clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; clock-names = "hclk", "cclk"; assigned-clocks = <&pmc PMC_TYPE_GCK 65>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>; assigned-clock-rates = <40000000>; bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; status = "disabled"; @@ -452,7 +453,7 @@ can5: can@e083c000 { clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; clock-names = "hclk", "cclk"; assigned-clocks = <&pmc PMC_TYPE_GCK 66>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>; assigned-clock-rates = <40000000>; bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; status = "disabled"; @@ -483,7 +484,7 @@ sdmmc0: mmc@e1204000 { interrupts = ; clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; clock-names = "hclock", "multclk"; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>; assigned-clocks = <&pmc PMC_TYPE_GCK 80>; assigned-clock-rates = <200000000>; microchip,sdcal-inverted; @@ -496,7 +497,7 @@ sdmmc1: mmc@e1208000 { interrupts = ; clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; clock-names = "hclock", "multclk"; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>; assigned-clocks = <&pmc PMC_TYPE_GCK 81>; assigned-clock-rates = <200000000>; microchip,sdcal-inverted; @@ -509,7 +510,7 @@ sdmmc2: mmc@e120c000 { interrupts = ; clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; clock-names = "hclock", "multclk"; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>; assigned-clocks = <&pmc PMC_TYPE_GCK 82>; assigned-clock-rates = <200000000>; microchip,sdcal-inverted; From patchwork Mon Feb 10 16:44:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13968231 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0D052500AF; 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Signed-off-by: Alexander Dahl --- Notes: v2: - new patch, not present in v1 drivers/clk/at91/sam9x60.c | 14 ++++++------- drivers/clk/at91/sam9x7.c | 22 +++++++++---------- drivers/clk/at91/sama7d65.c | 42 ++++++++++++++++++------------------- drivers/clk/at91/sama7g5.c | 28 ++++++++++++------------- 4 files changed, 52 insertions(+), 54 deletions(-) diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index db6db9e2073eb..11fe2d05fa9bb 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include "pmc.h" @@ -214,7 +214,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) if (IS_ERR(regmap)) return; - sam9x60_pmc = pmc_data_allocate(PMC_PLLACK + 1, + sam9x60_pmc = pmc_data_allocate(SAM9X60_PMC_PLLACK + 1, nck(sam9x60_systemck), nck(sam9x60_periphck), nck(sam9x60_gck), 8); @@ -237,10 +237,10 @@ static void __init sam9x60_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; - sam9x60_pmc->chws[PMC_MAIN] = hw; + sam9x60_pmc->chws[SAM9X60_PMC_MAIN] = hw; hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck", - "mainck", sam9x60_pmc->chws[PMC_MAIN], + "mainck", sam9x60_pmc->chws[SAM9X60_PMC_MAIN], 0, &plla_characteristics, &pll_frac_layout, /* @@ -263,7 +263,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; - sam9x60_pmc->chws[PMC_PLLACK] = hw; + sam9x60_pmc->chws[SAM9X60_PMC_PLLACK] = hw; hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck", "main_osc", main_osc_hw, 1, @@ -281,7 +281,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; - sam9x60_pmc->chws[PMC_UTMI] = hw; + sam9x60_pmc->chws[SAM9X60_PMC_UTMI] = hw; parent_names[0] = md_slck_name; parent_names[1] = "mainck"; @@ -299,7 +299,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; - sam9x60_pmc->chws[PMC_MCK] = hw; + sam9x60_pmc->chws[SAM9X60_PMC_MCK] = hw; parent_names[0] = "pllack_divck"; parent_names[1] = "upllck_divck"; diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index cbb8b220f16bc..c3c12e0523c4b 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -12,7 +12,7 @@ #include #include -#include +#include #include "pmc.h" @@ -220,7 +220,7 @@ static const struct { .t = PLL_TYPE_DIV, /* This feeds CPU. It should not be disabled */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, - .eid = PMC_PLLACK, + .eid = SAM9X7_PMC_PLLACK, .c = &plla_characteristics, }, }, @@ -242,7 +242,7 @@ static const struct { .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, - .eid = PMC_UTMI, + .eid = SAM9X7_PMC_UTMI, .c = &upll_characteristics, }, }, @@ -264,7 +264,7 @@ static const struct { .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, .c = &audiopll_characteristics, - .eid = PMC_AUDIOPMCPLL, + .eid = SAM9X7_PMC_AUDIOPMCPLL, .t = PLL_TYPE_DIV, }, @@ -275,7 +275,7 @@ static const struct { .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, .c = &audiopll_characteristics, - .eid = PMC_AUDIOIOPLL, + .eid = SAM9X7_PMC_AUDIOIOPLL, .t = PLL_TYPE_DIV, }, }, @@ -297,7 +297,7 @@ static const struct { .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, .c = &lvdspll_characteristics, - .eid = PMC_LVDSPLL, + .eid = SAM9X7_PMC_LVDSPLL, .t = PLL_TYPE_DIV, }, }, @@ -313,7 +313,7 @@ static const struct { */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, .c = &plladiv2_characteristics, - .eid = PMC_PLLADIV2, + .eid = SAM9X7_PMC_PLLADIV2, .t = PLL_TYPE_DIV, }, }, @@ -741,7 +741,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np) if (IS_ERR(regmap)) return; - sam9x7_pmc = pmc_data_allocate(PMC_LVDSPLL + 1, + sam9x7_pmc = pmc_data_allocate(SAM9X7_PMC_LVDSPLL + 1, nck(sam9x7_systemck), nck(sam9x7_periphck), nck(sam9x7_gck), 8); @@ -770,7 +770,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; - sam9x7_pmc->chws[PMC_MAIN] = hw; + sam9x7_pmc->chws[SAM9X7_PMC_MAIN] = hw; for (i = 0; i < PLL_ID_MAX; i++) { for (j = 0; j < 3; j++) { @@ -782,7 +782,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np) switch (sam9x7_plls[i][j].t) { case PLL_TYPE_FRAC: if (!strcmp(sam9x7_plls[i][j].p, "mainck")) - parent_hw = sam9x7_pmc->chws[PMC_MAIN]; + parent_hw = sam9x7_pmc->chws[SAM9X7_PMC_MAIN]; else if (!strcmp(sam9x7_plls[i][j].p, "main_osc")) parent_hw = main_osc_hw; else @@ -838,7 +838,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; - sam9x7_pmc->chws[PMC_MCK] = hw; + sam9x7_pmc->chws[SAM9X7_PMC_MCK] = hw; parent_names[0] = "plla_divpmcck"; parent_names[1] = "upll_divpmcck"; diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index a5d40df8b2f27..024c5abee25ff 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include "pmc.h" @@ -19,8 +19,6 @@ static DEFINE_SPINLOCK(pmc_pll_lock); static DEFINE_SPINLOCK(pmc_mck0_lock); static DEFINE_SPINLOCK(pmc_mckX_lock); -#define PMC_INDEX_MAX 25 - /* * PLL clocks identifiers * @PLL_ID_CPU: CPU PLL identifier @@ -221,7 +219,7 @@ static struct sama7d65_pll { .t = PLL_TYPE_DIV, /* This feeds CPU. It should not be disabled. */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .eid = PMC_CPUPLL, + .eid = SAMA7D65_PMC_CPUPLL, /* * Safe div=15 should be safe even for switching b/w 1GHz and * 90MHz (frac pll might go up to 1.2GHz). @@ -256,7 +254,7 @@ static struct sama7d65_pll { * Therefore it should not be disabled. */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, - .eid = PMC_SYSPLL, + .eid = SAMA7D65_PMC_SYSPLL, }, }, @@ -324,7 +322,7 @@ static struct sama7d65_pll { .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, - .eid = PMC_BAUDPLL, + .eid = SAMA7D65_PMC_BAUDPLL, }, }, @@ -346,7 +344,7 @@ static struct sama7d65_pll { .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, - .eid = PMC_AUDIOPMCPLL, + .eid = SAMA7D65_PMC_AUDIOPMCPLL, }, [PLL_COMPID_DIV1] = { @@ -357,7 +355,7 @@ static struct sama7d65_pll { .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, - .eid = PMC_AUDIOIOPLL, + .eid = SAMA7D65_PMC_AUDIOIOPLL, }, }, @@ -379,7 +377,7 @@ static struct sama7d65_pll { .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, - .eid = PMC_ETHPLL, + .eid = SAMA7D65_PMC_ETHPLL, }, }, @@ -401,7 +399,7 @@ static struct sama7d65_pll { .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, - .eid = PMC_LVDSPLL, + .eid = SAMA7D65_PMC_LVDSPLL, }, }, @@ -423,7 +421,7 @@ static struct sama7d65_pll { .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, - .eid = PMC_UTMI, + .eid = SAMA7D65_PMC_UTMI, }, }, }; @@ -466,7 +464,7 @@ static struct { .ep_mux_table = { 5, }, .ep_count = 1, .ep_chg_id = INT_MIN, - .eid = PMC_MCK1, + .eid = SAMA7D65_PMC_MCK1, .c = 1, }, { .n = "mck2", @@ -483,7 +481,7 @@ static struct { .ep_mux_table = { 5, 6, }, .ep_count = 2, .ep_chg_id = INT_MIN, - .eid = PMC_MCK3, + .eid = SAMA7D65_PMC_MCK3, .c = 1, }, { .n = "mck4", @@ -500,7 +498,7 @@ static struct { .ep_mux_table = { 5, }, .ep_count = 1, .ep_chg_id = INT_MIN, - .eid = PMC_MCK5, + .eid = SAMA7D65_PMC_MCK5, .c = 1, }, { .n = "mck6", @@ -1116,7 +1114,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np) if (IS_ERR(regmap)) return; - sama7d65_pmc = pmc_data_allocate(PMC_INDEX_MAX, + sama7d65_pmc = pmc_data_allocate(SAMA7D65_PMC_INDEX_MAX, nck(sama7d65_systemck), nck(sama7d65_periphck), nck(sama7d65_gck), 8); @@ -1149,7 +1147,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; - sama7d65_pmc->chws[PMC_MAIN] = hw; + sama7d65_pmc->chws[SAMA7D65_PMC_MAIN] = hw; for (i = 0; i < PLL_ID_MAX; i++) { for (j = 0; j < PLL_COMPID_MAX; j++) { @@ -1162,7 +1160,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np) case PLL_TYPE_FRAC: switch (sama7d65_plls[i][j].p) { case SAMA7D65_PLL_PARENT_MAINCK: - parent_hw = sama7d65_pmc->chws[PMC_MAIN]; + parent_hw = sama7d65_pmc->chws[SAMA7D65_PMC_MAIN]; break; case SAMA7D65_PLL_PARENT_MAIN_XTAL: parent_hw = main_xtal_hw; @@ -1211,12 +1209,12 @@ static void __init sama7d65_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; - sama7d65_pmc->chws[PMC_MCK] = hw; + sama7d65_pmc->chws[SAMA7D65_PMC_MCK0] = hw; sama7d65_mckx[PCK_PARENT_HW_MCK0].hw = hw; parent_hws[0] = md_slck_hw; parent_hws[1] = td_slck_hw; - parent_hws[2] = sama7d65_pmc->chws[PMC_MAIN]; + parent_hws[2] = sama7d65_pmc->chws[SAMA7D65_PMC_MAIN]; for (i = PCK_PARENT_HW_MCK1; i < ARRAY_SIZE(sama7d65_mckx); i++) { u8 num_parents = 3 + sama7d65_mckx[i].ep_count; struct clk_hw *tmp_parent_hws[8]; @@ -1265,7 +1263,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np) parent_hws[0] = md_slck_hw; parent_hws[1] = td_slck_hw; - parent_hws[2] = sama7d65_pmc->chws[PMC_MAIN]; + parent_hws[2] = sama7d65_pmc->chws[SAMA7D65_PMC_MAIN]; parent_hws[3] = sama7d65_plls[PLL_ID_SYS][PLL_COMPID_DIV0].hw; parent_hws[4] = sama7d65_plls[PLL_ID_DDR][PLL_COMPID_DIV0].hw; parent_hws[5] = sama7d65_plls[PLL_ID_GPU][PLL_COMPID_DIV0].hw; @@ -1316,8 +1314,8 @@ static void __init sama7d65_pmc_setup(struct device_node *np) parent_hws[0] = md_slck_hw; parent_hws[1] = td_slck_hw; - parent_hws[2] = sama7d65_pmc->chws[PMC_MAIN]; - parent_hws[3] = sama7d65_pmc->chws[PMC_MCK1]; + parent_hws[2] = sama7d65_pmc->chws[SAMA7D65_PMC_MAIN]; + parent_hws[3] = sama7d65_pmc->chws[SAMA7D65_PMC_MCK1]; for (i = 0; i < ARRAY_SIZE(sama7d65_gck); i++) { u8 num_parents = 4 + sama7d65_gck[i].pp_count; struct clk_hw *tmp_parent_hws[8]; diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 8385badc1c706..7dfeec8f2232b 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -12,7 +12,7 @@ #include #include -#include +#include #include "pmc.h" @@ -181,7 +181,7 @@ static struct sama7g5_pll { .t = PLL_TYPE_DIV, /* This feeds CPU. It should not be disabled. */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .eid = PMC_CPUPLL, + .eid = SAMA7G5_PMC_CPUPLL, /* * Safe div=15 should be safe even for switching b/w 1GHz and * 90MHz (frac pll might go up to 1.2GHz). @@ -216,7 +216,7 @@ static struct sama7g5_pll { * Therefore it should not be disabled. */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, - .eid = PMC_SYSPLL, + .eid = SAMA7G5_PMC_SYSPLL, }, }, @@ -304,7 +304,7 @@ static struct sama7g5_pll { .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, - .eid = PMC_AUDIOPMCPLL, + .eid = SAMA7G5_PMC_AUDIOPMCPLL, }, [PLL_COMPID_DIV1] = { @@ -315,7 +315,7 @@ static struct sama7g5_pll { .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, - .eid = PMC_AUDIOIOPLL, + .eid = SAMA7G5_PMC_AUDIOIOPLL, }, }, @@ -379,7 +379,7 @@ static struct { .ep_mux_table = { 5, }, .ep_count = 1, .ep_chg_id = INT_MIN, - .eid = PMC_MCK1, + .eid = SAMA7G5_PMC_MCK1, .c = 1, }, { .n = "mck2", @@ -995,7 +995,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (IS_ERR(regmap)) return; - sama7g5_pmc = pmc_data_allocate(PMC_MCK1 + 1, + sama7g5_pmc = pmc_data_allocate(SAMA7G5_PMC_MCK1 + 1, nck(sama7g5_systemck), nck(sama7g5_periphck), nck(sama7g5_gck), 8); @@ -1028,7 +1028,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; - sama7g5_pmc->chws[PMC_MAIN] = hw; + sama7g5_pmc->chws[SAMA7G5_PMC_MAIN] = hw; for (i = 0; i < PLL_ID_MAX; i++) { for (j = 0; j < PLL_COMPID_MAX; j++) { @@ -1041,7 +1041,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) case PLL_TYPE_FRAC: switch (sama7g5_plls[i][j].p) { case SAMA7G5_PLL_PARENT_MAINCK: - parent_hw = sama7g5_pmc->chws[PMC_MAIN]; + parent_hw = sama7g5_pmc->chws[SAMA7G5_PMC_MAIN]; break; case SAMA7G5_PLL_PARENT_MAIN_XTAL: parent_hw = main_xtal_hw; @@ -1090,11 +1090,11 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; - sama7g5_mckx[PCK_PARENT_HW_MCK0].hw = sama7g5_pmc->chws[PMC_MCK] = hw; + sama7g5_mckx[PCK_PARENT_HW_MCK0].hw = sama7g5_pmc->chws[SAMA7G5_PMC_MCK0] = hw; parent_hws[0] = md_slck_hw; parent_hws[1] = td_slck_hw; - parent_hws[2] = sama7g5_pmc->chws[PMC_MAIN]; + parent_hws[2] = sama7g5_pmc->chws[SAMA7G5_PMC_MAIN]; for (i = PCK_PARENT_HW_MCK1; i < ARRAY_SIZE(sama7g5_mckx); i++) { u8 num_parents = 3 + sama7g5_mckx[i].ep_count; struct clk_hw *tmp_parent_hws[8]; @@ -1136,11 +1136,11 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; - sama7g5_pmc->chws[PMC_UTMI] = hw; + sama7g5_pmc->chws[SAMA7G5_PMC_UTMI] = hw; parent_hws[0] = md_slck_hw; parent_hws[1] = td_slck_hw; - parent_hws[2] = sama7g5_pmc->chws[PMC_MAIN]; + parent_hws[2] = sama7g5_pmc->chws[SAMA7G5_PMC_MAIN]; parent_hws[3] = sama7g5_plls[PLL_ID_SYS][PLL_COMPID_DIV0].hw; parent_hws[4] = sama7g5_plls[PLL_ID_DDR][PLL_COMPID_DIV0].hw; parent_hws[5] = sama7g5_plls[PLL_ID_IMG][PLL_COMPID_DIV0].hw; @@ -1190,7 +1190,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) parent_hws[0] = md_slck_hw; parent_hws[1] = td_slck_hw; - parent_hws[2] = sama7g5_pmc->chws[PMC_MAIN]; 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Mon, 10 Feb 2025 17:45:27 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1739205927; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0WHUhKfS+ZaE2np/nTIVSoQCKqx2vGtVJRjfiTaKlFI=; b=bNcPmcycV16BVxYBZn4F/R/IPE5AjKPvr1AaFSMK12kIuoE0BNKJ8Cf23OP4hppFsuIOqR 3lIVX8EhZlpJfRggCvq0YttBKutSbqIhi5PNgMPwI3QrBk0nmS2XWfd7ValonGF7hISV3A wfAMZ1Hv5YVzrXpeAO0LTP98ALZZfIEg6FuyJlle2Y0UuqGe2URVFn1cdALz2K2RVZLGhT srEOTJkp8b/B8azWu0R1fnlFHsc/h/NYk2qpMU9C+1WQK0UpnZl3IXTDf0BEEKwyqj0GMV bKCIAuER9uvBpFVNfOvka4YmEXpJxSn49oJ1SbQSBBKWEIa5FXUPqsSH5YJsWw== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 04/16] dt-bindings: clock: at91: Allow referencing main rc oscillator in DT Date: Mon, 10 Feb 2025 17:44:54 +0100 Message-Id: <20250210164506.495747-5-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210164506.495747-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The main rc oscillator will be needed for the OTPC to work properly. The new index introduced here was not used on the four affected SoC clock drivers before, but for sama5d2 only (PMC_I2S1_MUX). Link: https://lore.kernel.org/linux-devicetree/20250207-jailbird-circus-bcc04ee90e05@thorsis.com/T/#u Signed-off-by: Alexander Dahl --- Notes: v2: - new patch, not present in v1 include/dt-bindings/clock/microchip,sam9x60-pmc.h | 3 +++ include/dt-bindings/clock/microchip,sam9x7-pmc.h | 3 +++ include/dt-bindings/clock/microchip,sama7d65-pmc.h | 3 +++ include/dt-bindings/clock/microchip,sama7g5-pmc.h | 3 +++ 4 files changed, 12 insertions(+) diff --git a/include/dt-bindings/clock/microchip,sam9x60-pmc.h b/include/dt-bindings/clock/microchip,sam9x60-pmc.h index e01e867e8c4da..dcd3c74f75b54 100644 --- a/include/dt-bindings/clock/microchip,sam9x60-pmc.h +++ b/include/dt-bindings/clock/microchip,sam9x60-pmc.h @@ -16,4 +16,7 @@ #define SAM9X60_PMC_PLLACK PMC_PLLACK /* 7 */ +/* new from after bindings splitup */ +#define SAM9X60_PMC_MAIN_RC 6 + #endif diff --git a/include/dt-bindings/clock/microchip,sam9x7-pmc.h b/include/dt-bindings/clock/microchip,sam9x7-pmc.h index 2df1ff97a5b18..6f17d6553b33c 100644 --- a/include/dt-bindings/clock/microchip,sam9x7-pmc.h +++ b/include/dt-bindings/clock/microchip,sam9x7-pmc.h @@ -22,4 +22,7 @@ #define SAM9X7_PMC_PLLADIV2 PMC_PLLADIV2 /* 14 */ #define SAM9X7_PMC_LVDSPLL PMC_LVDSPLL /* 15 */ +/* new from after bindings splitup */ +#define SAM9X7_PMC_MAIN_RC 6 + #endif diff --git a/include/dt-bindings/clock/microchip,sama7d65-pmc.h b/include/dt-bindings/clock/microchip,sama7d65-pmc.h index f5be643be9b36..5c8e52299c110 100644 --- a/include/dt-bindings/clock/microchip,sama7d65-pmc.h +++ b/include/dt-bindings/clock/microchip,sama7d65-pmc.h @@ -29,4 +29,7 @@ #define SAMA7D65_PMC_INDEX_MAX 25 +/* new from after bindings splitup */ +#define SAMA7D65_PMC_MAIN_RC 6 + #endif diff --git a/include/dt-bindings/clock/microchip,sama7g5-pmc.h b/include/dt-bindings/clock/microchip,sama7g5-pmc.h index ad69ccdf9dc78..7bcd2634da37e 100644 --- a/include/dt-bindings/clock/microchip,sama7g5-pmc.h +++ b/include/dt-bindings/clock/microchip,sama7g5-pmc.h @@ -21,4 +21,7 @@ #define SAMA7G5_PMC_MCK1 PMC_MCK1 /* 13 */ +/* new from after bindings splitup */ +#define SAMA7G5_PMC_MAIN_RC 6 + #endif From patchwork Mon Feb 10 16:44:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13968233 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C74DC24061F; Mon, 10 Feb 2025 16:45:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739205940; cv=none; b=mj7CsAaUXzyDy6nDae/ne2dduO/pxBpHTPZKQvUWp1CflbrsT5P6eXDOBgiBKy4AjADCBIIPgq6HnyFlbx3kKE9//MlWJCpeLKxKbIoJc1piO1mmWEsKApfk++X8YQwi9SK+ZI4t/rFeYFwTvwoGjXKGM5epCP3tILUKmtW+/xY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739205940; c=relaxed/simple; bh=Ib+aRuOZ1DzzF4UQ00U+Y9SNM1ucCEeo0DE0zobw5yw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sX9+kSf2sRLBJ58VkUf6QTcTHef8kDuT1kynCj+DVtcA5iVGEji7JMcZjlX3UFaEGpLcFL+0byQFDRcFtXI3IjITktgcpa4oHfeOXQGnbAIjv7gdTCkXbbBw+svF3lbFHTW7g0tvekZk5hSHQS3kHg1K+glF8vLmg4s7Xnu+xLI= ARC-Authentication-Results: i=1; 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bh=UIGNu3f6Vyqk5hPI7JVYcMMOBwHkl3SRqCUKCqsPTxc=; b=jy8TyQcaMaIs3amJmcfBQvMtkXeLEkYb+iVEDCz891gac0gUP0LwaayyaAGFgmN0RmKCQE zqlD8enJnFxj5IZ8ZgOyQt9fcZ7DagtMziMGiTih3QzyX/k1Ef95jD/lGzoNudB82dSnag NETKvuD06HeeR0+C3RZDpgup/rcH1sRcAMThRgq7hAIJCQ/5GejIvDqeRjWFEbvcqbuGGU F4ztBAq9+b5o4O3Q2rkrA2akfl668wHirYaGgMjpZwkL4ah/2eMnXGlj6+9MQQu3uhHO5s SISq36BQTK2+t2bqhNolkAPfVtSwDX/Z20QRUvi3pEvjBPHts7mzruFb7JNWaQ== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Turquette , Stephen Boyd , Alexandre Belloni , Varshini Rajendran , Ryan Wanner Subject: [PATCH v2 05/16] clk: at91: Allow enabling main_rc_osc through DT Date: Mon, 10 Feb 2025 17:44:55 +0100 Message-Id: <20250210164506.495747-6-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210164506.495747-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 SAM9X60 Datasheet (DS60001579G) Section "23.4 Product Dependencies" says: "The OTPC is clocked through the Power Management Controller (PMC). The user must power on the main RC oscillator and enable the peripheral clock of the OTPC prior to reading or writing the OTP memory." The code for enabling/disabling that clock is already present, it was just not possible to hook into DT anymore, after at91 clk devicetree binding rework back in 2018 for kernel v4.19. Do it for all controllers with an OTPC controller, where the main rc oscillator is required for proper operation. Signed-off-by: Alexander Dahl --- Notes: v2: - split out dt-bindings changes into separate patch - extend to drivers for other SoCs providing the OTPC drivers/clk/at91/sam9x60.c | 1 + drivers/clk/at91/sam9x7.c | 1 + drivers/clk/at91/sama7d65.c | 1 + drivers/clk/at91/sama7g5.c | 1 + 4 files changed, 4 insertions(+) diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index 11fe2d05fa9bb..58a5b6c4473da 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -225,6 +225,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) 50000000); if (IS_ERR(hw)) goto err_free; + sam9x60_pmc->chws[SAM9X60_PMC_MAIN_RC] = hw; hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0); if (IS_ERR(hw)) diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index c3c12e0523c4b..8a2955d1f67c6 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -758,6 +758,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np) 50000000); if (IS_ERR(hw)) goto err_free; + sam9x7_pmc->chws[SAM9X7_PMC_MAIN_RC] = hw; hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0); if (IS_ERR(hw)) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 024c5abee25ff..eaddb154c4381 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1131,6 +1131,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np) 50000000); if (IS_ERR(main_rc_hw)) goto err_free; + sama7d65_pmc->chws[SAMA7D65_PMC_MAIN_RC] = hw; bypass = of_property_read_bool(np, "atmel,osc-bypass"); diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 7dfeec8f2232b..e6d5739371a76 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -1012,6 +1012,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) 50000000); if (IS_ERR(main_rc_hw)) goto err_free; + sama7g5_pmc->chws[SAMA7G5_PMC_MAIN_RC] = hw; bypass = of_property_read_bool(np, "atmel,osc-bypass"); From patchwork Mon Feb 10 16:44:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13968234 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2533222575; Mon, 10 Feb 2025 16:45:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739205949; cv=none; b=sthyqoo5+qAIaxZhITFJ9foJQehuo4K+6+EDJlUFiUG5h0QrJzL82jLkbO/S3ItD6dl7GjtbvWINWpFWSj94ADQSBJk74ySWd48n3Xzl88KFygh7jw78btJp3l9WQldwiVRb5krEcODxpAL0nDCouODCUKDFO1J45TOpkbv9x14= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739205949; c=relaxed/simple; bh=8DxD0g1D7UvJQhlM+gdbyNAf5AQkwySPboNWSreF2Sg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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s=dkim; t=1739205945; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vZsDtBbNTPdOOIKQhPF/5tyxBSQNXhxrVIA8sfG14DQ=; b=gqxwCj6nzhhpK4oe02YY1gXNTd42nHtNyKQpHuYFPMMnyy2Yqc6rV1jDvv7fm0ErmFVX3q S5rSotWYs/EqlMH8uSLQ5qDg02DpveFtZAXhYxTQIZgBjIhJnjHPoWc1myo4saecEEadx0 uKbqzsuaz07v+s6b6lR4A1g/goZSryZ6KEJuHJDT1gDnv+pZ1aBpT+wHBlg4V2aYN6CZnX 9Q1erZ4LKVLhGdrtir+8ofoIkhefoAo3TwXvXL2gmgj40VsqfleZ/+JMzRACcJKnAimdVa pa8bs45er6dItkBl9Jrdr/b3w6bGu82noMwjzozgNofPqyriBTmR2xx1GuVo2w== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Turquette , Stephen Boyd , Alexandre Belloni , Varshini Rajendran , Ryan Wanner Subject: [PATCH v2 06/16] clk: at91: Add peripheral id for OTPC Date: Mon, 10 Feb 2025 17:44:56 +0100 Message-Id: <20250210164506.495747-7-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210164506.495747-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 That peripheral clock is required for proper OTPC function. Link: https://lore.kernel.org/linux-clk/ec34efc2-2051-4b8a-b5d8-6e2fd5e08c28@microchip.com/T/#u Signed-off-by: Alexander Dahl --- Notes: v2: - new patch in series, was not present in v1 drivers/clk/at91/sam9x60.c | 1 + drivers/clk/at91/sam9x7.c | 1 + drivers/clk/at91/sama7d65.c | 1 + drivers/clk/at91/sama7g5.c | 1 + 4 files changed, 4 insertions(+) diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index 58a5b6c4473da..ce0f73125e87c 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -144,6 +144,7 @@ static const struct { { .n = "isi_clk", .id = 43, }, { .n = "pioD_clk", .id = 44, }, { .n = "tcb1_clk", .id = 45, }, + { .n = "otpc_clk", .id = 46, }, { .n = "dbgu_clk", .id = 47, }, /* * mpddr_clk feeds DDR controller and is enabled by bootloader thus we diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index 8a2955d1f67c6..7278b9d15d0cf 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -402,6 +402,7 @@ static const struct { { .n = "isi_clk", .id = 43, }, { .n = "pioD_clk", .id = 44, }, { .n = "tcb1_clk", .id = 45, }, + { .n = "otpc_clk", .id = 46, }, { .n = "dbgu_clk", .id = 47, }, /* * mpddr_clk feeds DDR controller and is enabled by bootloader thus we diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index eaddb154c4381..19613e587d5b9 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -637,6 +637,7 @@ static struct { { .n = "mcan2_clk", .p = PCK_PARENT_HW_MCK5, .id = 60, .r = { .max = 200000000, }, }, { .n = "mcan3_clk", .p = PCK_PARENT_HW_MCK5, .id = 61, .r = { .max = 200000000, }, }, { .n = "mcan4_clk", .p = PCK_PARENT_HW_MCK5, .id = 62, .r = { .max = 200000000, }, }, + { .n = "otpc_clk", .p = PCK_PARENT_HW_MCK0, .id = 63, }, { .n = "pdmc0_clk", .p = PCK_PARENT_HW_MCK9, .id = 64, .r = { .max = 200000000, }, }, { .n = "pdmc1_clk", .p = PCK_PARENT_HW_MCK9, .id = 65, .r = { .max = 200000000, }, }, { .n = "pit64b0_clk", .p = PCK_PARENT_HW_MCK7, .id = 66, }, diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index e6d5739371a76..5147d8f34a3be 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -502,6 +502,7 @@ static struct { { .n = "mcan3_clk", .p = PCK_PARENT_HW_MCK1, .id = 64, .r = { .max = 200000000, }, }, { .n = "mcan4_clk", .p = PCK_PARENT_HW_MCK1, .id = 65, .r = { .max = 200000000, }, }, { .n = "mcan5_clk", .p = PCK_PARENT_HW_MCK1, .id = 66, .r = { .max = 200000000, }, }, + { .n = "otpc_clk", .p = PCK_PARENT_HW_MCK0, .id = 67, }, { .n = "pdmc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 68, .r = { .max = 200000000, }, }, { .n = "pdmc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 69, .r = { .max = 200000000, }, }, { .n = "pit64b0_clk", .p = PCK_PARENT_HW_MCK1, .id = 70, }, From patchwork Mon Feb 10 16:44:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13968235 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DD3F24BD0F; Mon, 10 Feb 2025 16:45:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739205950; cv=none; b=ifIykvuE3E0etLuAJ2/x/Ga9Un68X6mAVrfF7eednBbYN1FaFHzjlDyUYM3GDq/ij7+aCpMDByUsbm9tBFH8E5sXgh7zUZQt8B+wem6rEZqBj/QXmq+mJHk5APwYN062PjpUGVnojisO1EOWFOoR9lETA3kql3W9DPvl9+nv4cg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739205950; c=relaxed/simple; bh=b4lYTDnpkr0KJoUnCnG4HZU0UkFb/yot10aEK6Eco8M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mAlaxUixTRM/rBnd10GOmwrfSvZTJwhqSgc1UMergJGOvz4KPfK4yNKbidv340tRfS8nP8zlAM1wOPYqYqYt+/4R3MoCv6tMemqzRlnNpJuaARYbgvNQPLtaAoGvXU7QFSNU07daWVmBoH6jfCCous6yx+ytpDiugbC0rWVh5L4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com; spf=pass smtp.mailfrom=thorsis.com; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b=ZwlPk/EE; arc=none smtp.client-ip=217.92.40.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thorsis.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b="ZwlPk/EE" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 160D2148026A; Mon, 10 Feb 2025 17:45:46 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1739205946; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=b7LZo2mymbyoxBQ+HVYCFE4IwziNlomr+D3mfbsPVcQ=; b=ZwlPk/EEHCFUY+znTldtIjO5fYWORis2QIZRHWBwqye73x6TlDNAIqmxTV02KONZ7hIlNL BbTXgOxSYjYl6FkT4ruIcukZk6T9rMXUK7joxvXKDc4XqlsxYFd7HFhdeL94l+yFMUyWDo XqMh1DnERQMtiX+h6T51jhwHgyt/0iNMjkn9Hl1wboli+b8RY/IQ+5GWV316kukApfpK60 mIhpfwESXhoSI2Pq2A51zbxVbdrLD374bkMtPXPmzsbFmE5fVYj0VSWscfRNKQmy+ffnWP v7XI85fOimcPRYzaZxmN+SgKvcLMV88zniERCYZwAH3zHdHErjPk24gUf1n0MA== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 07/16] dt-bindings: nvmem: microchip-otpc: Add compatible for SAM9X60 Date: Mon, 10 Feb 2025 17:44:57 +0100 Message-Id: <20250210164506.495747-8-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210164506.495747-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The SAM9X60 SoC family has a similar, but slightly different OTPC to the SAMA7G5 family. Signed-off-by: Alexander Dahl Acked-by: Krzysztof Kozlowski --- Notes: v2: - Fix dt_binding_check warnings .../devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml index cc25f2927682e..9a7aaf64eef32 100644 --- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml +++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml @@ -21,7 +21,9 @@ allOf: properties: compatible: items: - - const: microchip,sama7g5-otpc + - enum: + - microchip,sam9x60-otpc + - microchip,sama7g5-otpc - const: syscon reg: From patchwork Mon Feb 10 16:44:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13968236 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4682424F5BB; Mon, 10 Feb 2025 16:45:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739205950; cv=none; b=Sz8w+9/by/EsbM99Q2Fl6jBrOxmPKyFi19AkjVMHWWGFyzDkKr5gT0Er356U2fkL7ZjNjN6Al8mo8CP+7b+HmPYw2w6pWzmPbTK/fP4z9YI5iCne+1btEHkClsEalGsFKTiHqyz6/nEt9RyfXG90AP4MHfF3Iti+nI6Y105sryE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739205950; c=relaxed/simple; bh=GMFw1/abymd1ov05uZwkd1yWlJK+I5N0ohjbO8CqvMw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GM59R99g6eoq2ZDw1Z33wI7ggHHg3dcObJQN/P7zN/63O+aBPu3iVMGowj4L1BkWdzEHSKSqBgDQt99kgYK3zPadKp5HRegAJN+ytWdnuDYaAkDVXwW394hgWMGWIQ18lh3D6MC+crdzNyJFl5koa2A+3aMG5FjgDbRJuoLLRaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com; spf=pass smtp.mailfrom=thorsis.com; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b=mt+s6AcA; arc=none smtp.client-ip=217.92.40.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thorsis.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b="mt+s6AcA" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DD53C1480320; Mon, 10 Feb 2025 17:45:46 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1739205947; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JxVraOdaNDoa+gL84QMf+jc4LDKQyFyDdKOVrhJTQNU=; b=mt+s6AcAI14JX3eZwDjERM8NyrjFx+5WuXH238XMXaxWVLeZ7DgMKY7ipf84kiRGqCHUJi FERQ3cjmDy1cnVGCXBATXKBXaj/gaqnP3i5QsqYOAaRVbrOh+8Sn6ZmApR6hz9xwmuNdAb 8Zbd8cfM2P3eZV3jOW3+snM/g1cyh5HCe6WSd/+3QtONJnaIErcHgbVCuf5jWBscMhyScU wIiMN1/BRmIbINqqmb/sDMHFlOunGmcw7M5d5cuNxRTin1TdNzTQywB4PX/ols3QFOki04 /axBkI/mbF5FKp/5mGgLUQwnbACzIyP/2QVIUO/YHUiGtGDGdq1CuYfDPbV31A== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 08/16] dt-bindings: nvmem: microchip-otpc: Add required clocks Date: Mon, 10 Feb 2025 17:44:58 +0100 Message-Id: <20250210164506.495747-9-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210164506.495747-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The OTPC requires both the peripheral clock through PMC and the main RC oscillator. Seemed to work without explicitly enabling those clocks on sama7g5 before, but did not on sam9x60. Older datasheets were not clear and explicit about this, but recent are, e.g. SAMA7G5 series datasheet (DS60001765B), section 30.4.1 Power Management: > The OTPC is clocked through the Power Management Controller (PMC). > The user must power on the main RC oscillator and enable the > peripheral clock of the OTPC prior to reading or writing the OTP > memory. Link: https://lore.kernel.org/linux-clk/ec34efc2-2051-4b8a-b5d8-6e2fd5e08c28@microchip.com/T/#u Signed-off-by: Alexander Dahl --- Notes: v2: - new patch, not present in v1 .../nvmem/microchip,sama7g5-otpc.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml index 9a7aaf64eef32..1fa40610888f3 100644 --- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml +++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml @@ -29,6 +29,16 @@ properties: reg: maxItems: 1 + clocks: + items: + - description: main rc oscillator + - description: otpc peripheral clock + + clock-names: + items: + - const: main_rc_osc + - const: otpc_clk + required: - compatible - reg @@ -37,6 +47,8 @@ unevaluatedProperties: false examples: - | + #include + #include #include otpc: efuse@e8c00000 { @@ -44,10 +56,26 @@ examples: reg = <0xe8c00000 0xec>; #address-cells = <1>; #size-cells = <1>; + clocks = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_MAIN_RC>, <&pmc PMC_TYPE_PERIPHERAL 67>; + clock-names = "main_rc_osc", "otpc_clk"; temperature_calib: calib@1 { reg = ; }; }; + - | + #include + #include + #include + + efuse@eff00000 { + compatible = "microchip,sam9x60-otpc", "syscon"; + reg = <0xeff00000 0xec>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_MAIN_RC>, <&pmc PMC_TYPE_PERIPHERAL 46>; + clock-names = "main_rc_osc", "otpc_clk"; + }; + ... From patchwork Mon Feb 10 16:50:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13968241 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C87822586DD; Mon, 10 Feb 2025 16:50:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739206261; cv=none; b=LriWE5objBs5lYQyzTT+vNlEfIiApNp9h9uulrWoZ6/xAJqOdvbY7ZRJgZ7s78hPIrAhBEtWFGBfebfA1rVgItROPKkR5PZYpKH/cy4zQ9QjIm0fhoGlwEyUxL6lRwinFDGlyoC6hxTfhbSHQcZ6Jt+P3iu+BapHj1MWbD9a2EY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739206261; c=relaxed/simple; bh=oNYp33jxngaML7ct2N4mOAELHAXsHNrKBnIHuGSuNlQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sf6EGzdIhPEJeNFzYEQxIiN5zyMDX6Sr2UhoHy5CeyOTxQgjKsaW/h4EWTW2L7sqQUfFq/vjHdiSduoOvdxdqE585SH7Ip3maRxDeS9ZL14bFMDR5N6mHhFxjzOR8UU5RWAdff1dUauBN/qPCIzMpmvmQ9WvxyQkT0HsAtLBrMA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com; spf=pass smtp.mailfrom=thorsis.com; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b=WeufU5F0; arc=none smtp.client-ip=217.92.40.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thorsis.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b="WeufU5F0" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A2CC71480320; Mon, 10 Feb 2025 17:50:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1739206257; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Dx2AyCMYhFFbWrbn642fofkzdPw2vsH5Sq2hYcPNPjo=; b=WeufU5F04oIdoa+jIjBiljm+kcpuXaacU7TtFk2amz8xodrGnWESGchS1CTSG5Gu678GPz p+x8WZu1frRJNtPrCDfoULtLl5W4uz5e7yr+1l8rqHdTdD2WU+alJv7UgS8j5nkS6YniLc y/AKnxJiAz24d7dBsfxsoDjNdoAFxcaoGroNUlOwkPy2lRxMuG2tcK1hqUEg1SfuNuAfNF /H3cruIVrUfKYa6pvFsc8kU6udnA9/5rer4TZOVgq3lqNFAonQCYWw7hKgWqqSRkGVndHJ k5RzWCgc8M8rFEl29o9yvFppLhkYLwUqQKx+XP8pv7zYEsfnYvJMZG9kix+U0A== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla , Greg Kroah-Hartman Subject: [PATCH v2 09/16] nvmem: microchip-otpc: Avoid reading a write-only register Date: Mon, 10 Feb 2025 17:50:47 +0100 Message-Id: <20250210165050.496486-1-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210164506.495747-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The OTPC Control Register (OTPC_CR) has just write-only members. Reading from that register leads to a warning in OTPC Write Protection Status Register (OTPC_WPSR) in field Software Error Type (SWETYP) of type READ_WO (A write-only register has been read (warning).) Just create the register write content from scratch is sufficient here. Signed-off-by: Alexander Dahl Fixes: 98830350d3fc ("nvmem: microchip-otpc: add support") --- Notes: v2: - Add Fixes tag - Remove temporary variable usage - Reword misleading subject (s/writing/reading/) drivers/nvmem/microchip-otpc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c index df979e8549fdb..e2851c63cc0b4 100644 --- a/drivers/nvmem/microchip-otpc.c +++ b/drivers/nvmem/microchip-otpc.c @@ -82,9 +82,7 @@ static int mchp_otpc_prepare_read(struct mchp_otpc *otpc, writel_relaxed(tmp, otpc->base + MCHP_OTPC_MR); /* Set read. */ - tmp = readl_relaxed(otpc->base + MCHP_OTPC_CR); - tmp |= MCHP_OTPC_CR_READ; - writel_relaxed(tmp, otpc->base + MCHP_OTPC_CR); + writel_relaxed(MCHP_OTPC_CR_READ, otpc->base + MCHP_OTPC_CR); /* Wait for packet to be transferred into temporary buffers. */ return read_poll_timeout(readl_relaxed, tmp, !(tmp & MCHP_OTPC_SR_READ), From patchwork Tue Feb 11 06:52:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13970195 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8271B190674; Tue, 11 Feb 2025 06:52:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256756; cv=none; b=lVmagSoi1IS/JODuG7fsbny0zcn46/Y/TiIDbxs++VLiM21ThEI1B4d5YQvP3pZ17wGhUqeifL/M0XiYB0NrzK0Ed51/dyy0ohq86TK5G5lWaN0610vsAamiLiMM37stQcP2JWs7I/ZIcKSdpCFf25+JNu9u2GlBE4Nr95s0YE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256756; c=relaxed/simple; bh=6mIJYzmVBucysBvmuxFwplO26bkr8ex6WKmLy55KY0U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DezTlMekGDfnS42BbesaWkKz26BLGj5rMnSNqTz2cbNfh+kNCKM1HYrELqQ95oUUXgVWv3gI3/Y8YJBX/noqQ5MKtA7Ch42UUmtwA+u+GiiJNg95WfgF+EbI0Ad0rg4O6Ak0da+F+lcrbJDWy1nnBajMtos2CINk7GC9vZ6UuZw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com; spf=pass smtp.mailfrom=thorsis.com; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b=roZpjScj; arc=none smtp.client-ip=217.92.40.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thorsis.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b="roZpjScj" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 81BB61480388; Tue, 11 Feb 2025 07:52:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1739256749; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QiFIIYGgGBWuarCiW5+YZwUI5o3pOP+hr5uNDNTqvG4=; b=roZpjScjYGJ8VLAI8XAAMZXHJfN9L7/Q4kz4gM2SF3Z7rgmg/ifXKDsGxmjqAahtSX1VMs PzHPeXcowl1BwsE6qUyriU6sA9YnOWcYRhHvOu6T5GT2awj8nFIBD/JX9v0YaLUtiFsIwo iTdMZdGqJIpv5AeKwIZ/aPmdbfFf7d1qo6GsFp74tMo/TmU6m2L3gR0dAQe3A4diNar9l3 sHySDBBRFsHcikVR6BzEZ7s44lCM8r2L8YEOs6OCEElM7ypZl30woHag+jj6w6UzGJHYKj 12pvmlG2LIHeXHmaTdybGcHcyrBvjFd03UW5CH+ZQAsiRrTVZhdsCiUKobLecg== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla , Greg Kroah-Hartman Subject: [PATCH v2 10/16] nvmem: microchip-otpc: Fix swapped 'sleep' and 'timeout' parameters Date: Tue, 11 Feb 2025 07:52:21 +0100 Message-Id: <20250211065223.4831-1-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210164506.495747-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Makes no sense to have a timeout shorter than the sleep time, it would run into timeout right after the first sleep already. While at it, use a more specific macro instead of the generic one, which does exactly the same, but needs less parameters. Signed-off-by: Alexander Dahl Fixes: 98830350d3fc ("nvmem: microchip-otpc: add support") --- Notes: v2: - Add Fixes tag drivers/nvmem/microchip-otpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c index e2851c63cc0b4..bf7e5167152cb 100644 --- a/drivers/nvmem/microchip-otpc.c +++ b/drivers/nvmem/microchip-otpc.c @@ -85,8 +85,8 @@ static int mchp_otpc_prepare_read(struct mchp_otpc *otpc, writel_relaxed(MCHP_OTPC_CR_READ, otpc->base + MCHP_OTPC_CR); /* Wait for packet to be transferred into temporary buffers. */ - return read_poll_timeout(readl_relaxed, tmp, !(tmp & MCHP_OTPC_SR_READ), - 10000, 2000, false, otpc->base + MCHP_OTPC_SR); + return readl_relaxed_poll_timeout(otpc->base + MCHP_OTPC_SR, tmp, + !(tmp & MCHP_OTPC_SR_READ), 2000, 10000); } /* From patchwork Tue Feb 11 06:52:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13970193 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8277F1E6DCF; Tue, 11 Feb 2025 06:52:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256755; cv=none; b=sWddPsT+TIpmCm37hLytp6NlKucOrAJLUGPVhWBhRWyA4CpnwF18ojwkVsoxxSWMd8NzNQBfnn1QaIE8WVpRobhEqUFBKE1fjL2DKZqEMb1EPK2eRv+a9tDe82RI1P6n4w9Dj45nCp/UFtIfMM4T3QVLqt1AD1KGiwSiGfmuzy4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256755; c=relaxed/simple; bh=A+AkBIPD4cMDrgF315D/sUXmWXFAMXQ9kIytyxl859Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=c4EzPxRddJ6kB4OjOwQ/4Q6JerQwrFF4AXQQ55RksJU3YCyJgU7bG6p/N9L+Bqylqvl1xkSgeyn8I3tgeBJvZjKtnRQbnIlcKLVinPHTwP+ndtl/640SGdn2Tb7E+99JDbrhlDdfVbEvUuPqx7MqcScHSzDKkN0jqrT4GdmkUQk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com; spf=pass smtp.mailfrom=thorsis.com; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b=GhUSxRtB; arc=none smtp.client-ip=217.92.40.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thorsis.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b="GhUSxRtB" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 02FE2148718D; Tue, 11 Feb 2025 07:52:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1739256750; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=I7ZPupAqKk5CZVK/CQ4Ue0k5HUeF4M2ZpeGOEPD1OnQ=; b=GhUSxRtBnj0vU0y6JUZzwoLMI/zhGfkVr4ENF3tc+svAb6TGUl3fu3ehDPDmgcjDCAkQvN /koKqFqKPvzJzjkUTljbK8oIpE6gShLEpSvhprxe83Tnat3ZWKdRAIorZx2Du8iOf0r0I/ shuUx2d2fAgckDw3RM+EGM6CI+Z2ArGeLW0H7JfqnliNHTKmbD+eqvb5hNQLbv955qfg/K tljAXGXM+14DIQcROM2sfJpJlgSUVfHZDbTIDYCDFnrjgEu7RbQaLUzSqgN7yv+PQ3vlgH FEdNw/Yu3OpcuIanseMyBFWFV7fXmxOQDojK7+Jgy8aptGiZAXvGwmFACvAdAA== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 11/16] nvmem: microchip-otpc: Add SAM9X60 support Date: Tue, 11 Feb 2025 07:52:22 +0100 Message-Id: <20250211065223.4831-2-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250211065223.4831-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> <20250211065223.4831-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Register layout is almost identical to SAMA7G5 OTPC. SAMA7G5 has some additional bits in common registers, and some additional registers all related to custom packages in secure world. None of these are currently used by the driver. Signed-off-by: Alexander Dahl --- Notes: v2: - Reword commit message (additional information about SoC differences) drivers/nvmem/microchip-otpc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c index bf7e5167152cb..d39f2d57e5f5e 100644 --- a/drivers/nvmem/microchip-otpc.c +++ b/drivers/nvmem/microchip-otpc.c @@ -269,6 +269,7 @@ static int mchp_otpc_probe(struct platform_device *pdev) static const struct of_device_id __maybe_unused mchp_otpc_ids[] = { { .compatible = "microchip,sama7g5-otpc", }, + { .compatible = "microchip,sam9x60-otpc", }, { }, }; MODULE_DEVICE_TABLE(of, mchp_otpc_ids); From patchwork Tue Feb 11 06:52:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13970194 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AB8E1E883E; Tue, 11 Feb 2025 06:52:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256756; cv=none; b=jwGPGjifj711Uc5MFVSYvGJUM24Dz60Ajpn2v4f9oc4/dgUmQ2xmhARqMJ7CdgIFx4nXhkPjnAvFgNZK6CQVZ36zVxjk/GbE4r/6UYakM+HakxPs3jHo3TxNG0acy2rkK/ID8L5n6foxkjbquHQ/jVbU165tYDJh/k0uAdlRwQo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256756; c=relaxed/simple; bh=6Nnpo/wyqDm7AnIKoOm4JPNVZ5n7R6N3ycKxmow5nJs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qnXYYvoW/ZsV/e4lLTwenIp1NdY8tv2/zfxomr+rb+Tdl8yt99XGZw7v/U/iUp7P99NfFkIHh259UeLVMqrVBtN9qGtk0n2tbE5Gkbpz7Yy/v+2VjCGR4ZQCbZbY/KG28y8OeYdSy+7PZ+tmuFuecxjByeZSXoOsgMLrWkijaac= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com; spf=pass smtp.mailfrom=thorsis.com; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b=VmQ9o9xY; arc=none smtp.client-ip=217.92.40.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thorsis.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b="VmQ9o9xY" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 60BFD1487190; Tue, 11 Feb 2025 07:52:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1739256751; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mJiswliuC8yJUwUEEk+zWNkofLRfEQuTytGzzJetlvI=; b=VmQ9o9xYAgNrT+nU8eBegHtGR8nBQlz3zDcxlT7SvS+Q1fNzgj+bt7raCaHVaG6fH3/47f lDGAAnSm9LiotxkTQfrEt5sx6wh2aVYFuOZT43NdGjW2bnGWrnUPVcmdfZLlRI0aPnap7m REPJqrhwawW67j+lfDn0Q6keJ889Wv1C+r2HGne/vQA3YMKaF4RCvbofyFKnXyrq54MIh8 Eau6kAidC43rG4o0GoDR/hql3mSwPTRq+RcHe9WjXAGZk23Zb1mUGX8u45SFextzXNBbVH ETEyYnlIx61LMyv/MFA7v3ED9uPfdNX3vXtLwTX+yZUitF5d3+7NCLqlNRozMw== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 12/16] ARM: dts: microchip: sama7g5: Add OTPC clocks Date: Tue, 11 Feb 2025 07:52:23 +0100 Message-Id: <20250211065223.4831-3-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250211065223.4831-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> <20250211065223.4831-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 These clocks should be enabled, datasheet says: > The OTPC is clocked through the Power Management Controller (PMC). > The user must power on the main RC oscillator and enable the > peripheral clock of the OTPC prior to reading or writing the OTP > memory. Earlier discussions suggest, MCK0 must be enabled, too. MCK0 is parent of peripheral otpc_clk, so this is done implicitly. Link: https://lore.kernel.org/linux-clk/ec34efc2-2051-4b8a-b5d8-6e2fd5e08c28@microchip.com/T/#u Signed-off-by: Alexander Dahl --- Notes: v2: - new patch, not present in v1 arch/arm/boot/dts/microchip/sama7g5.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi index f68c2eb8edd54..b33204688b90c 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -1023,6 +1023,8 @@ otpc: efuse@e8c00000 { reg = <0xe8c00000 0x100>; #address-cells = <1>; #size-cells = <1>; + clocks = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_MAIN_RC>, <&pmc PMC_TYPE_PERIPHERAL 67>; + clock-names = "main_rc_osc", "otpc_clk"; temperature_calib: calib@1 { reg = ; From patchwork Tue Feb 11 06:53:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13970196 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E5F31E9B17; Tue, 11 Feb 2025 06:53:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256793; cv=none; b=lWYrkHDvnNTfteFdcdCcLFf68ntWkxXV+itMUDbLTAhyXeKvAo4BWDhzDE5YimeWA5Zw3juC5EjCx6XuM2vGFFUbnj4B5sqAElYBtzObvfgOA3aI98FpVYR15ZgFUzQjIMqIioEXFL5qv+xLCL63BoF/cLDJUOykbPaULUC3cUg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256793; c=relaxed/simple; bh=IB7avKqpVovtyYt3B+xnMLSza+KzVisN0RPkQRbQuS8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sTkwHOQ38r0h0jjM0ICuoCjbPByUn0Vrs8cUEAKO0sPYHNcQSrVPB2GTLVL0nyO9XV05ulK9l0bSZ4AKSZXdmFve5xBBQBpcuzBrE3Iu/HXxOG7TTSMKDItUvbZDcuOE6TnCGjWt7JR2y5yafNeR8Mi1LnACtpkG39pIbEUxKFo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com; spf=pass smtp.mailfrom=thorsis.com; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b=NIe33w8+; arc=none smtp.client-ip=217.92.40.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thorsis.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b="NIe33w8+" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7DA1E1480388; Tue, 11 Feb 2025 07:53:09 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1739256789; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RpKbxzsb7RKOzJwg1Uq2SN9OBeCYnqQPSZz6F1//cF8=; b=NIe33w8+6L1Z4pJRrUOakrYKPKkAMwv0sWpdx5l+3bIRD1REV744LKrimk8dzE67GmIIz0 gDLYzeMDCtZ4aGIWUuk8FGpnTFiNXzh41xY4HcwIjk+FOdoOSJ6D+6fph9X3EoS1hXIYvW 9GnU9C6nZtk8HgoaiwcU6MH8klqK+1HmD0wv7T+WeUmksq/NoDYpGs2bbL9qfdw5+yrMz/ gPstDeXz04Hb8YHPcYhQeNIzSCygeKKy4ro1py8nEropB22myO/5p/y0XuUBC8qmy4lxA3 NwWa2506ksdgOsW6dW/JjKTDqBbK5tx3tmIl6bV4aaI6ixPuti/fnG/LfB25yg== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 13/16] ARM: dts: microchip: sam9x60: Add OTPC node Date: Tue, 11 Feb 2025 07:53:01 +0100 Message-Id: <20250211065304.5019-1-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210164506.495747-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The One-Time Programmable (OTP) Memory Controller (OTPC) is the secure interface between the system and the OTP memory. It also features the Unique Product ID (UID) registers containing a unique serial number. See datasheet (DS60001579G) sections "7. Memories" and "23. OTP Memory Controller (OTPC)" for reference. Signed-off-by: Alexander Dahl --- Notes: v2: - squashed with patch adding the clock properties arch/arm/boot/dts/microchip/sam9x60.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi index 1724b79967a17..af859f0b83a0f 100644 --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -157,6 +158,15 @@ sdmmc1: sdio-host@90000000 { status = "disabled"; }; + otpc: efuse@eff00000 { + compatible = "microchip,sam9x60-otpc", "syscon"; + reg = <0xeff00000 0xec>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_MAIN_RC>, <&pmc PMC_TYPE_PERIPHERAL 46>; + clock-names = "main_rc_osc", "otpc_clk"; + }; + apb { compatible = "simple-bus"; #address-cells = <1>; From patchwork Tue Feb 11 06:53:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13970197 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F24E61E9B23; Tue, 11 Feb 2025 06:53:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256794; cv=none; b=HenSZiyYDUlictnKuPOtZtGBw+yP5oBqEqr18oamGmd+q3hF4LhfjSJx4BaP14xlUlGIgUk+CL3lhJk0JmQSU45TYDPW2zDgdj2y+dquyPtbSxy0wgwRuREfqCler/ENIg4s3VLLRiN3eUdfbL+GxRy/hBkM554mbRiftVG996w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256794; c=relaxed/simple; bh=VRmUa/s3Nl9xiy/3IgREQzt2mmD318TmEYFUI0lfwDQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Sg06lYjcLTflAke1nz2u/T3aOYinVz3sN47fiUaDRqg0UKR4decReSXkeWl6HLjLHQUaFHSKyJRFItskPFE8PsssocZnun7O8KKIhCwtS4fvftXABquyjuP9DUd0rOIU1aV6XCaQ+1/gFmfv/XASDNGN/F93AfOUtMip8VnbBUY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com; spf=pass smtp.mailfrom=thorsis.com; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b=Uj41sTPV; arc=none smtp.client-ip=217.92.40.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thorsis.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b="Uj41sTPV" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 372FF1487178; Tue, 11 Feb 2025 07:53:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1739256790; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kcrBcoZxZD0KOSfIajrWXKnkY7Tho0NlrAQP/789iY8=; b=Uj41sTPVbuELc7zWPiWuQOLNaPqUKRlyhq7COUvGzHhUjh4zIP9i1BucViH/E6nL7iezJ/ u06N3hZn7t+yzEdzw/0kEeiZjBAJWn16TO8Z7Mmuv2MyUhwPRyY4mRviZ2Xz7yjzTjrAug jBzigh7V2l4XHPK54bBjG2r2c0CfHhDxig+XDrCO5GstJPEtcWlOzKgPS8Ez+MXYtpqDU6 RhY+is7N+3QPE3EChkE+Kn5Rh/ZZ1ssauiFM4FfZV/1H3y3ZuBSOsQtReuzFOkaME875Fx zG2iqSZpUAWIR9vIJ0eAHd03RzQOx1xDQNpGzPfgAX28PUgGlzDiEHVe1dSRhg== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Belloni Subject: [PATCH v2 14/16] ARM: dts: microchip: sam9x60_curiosity: Enable OTP Controller Date: Tue, 11 Feb 2025 07:53:02 +0100 Message-Id: <20250211065304.5019-2-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250211065304.5019-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> <20250211065304.5019-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Allows to access the OTP memory now, and Product UID later. Signed-off-by: Alexander Dahl --- Notes: v2: - same as in v1, no changes arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts index b9ffd9e5faacc..c110a8e87568a 100644 --- a/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts @@ -252,6 +252,10 @@ ethernet-phy@0 { }; }; +&otpc { + status = "okay"; +}; + &pinctrl { adc { pinctrl_adc_default: adc-default { From patchwork Tue Feb 11 06:53:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13970198 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8097E1E9B25; Tue, 11 Feb 2025 06:53:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256795; cv=none; b=k/z37ooLaRUz5v2JgXv6f8BKM0J44A3jGxX9wpVza88yz14vx7FZMfKRn2JDmP7wZECiG+emJGqSORGhiLGYaNZzBcbFkUyGoIT6yQ2xGksy92qx4sNQdFeZdYwk9MZaDA25wmZZvzxZReYGnDFyhh+qW3rIT+TLbc/HgCS2BGQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256795; c=relaxed/simple; bh=C4obFeVAgYCCUOZg+qluTM/kRQ1+ugEIZX9ckuzFnvk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=de8Mvai5cOg/dPfg/J/Hf5ZabwNbPNuQ0u4K2FlAc1RlHa07kE/4MFjeyqXFr110zhUFGx2bUPJRoUGNoPnZbILyHrLdHH99WO4Uqg/nBSei4pqPFhREPHweGlMWwOHnaMZyz0eXyKDyetFD6c2vt6Oxp9LMcbSgCE40F+4G6fA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com; spf=pass smtp.mailfrom=thorsis.com; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b=Q2h4rqak; arc=none smtp.client-ip=217.92.40.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thorsis.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b="Q2h4rqak" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1ACE5148718D; Tue, 11 Feb 2025 07:53:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1739256791; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3RV3fhgTUiFE5VWNVLFbOVq1Uvf+BwjLKdZ/zyjmf0I=; b=Q2h4rqakGU5/WcMnFYZmntvJM+pZ32O5QvbGJjNwHAGAz4B5MW0EHIinv90QUCZeOJ3z17 /NTCADvZN09+8K0lyXOYbnyOleS2ksX4LmZNKA9LX/1UnJ5rnmVZSNutDg2bfnU7xtyama zO0osD7C+03MCT8moRGLmkwCJEGB3+AgmJzNUslC5FxbOpSoY2hbLk6qs4dCKsOWzENvUc qbJtfM8cFcI3BFmI67mSrV9yH76uZZA4Fq2QXdCoyOmU1Ae4gJn7CjojLsBcAKXy+54dsm e2j0y6nwrHKTilkzkirrt0YI++2ULVUIecxCwT8LUsej8w9wugaZLtTgVGMp6A== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 15/16] nvmem: microchip-otpc: Enable necessary clocks Date: Tue, 11 Feb 2025 07:53:03 +0100 Message-Id: <20250211065304.5019-3-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250211065304.5019-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> <20250211065304.5019-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Without enabling the main rc clock, initializing the packet list leads to a read timeout on the first packet, at least on sam9x60. According to SAM9X60 datasheet (DS60001579G) section "23.4 Product Dependencies" the clock must be enabled for reading and writing. Tested on sam9x60-curiosity board. Link: https://lore.kernel.org/linux-clk/ec34efc2-2051-4b8a-b5d8-6e2fd5e08c28@microchip.com/T/#u Signed-off-by: Alexander Dahl --- Notes: v2: - Rewrite to enable _all_ clocks defined in dts drivers/nvmem/microchip-otpc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c index d39f2d57e5f5e..2c524c163b7e2 100644 --- a/drivers/nvmem/microchip-otpc.c +++ b/drivers/nvmem/microchip-otpc.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -241,6 +242,7 @@ static struct nvmem_config mchp_nvmem_config = { static int mchp_otpc_probe(struct platform_device *pdev) { struct nvmem_device *nvmem; + struct clk_bulk_data *clks; struct mchp_otpc *otpc; u32 size; int ret; @@ -253,6 +255,11 @@ static int mchp_otpc_probe(struct platform_device *pdev) if (IS_ERR(otpc->base)) return PTR_ERR(otpc->base); + ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clks); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Error getting clocks!\n"); + otpc->dev = &pdev->dev; ret = mchp_otpc_init_packets_list(otpc, &size); if (ret) From patchwork Tue Feb 11 06:53:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13970199 Received: from mail.thorsis.com (mail.thorsis.com [217.92.40.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E7531E9B33; Tue, 11 Feb 2025 06:53:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.92.40.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256796; cv=none; b=s0ZT9JDDYYO+AIQ2iJwYImiznTVrdBpNxKrIFx8RNxkWTXXYqBD0vnG76vI010KBOJpXLZ6ri2o8p5uV0YG2IVkCPuuPPltWHZK0R7bxJ9iuByoBFOonrV5Msri7qC7h8ct0PrZe7kK+0cx14BlS9fEG9xW2b4QLt1qOzdz+IbI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739256796; c=relaxed/simple; bh=rE7L1ARhYuOgF0kVNeX4hwMhJfIOtDWsfQqGVqOGvGg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EZCs3k7Myv3eaApc/18yTZAjN4pgUyqsuavt/V8WjQLCuZmcB/3n84/bcwa+JUDhJjUdQ4fGBrW//whKRSqVhsPmnoeKuyeU5jUnwZ/ufVfpISM1EsqQa9NsjigDzRa/a/0tODgdF5emqTuCjK++OHEfWqAe3YGf82mp1jPRinw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com; spf=pass smtp.mailfrom=thorsis.com; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b=YNAtyCCX; arc=none smtp.client-ip=217.92.40.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=thorsis.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thorsis.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thorsis.com header.i=@thorsis.com header.b="YNAtyCCX" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id BE84C1487190; Tue, 11 Feb 2025 07:53:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1739256792; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bj/uk16+Hrn66Q2o4G0o90gz6ZpVpof9duaSUY2Gbv8=; b=YNAtyCCXg1vLyvrVQqozWuySt4vzLUl66EK6oatEYw1HPn3UGlnXwRZq3NHC/YdTU6/SHD UDYa0wFe52ZKgiK1+7LIuuMlRXqjPUzHLVCjTOdQK9aSuaGlz6aa55NN21km6ljY4P79CD e/UECLUtBSz+hFJXjZcs46tSut3UHgnPIRF+1mHHvm1T+CaWP7yqGZqpNQLZ7yGqAM6Btq 2ujDMGC3LfuwNhElwVaxGc2BB/QuGt5QZ7r6nih1UGq4CizXCn77rglommIxkdUXeqbaAN +UIU8wsnRGQAjYT7BIIUJn2X0p7fGUVadrfXlhnK67pkBcvhI5cJ3kOut0L8lg== From: Alexander Dahl To: Claudiu Beznea Cc: Nicolas Ferre , Ryan Wanner , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 16/16] nvmem: microchip-otpc: Expose UID registers as 2nd nvmem device Date: Tue, 11 Feb 2025 07:53:04 +0100 Message-Id: <20250211065304.5019-4-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250211065304.5019-1-ada@thorsis.com> References: <20250210164506.495747-1-ada@thorsis.com> <20250211065304.5019-1-ada@thorsis.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 For SAM9X60 the Product UID x Register containing the Unique Product ID is part of the OTPC registers. We have everything at hand here to just create a trivial nvmem device for those. Signed-off-by: Alexander Dahl --- Notes: v2: - Use dev_err_probe() for error reporting (thanks Claudiu) - Move required register definition over here from removed patch drivers/nvmem/microchip-otpc.c | 38 +++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c index 2c524c163b7e2..8353a117769a8 100644 --- a/drivers/nvmem/microchip-otpc.c +++ b/drivers/nvmem/microchip-otpc.c @@ -25,10 +25,14 @@ #define MCHP_OTPC_HR (0x20) #define MCHP_OTPC_HR_SIZE GENMASK(15, 8) #define MCHP_OTPC_DR (0x24) +#define MCHP_OTPC_UID0R (0x60) #define MCHP_OTPC_NAME "mchp-otpc" #define MCHP_OTPC_SIZE (11 * 1024) +#define MCHP_OTPC_UID_NAME "mchp-uid" +#define MCHP_OTPC_UID_SIZE 16 + /** * struct mchp_otpc - OTPC private data structure * @base: base address @@ -230,6 +234,16 @@ static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size) return 0; } +static int mchp_otpc_uid_read(void *priv, unsigned int offset, + void *val, size_t bytes) +{ + struct mchp_otpc *otpc = priv; + + memcpy_fromio(val, otpc->base + MCHP_OTPC_UID0R + offset, bytes); + + return 0; +} + static struct nvmem_config mchp_nvmem_config = { .name = MCHP_OTPC_NAME, .type = NVMEM_TYPE_OTP, @@ -239,6 +253,15 @@ static struct nvmem_config mchp_nvmem_config = { .reg_read = mchp_otpc_read, }; +static struct nvmem_config mchp_otpc_uid_nvmem_config = { + .name = MCHP_OTPC_UID_NAME, + .read_only = true, + .word_size = 4, + .stride = 4, + .size = MCHP_OTPC_UID_SIZE, + .reg_read = mchp_otpc_uid_read, +}; + static int mchp_otpc_probe(struct platform_device *pdev) { struct nvmem_device *nvmem; @@ -270,8 +293,21 @@ static int mchp_otpc_probe(struct platform_device *pdev) mchp_nvmem_config.size = size; mchp_nvmem_config.priv = otpc; nvmem = devm_nvmem_register(&pdev->dev, &mchp_nvmem_config); + if (IS_ERR(nvmem)) { + return dev_err_probe(&pdev->dev, PTR_ERR(nvmem), + "Error registering OTP as nvmem device\n"); + } - return PTR_ERR_OR_ZERO(nvmem); + mchp_otpc_uid_nvmem_config.dev = otpc->dev; + mchp_otpc_uid_nvmem_config.priv = otpc; + + nvmem = devm_nvmem_register(&pdev->dev, &mchp_otpc_uid_nvmem_config); + if (IS_ERR(nvmem)) { + return dev_err_probe(&pdev->dev, PTR_ERR(nvmem), + "Error registering UIDxR as nvmem device\n"); + } + + return 0; } static const struct of_device_id __maybe_unused mchp_otpc_ids[] = {