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Tue, 11 Feb 2025 10:29:54 +0800 X-QQ-mid: xmsmtpt1739240994ts1ern8k5 Message-ID: X-QQ-XMAILINFO: N7h1OCCDntujn8zIAKkUixZyrzF1c0t5ZmDIrdNwCTJtUPKHFEmt9e0gc2FgR0 mMWeeFnKy/a4aUIo/rpJDpJ6SY0wtec1J5MS8eQwtEa3YVcY8jLNMa9250s5hJh8q2GeyH9Ly3mq OTjH4/qFlZhPPAFWvBJEpQ65MRW/Cd3EXCj/HnesqzbMyLjwYfR1re3CA1q5oF00yClAiTDCAq93 uzZRTGp9k97DyCuidfDsHfkE4KCi5QAqD/jK2bgjXz5qzZIdE+gvfca8NS/a9PT6iNL+WQQW+GuE a/bQhd/OIclYthoeWmAtdxMaAzRqg03jCUs0WHFTc3lS+USxYSUtdsk/O5KnHioFskTH4y3/vyoy /rTMC7j/PJiMqKJNzDE2IJEcrC5urLsd0zry0qw4ZmcNDIivx8KgGn8dTfmTHWQctsIpLZ3SwdJN d0smXgOzmIm3FwMU93YLACBfni2fBi2GA7YTQcoswQAf/JOlAALE5KEBO7MPVxoZS6PhBwnf7ZtR XqFfkYyBkiEHgnjW33cBIF75mVwnnY/qojK+SDNXRuzRsB5xpLJgajwy7a8E8k4TNuqPOEWxAQ8K n+f1MWODzFsDYhGk27nUDdfj3jxlXpFlReK+kB+FcmdoGgWDDcGPvh2u73p8M8DBTWGhPfe1eQ+w PSsPaO5hfgdg/9K6Hg6XnNnEBqJVoPt1QIBUdEkCsK7parRXaNPrcR7e1VmVlSn8g/km0GYb+Aaw Vri/jRHfIeF23ArFugzbEX2shqmyhWWSJK2MbjMZr4MfI3/6ucHf+wZttgkUFy9cNOK6Z1f9kmVg oBpCCCahFSAeS7kQhJHVz0lkz4MCm9lf3T+4K4O2tbrOVtTYfopwVVd4wUKzr04eUc+iWfnnqTBP QnsMNVFL7UNcFRM9FNpJKzlY1cMPfpxt6vRq/nC7al/jOxGzMw1rsiRzOWSnuTnrRFniI6qKJk X-QQ-XMRINFO: M/715EihBoGSf6IYSX1iLFg= From: xiaopeitux@foxmail.com To: vkoul@kernel.org, aford173@gmail.com, kishon@kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Pei Xiao Subject: [PATCH V6] phy: freescale: fsl-samsung-hdmi: Limit PLL lock detection clock divider to valid range Date: Tue, 11 Feb 2025 10:29:48 +0800 X-OQ-MSGID: <48bc37daf1d703f28a5216926cb4de5c5e89e904.1739240824.git.xiaopei01@kylinos.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250210_183026_718248_F3C177F4 X-CRM114-Status: GOOD ( 11.92 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: Pei Xiao FIELD_PREP() checks that a value fits into the available bitfield, but the index div equals to 4,is out of range. which gcc complains about: In function ‘fsl_samsung_hdmi_phy_configure_pll_lock_det’, inlined from ‘fsl_samsung_hdmi_phy_configure’ at drivers/phy/freescale/phy-fsl-samsung-hdmi.c :470:2: ././include/linux/compiler_types.h:542:38: error: call to ‘__compiletime_assert_538’ declared with attribute error: FIELD_PREP: value too large for the field 542 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^ ././include/linux/compiler_types.h:523:4: note: in definition of macro ‘__compiletime_assert’ 523 | prefix ## suffix(); | ^~~~~~ ././include/linux/compiler_types.h:542:2: note: in expansion of macro ‘_compiletime_assert’ 542 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) REG12_CK_DIV_MASK only two bit, limit div to range 0~3, so build error will fix. Fixes: d567679f2b6a ("phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation") Signed-off-by: Pei Xiao Changlog: --- V6: modify the title from Vinod V5: add return ret from Geert suggestion V4: change to use if statement V3: change to use do-while V2: change to use logical AND --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index 5eac70a1e858..6817ceabaab4 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -325,7 +325,7 @@ to_fsl_samsung_hdmi_phy(struct clk_hw *hw) return container_of(hw, struct fsl_samsung_hdmi_phy, hw); } -static void +static int fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, const struct phy_config *cfg) { @@ -341,6 +341,9 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, break; } + if (unlikely(div == 4)) + return -EINVAL; + writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12)); /* @@ -364,6 +367,8 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, FIELD_PREP(REG14_RP_CODE_MASK, 2) | FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8), phy->regs + PHY_REG(14)); + + return 0; } static unsigned long fsl_samsung_hdmi_phy_find_pms(unsigned long fout, u8 *p, u16 *m, u8 *s) @@ -467,7 +472,11 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21)); - fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); + ret = fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); + if (ret) { + dev_err(phy->dev, "pixclock too large\n"); + return ret; + } writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));