From patchwork Wed Feb 12 07:57:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1306CC0219E for ; Wed, 12 Feb 2025 07:57:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6ACEC10E7DA; Wed, 12 Feb 2025 07:57:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NtKPE1AI"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 583B610E26D; Wed, 12 Feb 2025 07:57:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739347073; x=1770883073; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gK6jFSk8f9KF9yFnrM9F7/9mc7AYHu6iz7U1J2AKbBc=; b=NtKPE1AIshO9ouF1HjBta29ckhyzPJnX6fpdC1dSkBrOhrl082ja8xBn mWEP6izj5Dpb/m2nFW2HEagBCFixsw9SjuLDZKM9iNH+upyaS3rzDr9jM +AHG7lO8SLJeVv6i5sctgstHTCPZ3LESj9a6u8/PXQSxk6Q2nsaluxtml uwhIGu38dHlzz8HEWs/FaPgc68s9tdErxklQVTtLYQZe7CzmVHTdeH3GT vdx2L3tEawV2HobKxrKFIVH3NzWaX0c1HVZAlvgaHPPj2psVosZClgRzz JdHSUVUEl0wHp61D099A0nL0nMbAnOYJ3ZJyz9bN0JXJ6JfzSQ+RMu7CY Q==; X-CSE-ConnectionGUID: jjM3x/IVR9e9qio2u3DGvA== X-CSE-MsgGUID: epAk5tqvQlSFG/7T/pGOyw== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="50973626" X-IronPort-AV: E=Sophos;i="6.13,279,1732608000"; d="scan'208";a="50973626" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:57:53 -0800 X-CSE-ConnectionGUID: XC8mTY+RTfSzfvB40HxdmQ== X-CSE-MsgGUID: tw1veh6hQpWRxHsD//euuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="116836870" Received: from dalessan-mobl3.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:57:52 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v7 01/13] drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update Date: Wed, 12 Feb 2025 09:57:29 +0200 Message-ID: <20250212075742.995022-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We are preparing for a change where only frontbuffer flush will use single full frame bit of a new register (SFF_CTL) available on LunarLake onwards. It shouldn't be necessary to have SFF bit set if CFF bit is set in PSR2_MAN_TRK_CTL -> removing setting it on all platforms as there is not reason to have it different on older platforms. v2: commit message improved Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 861e50ceef85..64e03d19cad5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2395,7 +2395,6 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, val |= man_trk_ctl_partial_frame_bit_get(display); if (full_update) { - val |= man_trk_ctl_single_full_frame_bit_get(display); val |= man_trk_ctl_continuos_full_frame(display); goto exit; } From patchwork Wed Feb 12 07:57:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 025C8C021A6 for ; Wed, 12 Feb 2025 07:57:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E58510E7DF; Wed, 12 Feb 2025 07:57:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="YDMiib0D"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 05E2F10E7DC; Wed, 12 Feb 2025 07:57:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739347075; x=1770883075; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Fb2VzKoGy5Zu6h7c81y/zHG24YywWQ3zgPH5xp4uFB4=; b=YDMiib0DkoSBPO7yJRZ4HictPywQh8iCm2j0nWg6OZfOp2KOKNPhgTZo PP/zlfH5hTZhtRj1Kt8kX9kpAVdKNfqwXAsQLQ0IBCOgKpwc7c65CFOPk yG0Twi0UmardBObqAruP8fdyrh5RB042zvHojUietxaEeud0m38bGNChy UJWh0aomVclTUNQGgjKY7XUOLADuF6+9lJ277K8FZZakeC4mG1GGUd+2N fiTkewVcxDtO5BnoW+Wesx/tL+/myPhw+XbqLzb3L2pVoU5AeEaQj/87H Pqqqu15Quo4xsslURrf3eVYPaBGooi6cibCht9hW3lsTtO/mQo6bPqFl9 w==; X-CSE-ConnectionGUID: SJo//tIqQuGE3ql3srqiRA== X-CSE-MsgGUID: 57ZpuR2hRKCCqHUW/V99EQ== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="50973627" X-IronPort-AV: E=Sophos;i="6.13,279,1732608000"; d="scan'208";a="50973627" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:57:54 -0800 X-CSE-ConnectionGUID: ErqJita9TG2jYN3fk5GZKw== X-CSE-MsgGUID: kLuNHscVS5SCt1rNVMcZtg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="116836877" Received: from dalessan-mobl3.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:57:53 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , Animesh Manna Subject: [PATCH v7 02/13] drm/i915/psr: Rename psr_force_hw_tracking_exit as intel_psr_force_update Date: Wed, 12 Feb 2025 09:57:30 +0200 Message-ID: <20250212075742.995022-3-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" psr_force_hw_tracking_exit is misleading name as it is used for PSR1, PSR2 HW tracking and PSR2 selective fetch. Due to this rename it as intel_psr_force_update. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 64e03d19cad5..16d125f51ab0 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2324,7 +2324,7 @@ static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; } -static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) +static void intel_psr_force_update(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; @@ -2869,7 +2869,7 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state, /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ if (crtc_state->crc_enabled && psr->enabled) - psr_force_hw_tracking_exit(intel_dp); + intel_psr_force_update(intel_dp); /* * Clear possible busy bits in case we have @@ -3266,10 +3266,10 @@ static void _psr_flush_handle(struct intel_dp *intel_dp) * continuous full frame is disabled, only a single full * frame is required */ - psr_force_hw_tracking_exit(intel_dp); + intel_psr_force_update(intel_dp); } } else { - psr_force_hw_tracking_exit(intel_dp); + intel_psr_force_update(intel_dp); if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); From patchwork Wed Feb 12 07:57:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42DEAC021A4 for ; Wed, 12 Feb 2025 07:57:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CE55810E7E1; Wed, 12 Feb 2025 07:57:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="A5aZjN2U"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id A7E7310E7E1; Wed, 12 Feb 2025 07:57:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739347076; x=1770883076; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xsPagkw3+A/zBXulh63VOHqd4wMclpy8ITLRYyGQ5gY=; b=A5aZjN2Uyjx3oR/yfh2AcgaTVBB9urZbXnHS4qTTRsT+4yWQEggKYeAN 7xNbwsuv4ZwLkFmEK5G3YsSM5ovkC7kzlt4GU7bugJjYAHnjdBapb/Tby B8gBiSNUg5e3eeM3bhN2ZvbOJwFaA9LD/+WoXqMDsPTR07+YYM10pOakn l3FzZU8yjP31bxayW9sG2ZIuleO1lG62i7pxoKS5o3jHmIlNRDdBCTci9 ieO+pPLW+bHQjdMaho0625uZELqDB/KzPFgQ4Iey4jmN6oZ+62D+E4BST xvp1gsXCuGfHQRrTRNfZeD7N/chxDmMsz+1rq8gsI5XQUEzroghc8pzBc Q==; X-CSE-ConnectionGUID: 1ovnd1V/QTOtkGTFNIC/IQ== X-CSE-MsgGUID: 8I5rWvA0Se6nZ4QI+9sJcA== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="50973628" X-IronPort-AV: E=Sophos;i="6.13,279,1732608000"; d="scan'208";a="50973628" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:57:56 -0800 X-CSE-ConnectionGUID: WJrpe4RAS2WDlRzMN2UYUw== X-CSE-MsgGUID: B4m1mooKTd2ShKoRGUeK0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="116836882" Received: from dalessan-mobl3.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:57:55 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , Animesh Manna Subject: [PATCH v7 03/13] drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update Date: Wed, 12 Feb 2025 09:57:31 +0200 Message-ID: <20250212075742.995022-4-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This is a clean-up and a preparation for adding own SFF and CFF registers for LunarLake onwards. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 88 +++++++++--------------- 1 file changed, 31 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 16d125f51ab0..c0ba74c16d16 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2327,15 +2327,6 @@ static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) static void intel_psr_force_update(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - - if (intel_dp->psr.psr2_sel_fetch_enabled) - intel_de_write(display, - PSR2_MAN_TRK_CTL(display, cpu_transcoder), - man_trk_ctl_enable_bit_get(display) | - man_trk_ctl_partial_frame_bit_get(display) | - man_trk_ctl_single_full_frame_bit_get(display) | - man_trk_ctl_continuos_full_frame(display)); /* * Display WA #0884: skl+ @@ -3131,31 +3122,31 @@ static void intel_psr_work(struct work_struct *work) mutex_unlock(&intel_dp->psr.lock); } -static void _psr_invalidate_handle(struct intel_dp *intel_dp) +static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - if (intel_dp->psr.psr2_sel_fetch_enabled) { - u32 val; + if (!intel_dp->psr.psr2_sel_fetch_enabled) + return; - if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { - /* Send one update otherwise lag is observed in screen */ - intel_de_write(display, - CURSURFLIVE(display, intel_dp->psr.pipe), - 0); - return; + intel_de_write(display, + PSR2_MAN_TRK_CTL(display, cpu_transcoder), + man_trk_ctl_enable_bit_get(display) | + man_trk_ctl_partial_frame_bit_get(display) | + man_trk_ctl_single_full_frame_bit_get(display) | + man_trk_ctl_continuos_full_frame(display)); +} + +static void _psr_invalidate_handle(struct intel_dp *intel_dp) +{ + if (intel_dp->psr.psr2_sel_fetch_enabled) { + if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) { + intel_dp->psr.psr2_sel_fetch_cff_enabled = true; + intel_psr_configure_full_frame_update(intel_dp); } - val = man_trk_ctl_enable_bit_get(display) | - man_trk_ctl_partial_frame_bit_get(display) | - man_trk_ctl_continuos_full_frame(display); - intel_de_write(display, - PSR2_MAN_TRK_CTL(display, cpu_transcoder), - val); - intel_de_write(display, - CURSURFLIVE(display, intel_dp->psr.pipe), 0); - intel_dp->psr.psr2_sel_fetch_cff_enabled = true; + intel_psr_force_update(intel_dp); } else { intel_psr_exit(intel_dp); } @@ -3236,44 +3227,27 @@ static void _psr_flush_handle(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); struct drm_i915_private *dev_priv = to_i915(display->drm); - enum transcoder cpu_transcoder = intel_dp->psr.transcoder; if (intel_dp->psr.psr2_sel_fetch_enabled) { if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { /* can we turn CFF off? */ - if (intel_dp->psr.busy_frontbuffer_bits == 0) { - u32 val = man_trk_ctl_enable_bit_get(display) | - man_trk_ctl_partial_frame_bit_get(display) | - man_trk_ctl_single_full_frame_bit_get(display) | - man_trk_ctl_continuos_full_frame(display); - - /* - * Set psr2_sel_fetch_cff_enabled as false to allow selective - * updates. Still keep cff bit enabled as we don't have proper - * SU configuration in case update is sent for any reason after - * sff bit gets cleared by the HW on next vblank. - */ - intel_de_write(display, - PSR2_MAN_TRK_CTL(display, cpu_transcoder), - val); - intel_de_write(display, - CURSURFLIVE(display, intel_dp->psr.pipe), - 0); + if (intel_dp->psr.busy_frontbuffer_bits == 0) intel_dp->psr.psr2_sel_fetch_cff_enabled = false; - } - } else { - /* - * continuous full frame is disabled, only a single full - * frame is required - */ - intel_psr_force_update(intel_dp); } - } else { - intel_psr_force_update(intel_dp); - if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) - queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); + /* + * Still keep cff bit enabled as we don't have proper SU + * configuration in case update is sent for any reason after + * sff bit gets cleared by the HW on next vblank. + */ + intel_psr_configure_full_frame_update(intel_dp); } + + intel_psr_force_update(intel_dp); + + if (!intel_dp->psr.psr2_sel_fetch_enabled && !intel_dp->psr.active && + !intel_dp->psr.busy_frontbuffer_bits) + queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); } /** From patchwork Wed Feb 12 07:57:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39C62C021A6 for ; Wed, 12 Feb 2025 07:58:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7A32210E7E8; Wed, 12 Feb 2025 07:58:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bgj10j/v"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 593B210E7E3; Wed, 12 Feb 2025 07:57:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739347078; x=1770883078; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SAGwH6LOxlieeoGWiBd3rvz4LM8WkVxTSI9Ts9Hlin0=; b=bgj10j/vq8g3P4OoB1K6n77dfj5xyS3AcZzsezZ4b4KyVzdM1cVO+DZ2 +et8sAauyGuJ7tVcLP4SvwScrF2GJtUq5e2Evd175rtv1t5hIRo18MXFy 1GI5rqGFI4cDotNyd/1oVh5DGxAyJbZr9fu+v25pWYE1x1W0+NCo0O3QH 01wKOhGJKqOpzDGArI02FsGRjC0iN4+YLAk2NC8LOtVQWEbm9h0fjEaiI h7i4LKa1nO0hGJ+hin13OIc18uZbqFU4yiQoSUgRezDY0Ve/txLHdGc9C QarwB82EMXgv48IPQr+8grDngKvoqD4dfcSj6aAdPXK67Bvro2qoUqkzP Q==; X-CSE-ConnectionGUID: +kNxonf6Sbqr3mFQL/Zltw== X-CSE-MsgGUID: D8HRWo22RX6DFXzG4K/5mA== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="50973629" X-IronPort-AV: E=Sophos;i="6.13,279,1732608000"; d="scan'208";a="50973629" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:57:58 -0800 X-CSE-ConnectionGUID: eviXjWXvQw2Mje18ky7VsA== X-CSE-MsgGUID: AhwrA86AQwunN59nExDUhQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="116836888" Received: from dalessan-mobl3.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:57:56 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , Animesh Manna Subject: [PATCH v7 04/13] drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers Date: Wed, 12 Feb 2025 09:57:32 +0200 Message-ID: <20250212075742.995022-5-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add register definitions for SFF_CTL and CFF_CTL registers. Name them as LNL_SFF_CTL and LNL_CFF_CTL. v2: use _MMIO_TRANS instead of _MMIO_TRANS2 Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 9ad7611506e8..795e6b9cc575 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -251,6 +251,16 @@ #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) +#define _LNL_SFF_CTL_A 0x60918 +#define _LNL_SFF_CTL_B 0x61918 +#define LNL_SFF_CTL(tran) _MMIO_TRANS(tran, _LNL_SFF_CTL_A, _LNL_SFF_CTL_B) +#define LNL_SFF_CTL_SF_SINGLE_FULL_FRAME REG_BIT(1) + +#define _LNL_CFF_CTL_A 0x6091c +#define _LNL_CFF_CTL_B 0x6191c +#define LNL_CFF_CTL(tran) _MMIO_TRANS(tran, _LNL_CFF_CTL_A, _LNL_CFF_CTL_B) +#define LNL_CFF_CTL_SF_CONTINUOUS_FULL_FRAME REG_BIT(1) + /* PSR2 Early transport */ #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074 #define _PIPE_SRCSZ_ERLY_TPT_B 0x71074 From patchwork Wed Feb 12 07:57:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97978C021A4 for ; Wed, 12 Feb 2025 07:58:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 22C7910E7E5; Wed, 12 Feb 2025 07:58:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="inlaMZAs"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1A3AE10E7E4; Wed, 12 Feb 2025 07:58:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739347080; x=1770883080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hBrBx5tbiagy+J6k5eHmc1wox0wWnEsKxte8bMohGbs=; b=inlaMZAsnnd7u28pViWCREwxBeTNHsz6KqdCYadIXWq7SSdAXNpcNLPQ RXwzNj8kb8TO5po47B/CEx/oWsN79cKIQr47eV+l3wtI3zA29IdvJtKGs 8mUiO5SkyxHjCrQ72qLhi2TUWHjNKw6zimAQW2nCRF625v1M84Qe/QuP6 1XocJ8CMLQ8rmBZ6TEQoocEnKDxK+M/fWmQe6u7xCn5Z4LkBBEZUUjbKm ty18z+8+w0GRLqZjWad9+sDV5z0h43i0PoLm+/FN2s1Si5xlaYINtBdSO vut/2SLnuyNYnQwfMzoJnw2UblG44T2j0NYW1qEqUHzxS6G9reCyj0Nag A==; X-CSE-ConnectionGUID: 3FbSFt6ITMOTOxZ+DEbh6w== X-CSE-MsgGUID: RQDuc5jtS/20kAkQO4IZkw== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="50973631" X-IronPort-AV: E=Sophos;i="6.13,279,1732608000"; d="scan'208";a="50973631" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:00 -0800 X-CSE-ConnectionGUID: XUFloNpSSKyc9Q6Db+k+ig== X-CSE-MsgGUID: M70XuO7YQnGAowYz3SHEcg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="116836895" Received: from dalessan-mobl3.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:57:58 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , Animesh Manna Subject: [PATCH v7 05/13] drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards Date: Wed, 12 Feb 2025 09:57:33 +0200 Message-ID: <20250212075742.995022-6-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In LunarLake we have SFF_CTL register which contains SFF bit ored with respective SFF bit in PSR2_MAN_TRK_CTL register. Use this register instead of the bit in PSR2_MAN_TRK_CTL on frontbuffer tracking callbacks. This helps us avoiding taking psr mutex when performing atomic commit. We don't need to set the CFF bit as selective update configuration in PSR2_MAN_TRL_CTL is not overwritten anymore. I.e. we have valid configuration in PSR2_MAN_TRK_CTL and in plane SEL_FETCH_* registers when SFF bit gets cleared by the HW in case something triggers "frame change" event after SFF bit is cleared. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index c0ba74c16d16..b5292f68d100 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2359,7 +2359,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st struct intel_dp *intel_dp = enc_to_intel_dp(encoder); lockdep_assert_held(&intel_dp->psr.lock); - if (intel_dp->psr.psr2_sel_fetch_cff_enabled) + if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled) return; break; } @@ -3130,12 +3130,16 @@ static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp) if (!intel_dp->psr.psr2_sel_fetch_enabled) return; - intel_de_write(display, - PSR2_MAN_TRK_CTL(display, cpu_transcoder), - man_trk_ctl_enable_bit_get(display) | - man_trk_ctl_partial_frame_bit_get(display) | - man_trk_ctl_single_full_frame_bit_get(display) | - man_trk_ctl_continuos_full_frame(display)); + if (DISPLAY_VER(display) >= 20) + intel_de_write(display, LNL_SFF_CTL(cpu_transcoder), + LNL_SFF_CTL_SF_SINGLE_FULL_FRAME); + else + intel_de_write(display, + PSR2_MAN_TRK_CTL(display, cpu_transcoder), + man_trk_ctl_enable_bit_get(display) | + man_trk_ctl_partial_frame_bit_get(display) | + man_trk_ctl_single_full_frame_bit_get(display) | + man_trk_ctl_continuos_full_frame(display)); } static void _psr_invalidate_handle(struct intel_dp *intel_dp) @@ -3239,6 +3243,10 @@ static void _psr_flush_handle(struct intel_dp *intel_dp) * Still keep cff bit enabled as we don't have proper SU * configuration in case update is sent for any reason after * sff bit gets cleared by the HW on next vblank. + * + * NOTE: Setting cff bit is not needed for LunarLake onwards as + * we have own register for SFF bit and we are not overwriting + * existing SU configuration */ intel_psr_configure_full_frame_update(intel_dp); } From patchwork Wed Feb 12 07:57:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EFE20C021A7 for ; Wed, 12 Feb 2025 07:58:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6ABBD10E7EA; Wed, 12 Feb 2025 07:58:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NP5qwGnC"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id C69B010E7EA; Wed, 12 Feb 2025 07:58:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739347081; x=1770883081; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nKlrvwkvZhMZ6V2RaPMJC1tIy76lwQlAuu3q3I5PtiM=; b=NP5qwGnCctULXbkEmnHRWyU5u7KjWUeT5I+3tesd1uq4q7I9qaXPZyJa 1+Krk5JlIhmjIJn8W3SFnURZAPv0PNx494/fEXJxl0IwVm6pP3W2jRp1J 7RzBDK5RJqSigFLZdEynJSCgjO1hpkHDrIYpjpReyCGWcz5x6ku/RWRo9 ZJH5daj0SOyoXmbMnW3eoIpWreCTjq5+3bM+1APPY9Cu/fq2CzhunLsIi o4TH6DelVNrwDtFmJq1f6Ajmp5ag3eDOmcv+2kPX1m1NtC7lU+yaU7xJW E2LDqkcEtOG8tJAIgvPxVqGabJ6KDJnqLMS/3fo7TmB1N7fRrGbwy9PAB Q==; X-CSE-ConnectionGUID: SB/4JeY/TC6cPToPLmw9gw== X-CSE-MsgGUID: YO+j3a0dTYummQwFuWFRww== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="50973632" X-IronPort-AV: E=Sophos;i="6.13,279,1732608000"; d="scan'208";a="50973632" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:01 -0800 X-CSE-ConnectionGUID: thp/3LCtRl23E7TdfVjmMQ== X-CSE-MsgGUID: EJIqqWDRRve40CCNAXiGxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="116836904" Received: from dalessan-mobl3.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:00 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , Animesh Manna Subject: [PATCH v7 06/13] drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB Date: Wed, 12 Feb 2025 09:57:34 +0200 Message-ID: <20250212075742.995022-7-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Allow writing PSR2_MAN_TRK_CTL using DSB by using intel_de_write_dsb. Do not check intel_dp->psr.lock being held when using DSB. This assertion doesn't make sense as in case of using DSB the actual write happens later and we are not taking intel_dp->psr.lock mutex over dsb commit. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++++------ drivers/gpu/drm/i915/display/intel_psr.h | 4 +++- 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2d7ac53bb924..a1e0fa304d22 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7156,7 +7156,7 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state, intel_pipe_fastset(old_crtc_state, new_crtc_state); } - intel_psr2_program_trans_man_trk_ctl(new_crtc_state); + intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state); intel_atomic_update_watermarks(state, crtc); } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b5292f68d100..c805ff82e700 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2344,7 +2344,8 @@ static void intel_psr_force_update(struct intel_dp *intel_dp) intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0); } -void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) +void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -2358,20 +2359,23 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st crtc_state->uapi.encoder_mask) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - lockdep_assert_held(&intel_dp->psr.lock); + if (!dsb) + lockdep_assert_held(&intel_dp->psr.lock); + if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled) return; break; } - intel_de_write(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), - crtc_state->psr2_man_track_ctl); + intel_de_write_dsb(display, dsb, + PSR2_MAN_TRK_CTL(display, cpu_transcoder), + crtc_state->psr2_man_track_ctl); if (!crtc_state->enable_psr2_su_region_et) return; - intel_de_write(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), - crtc_state->pipe_srcsz_early_tpt); + intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), + crtc_state->pipe_srcsz_early_tpt); } static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 5f1671d02d76..e6eba6633a92 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -17,6 +17,7 @@ struct intel_crtc; struct intel_crtc_state; struct intel_display; struct intel_dp; +struct intel_dsb; struct intel_encoder; struct intel_plane; struct intel_plane_state; @@ -54,7 +55,8 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat bool intel_psr_enabled(struct intel_dp *intel_dp); int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, struct intel_crtc *crtc); -void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state); +void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state); void intel_psr_pause(struct intel_dp *intel_dp); void intel_psr_resume(struct intel_dp *intel_dp); bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state); From patchwork Wed Feb 12 07:57:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971326 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54F36C02198 for ; Wed, 12 Feb 2025 07:58:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E28C110E7EB; Wed, 12 Feb 2025 07:58:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; 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([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:02 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , Animesh Manna Subject: [PATCH v7 07/13] drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use Date: Wed, 12 Feb 2025 09:57:35 +0200 Message-ID: <20250212075742.995022-8-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Do needed changes to handle PSR2_MAN_TRK_CTL correctly when DSB is in use: 1. Write PSR2_MAN_TRK_CTL in commit_pipe_pre_planes only when not using DSB. 2. Add PSR2_MAN_TRK_CTL writing into DSB commit in intel_atomic_dsb_finish. Taking PSR lock over DSB commit is not needed because PSR2_MAN_TRK_CTL is now written only by DSB. v2: remove checking use_dsb Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a1e0fa304d22..cab6852dd9c2 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7745,6 +7745,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, new_crtc_state); bdw_set_pipe_misc(new_crtc_state->dsb_commit, new_crtc_state); + intel_psr2_program_trans_man_trk_ctl(new_crtc_state->dsb_commit, + new_crtc_state); intel_crtc_planes_update_arm(new_crtc_state->dsb_commit, state, crtc); From patchwork Wed Feb 12 07:57:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55EA9C021AA for ; Wed, 12 Feb 2025 07:58:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E621110E7EE; Wed, 12 Feb 2025 07:58:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="BUckBdsn"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5C81B10E7ED; Wed, 12 Feb 2025 07:58:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739347086; x=1770883086; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BwPxekFYUFvLbcrzCyGHNcqjb29642EXGTXHrEFhCF0=; b=BUckBdsnH6PvdkmEGkHHIs5Pkr6I/ogETUdeEWUt32eZ86BCRxedqhpz A9+Jd8gfKzZnovU6wHr4H1DkxzjldAotH1vAtsEOx9dMfWuwgguKL0ma4 yIilKfgKLym+RYBtI72f3+YQg0fyNubWEE/lJ4ylmLvEnEZXW4amzVsYx /kwydzgXbWJmM31v598uZ4N5bNVltnG6MT6RGELHefudS2zD57IhXzKLU I2eqFFJK+Tpc8CMh/rnYbqp6cT5zOZxh36ax8y5yliqrSjVPU+4zcrYPX 5qgLllUemnog2Y3xGZSWpelcPhR6mPFP7j1zGTpJBSWIyWd1J3V7JALNg g==; X-CSE-ConnectionGUID: rLtNoB/CRm62C2Z8XimMQA== X-CSE-MsgGUID: KUKfk2zpSHm/aN5uaM/pAg== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="50973637" X-IronPort-AV: E=Sophos;i="6.13,279,1732608000"; d="scan'208";a="50973637" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:06 -0800 X-CSE-ConnectionGUID: T0UdsAoIQfWBrpegz20kFw== X-CSE-MsgGUID: rqGHgNJHTbirRixqCzFpCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="116836922" Received: from dalessan-mobl3.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:05 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v7 08/13] drm/i915/display: Warn on use_dsb in non-dsb pipe update functions Date: Wed, 12 Feb 2025 09:57:37 +0200 Message-ID: <20250212075742.995022-10-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add drm_WARN_ON(use_dsb) into commit_pipe_{pre,post}_planes() and intel_pipe_update_{start,end}() as they are not supposed to get called on non-dsb updates. Signed-off-by: Jouni Högander Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_crtc.c | 4 ++++ drivers/gpu/drm/i915/display/intel_display.c | 6 +++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 89785da93603..eb089d76ba2a 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -522,6 +522,8 @@ void intel_pipe_update_start(struct intel_atomic_state *state, struct intel_vblank_evade_ctx evade; int scanline; + drm_WARN_ON(display->drm, new_crtc_state->use_dsb); + intel_psr_lock(new_crtc_state); if (new_crtc_state->do_async_flip) { @@ -660,6 +662,8 @@ void intel_pipe_update_end(struct intel_atomic_state *state, ktime_t end_vbl_time = ktime_get(); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + drm_WARN_ON(display->drm, new_crtc_state->use_dsb); + if (new_crtc_state->do_async_flip) goto out; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index cab6852dd9c2..79b8d2ad3b9c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7141,11 +7141,13 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); bool modeset = intel_crtc_needs_modeset(new_crtc_state); + drm_WARN_ON(&dev_priv->drm, new_crtc_state->use_dsb); + /* * During modesets pipe configuration was programmed as the * CRTC was enabled. */ - if (!modeset && !new_crtc_state->use_dsb) { + if (!modeset) { if (intel_crtc_needs_color_update(new_crtc_state)) intel_color_commit_arm(NULL, new_crtc_state); @@ -7168,6 +7170,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + drm_WARN_ON(&dev_priv->drm, new_crtc_state->use_dsb); + /* * Disable the scaler(s) after the plane(s) so that we don't * get a catastrophic underrun even if the two operations From patchwork Wed Feb 12 07:57:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1DBB1C0219E for ; Wed, 12 Feb 2025 07:58:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AD72F10E7F0; Wed, 12 Feb 2025 07:58:09 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="h8snHR78"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 19FED10E7DC; Wed, 12 Feb 2025 07:58:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739347088; x=1770883088; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TQeO2EsJFGCpBQjWma/PjUiCvB8zU7gbR+XAEc3U+M8=; b=h8snHR78as4fmqIrCI+POZY7WHJ2unjWXrK5uBoId8x3Iy+EHNSDilVG jEyeUgI0WySJ9xCrno/Wz7N3dMzXN5iZ4t4VxVtbfqgFi0j3bbzKSlifN aeorpo5UfXuUyDFuROn8hM6DKnhN+1TomwBsotBIE6hi2Gj119isaFhpx PJnLqJaM0YHM2P1xqvSi177a8x7gK4fiCfIf4XXtYRG6qb+GHGqOs6/zk IcgEFRyxdPboIntyEaFMPT/nkUDYx5dH22B5ZLadnbXofuwxCeFtwbHD/ +utuPSnoTu7j5XVUmQvF1yApVrPbjZ6/8NLV4KenE0TE9Ee7tCoZkZdKW g==; X-CSE-ConnectionGUID: uIFf7Ch1QyC0YzG3ElB8+w== X-CSE-MsgGUID: O3gVjvV1RfOqjKgpqL4Q9g== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="50973639" X-IronPort-AV: E=Sophos;i="6.13,279,1732608000"; d="scan'208";a="50973639" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:08 -0800 X-CSE-ConnectionGUID: G0EGiO6xR8Oqj/K9JkBG1Q== X-CSE-MsgGUID: DR0wTMAfRaGuA1Cr4kHiSQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="116836929" Received: from dalessan-mobl3.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:06 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= Subject: [PATCH v7 09/13] drm/i915/psr: Remove DSB_SKIP_WAITS_EN chicken bit Date: Wed, 12 Feb 2025 09:57:38 +0200 Message-ID: <20250212075742.995022-11-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We have different approach on how flip is considered being complete. We are waiting for vblank on DSB and generate interrupt when it happens and this interrupt is considered as indication of completion -> we definitely do not want to skip vblank wait. Also not skipping scanline wait shouldn't cause any problems if we are in DEEP_SLEEP PIPEDSL register is returning 0 -> evasion does nothing and if we are not in DEEP_SLEEP evasion works same way as without PSR. v2: add comment explaining why we are not setting DSB_SKIP_WAITS_EN Signed-off-by: Jouni Högander Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 2f2812c23972..30782ab0b908 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -164,17 +164,26 @@ static int dsb_scanline_to_hw(struct intel_atomic_state *state, return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal; } +/* + * Bspec suggests that we should always set DSB_SKIP_WAITS_EN. We have approach + * different from what is explained in Bspec on how flip is considered being + * complete. We are waiting for vblank in DSB and generate interrupt when it + * happens and this interrupt is considered as indication of completion -> we + * definitely do not want to skip vblank wait. We also have concern what comes + * to skipping vblank evasion. I.e. arming registers are latched before we have + * managed writing them. Due to these reasons we are not setting + * DSB_SKIP_WAITS_EN. + */ static u32 dsb_chicken(struct intel_atomic_state *state, struct intel_crtc *crtc) { if (pre_commit_is_vrr_active(state, crtc)) - return DSB_SKIP_WAITS_EN | - DSB_CTRL_WAIT_SAFE_WINDOW | + return DSB_CTRL_WAIT_SAFE_WINDOW | DSB_CTRL_NO_WAIT_VBLANK | DSB_INST_WAIT_SAFE_WINDOW | DSB_INST_NO_WAIT_VBLANK; else - return DSB_SKIP_WAITS_EN; + return 0; } static bool assert_dsb_has_room(struct intel_dsb *dsb) From patchwork Wed Feb 12 07:57:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971330 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18A22C021AC for ; Wed, 12 Feb 2025 07:58:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A1A5A10E7F1; Wed, 12 Feb 2025 07:58:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="oKh/LHpD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id A9CBF10E7EF; Wed, 12 Feb 2025 07:58:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739347089; x=1770883089; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SvTv8Kqt3NNCW0hdhs0iC5P76CS0srJhSNSVT8+pIME=; b=oKh/LHpDSgSnBAFW3ekOyOJeN9yRDzeiN5pj9i2fxDscy2AC8jx8UWBK BPaeL+Vh3Bd+J3M2nZrFJ35Y/Upx7RENjLaSNuB98ZtdNvXKlbE1OyWkl yCRJMPotgVRFM48cv5COiRFi68CQNXVV6Fh7cPz9V/iuhYM2lUnPGhslQ CgYVhmLcM+5csp61VuJTZNRSUoK5lcRmHFqfrJrZqrti2/zwV+Xs/scdm yAD3Wa5S1odzP8msreAKFOdR00fiP/YHllcC4jj9u3YRUzBlwi1rDNQNU hJSkHYnF0e75YBMyjR3BUvU7YNuDLT94N9XiZ7nkujSuOZubPNG6pdnIC g==; X-CSE-ConnectionGUID: UhO/vLOJS0651fUE9PKeYA== X-CSE-MsgGUID: UPvHSNrNSiamX7gMylmwaw== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="50973643" X-IronPort-AV: E=Sophos;i="6.13,279,1732608000"; d="scan'208";a="50973643" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:09 -0800 X-CSE-ConnectionGUID: /1Hqit5FRLCywX1rJuHPfA== X-CSE-MsgGUID: uTOVaMEBSkmefriggN3IEA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="116836934" Received: from dalessan-mobl3.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:08 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= Subject: [PATCH v7 10/13] drm/i915/display: Evade scanline 0 as well if PSR1 or PSR2 is enabled Date: Wed, 12 Feb 2025 09:57:39 +0200 Message-ID: <20250212075742.995022-12-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On wake-up scanline counting starts from vblank_start - 1. We don't know if wake-up is already ongoing when evasion starts. In worst case PIPEDSL could start reading valid value right after checking the scanline. In this scenario we wouldn't have enough time to write all registers. To tackle this evade scanline 0 as well. As a drawback we have 1 frame delay in flip when waking up. v2: - use intel_dsb_emit_wait_dsl - add evasion of scanline 0 also for Panel Replay Signed-off-by: Jouni Högander Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 30782ab0b908..f15e6c2a195c 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -538,6 +538,18 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state, int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 20); int start, end; + /* + * PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On + * wake-up scanline counting starts from vblank_start - 1. We don't know + * if wake-up is already ongoing when evasion starts. In worst case + * PIPEDSL could start reading valid value right after checking the + * scanline. In this scenario we wouldn't have enough time to write all + * registers. To tackle this evade scanline 0 as well. As a drawback we + * have 1 frame delay in flip when waking up. + */ + if (crtc_state->has_psr) + intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0); + if (pre_commit_is_vrr_active(state, crtc)) { int vblank_delay = intel_vrr_vblank_delay(crtc_state); From patchwork Wed Feb 12 07:57:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E39AFC02198 for ; Wed, 12 Feb 2025 07:58:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7F77010E7F3; Wed, 12 Feb 2025 07:58:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="G8X5qsB1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5DBA710E7F2; Wed, 12 Feb 2025 07:58:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739347091; x=1770883091; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KB7rLDkiTQHzAJDSYoG15l4TlWyHES6rvmfxDHAEoPQ=; b=G8X5qsB1O0b8OLRCzV2DtAdxG/Ugg2tifJN+dfUUei+7NTbXIcNwu50N gr9waGFTTlr2bPXFRRf0knYYvu0lC7e33vQB9GwC6qDJghZ+wT6rhyJRY ElzGNbI8kfgKFZ0FmiIOGRaoiO/ZTbZBqrIbffytPTFn6jwznuxCONni3 c5XWFo3G0t7YXVb7+QL+Llp0of5IbSvRwFUI9SH26iiJ84VC7LJppwpE4 rFHFKWrZd4G2sjA3Ge851IpIuImQQ1RPrO4RL5FET38y0T5aGMId+M3H0 n6kuLpBRFc1/liodtqoCm+TooDI/vDbeloy7H746erbgkFsLFAr/cKqer A==; X-CSE-ConnectionGUID: 8hTlHUsRQU6cVo7FU2tqFA== X-CSE-MsgGUID: GTjshTkJQKaKClPGoo+JOw== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="50973649" X-IronPort-AV: E=Sophos;i="6.13,279,1732608000"; d="scan'208";a="50973649" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:11 -0800 X-CSE-ConnectionGUID: PgcogxOeQoSvwhlq2hTmcg== X-CSE-MsgGUID: KU3yAqkTSqyi2AnCDgoYdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="116836939" Received: from dalessan-mobl3.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:09 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= Subject: [PATCH v7 11/13] drm/i915/psr: Add function for triggering "Frame Change" event Date: Wed, 12 Feb 2025 09:57:40 +0200 Message-ID: <20250212075742.995022-13-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add new function to trigger "Frame Change" event for ensuring we are waking up before vblank evasion. v2: dsb as a first parameter Signed-off-by: Jouni Högander Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_psr.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 3 +++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index c805ff82e700..427a7d1df1f9 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -44,6 +44,7 @@ #include "intel_psr.h" #include "intel_psr_regs.h" #include "intel_snps_phy.h" +#include "intel_vblank.h" #include "skl_universal_plane.h" /** @@ -2289,6 +2290,27 @@ bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state) return false; } +/** + * intel_psr_trigger_frame_change_event - Trigger "Frame Change" event + * @dsb: DSB context + * @state: the atomic state + * @crtc: the CRTC + * + * Generate PSR "Frame Change" event. + */ +void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, + struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_crtc_state *crtc_state = + intel_pre_commit_crtc_state(state, crtc); + struct intel_display *display = to_intel_display(crtc); + + if (crtc_state->has_psr) + intel_de_write_dsb(display, dsb, + CURSURFLIVE(display, crtc->pipe), 0); +} + static u32 man_trk_ctl_enable_bit_get(struct intel_display *display) { struct drm_i915_private *dev_priv = to_i915(display->drm); diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index e6eba6633a92..a43a374cff55 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -64,6 +64,9 @@ bool intel_psr_link_ok(struct intel_dp *intel_dp); void intel_psr_lock(const struct intel_crtc_state *crtc_state); void intel_psr_unlock(const struct intel_crtc_state *crtc_state); +void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, + struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_psr_connector_debugfs_add(struct intel_connector *connector); void intel_psr_debugfs_register(struct intel_display *display); From patchwork Wed Feb 12 07:57:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65084C021AB for ; Wed, 12 Feb 2025 07:58:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0476910E7F2; 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([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:11 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= Subject: [PATCH v7 12/13] drm/i915/display: Ensure we have "Frame Change" event in DSB commit Date: Wed, 12 Feb 2025 09:57:41 +0200 Message-ID: <20250212075742.995022-14-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We may have commit which doesn't have any non-arming plane register writes. In that case there aren't "Frame Change" event before DSB vblank evasion which hangs as PIPEDSL register is reading as 0 when PSR state is SRDENT(PSR1) or DEEP_SLEEP(PSR2). Handle this by ensuring "Frame Change" event at the begin of DSB commit if using PSR/PR. v3: dsb_commit as a first parameter v2: use intel_psr_trigger_frame_change_event Signed-off-by: Jouni Högander Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 79b8d2ad3b9c..0ba85623835c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7742,6 +7742,14 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit, state, crtc); + /* + * Ensure we have "Frame Change" event when PSR state is + * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank + * evasion hangs as PIPEDSL is reading as 0. + */ + intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit, + state, crtc); + intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit); if (intel_crtc_needs_color_update(new_crtc_state)) From patchwork Wed Feb 12 07:57:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13971333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 720A8C021A6 for ; Wed, 12 Feb 2025 07:58:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A3CD10E7F4; Wed, 12 Feb 2025 07:58:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WlH/6sBX"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id B3D3010E7F4; Wed, 12 Feb 2025 07:58:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739347094; x=1770883094; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8TBvc+pPqWn4Y2C8qEqHR8ariik/CtZFlVZ8Uu61qw8=; b=WlH/6sBXJegRoRCHMswPcfuXZ9NwSZjAIjr9SBUCsE5xOzz1AToRm63c pD4dUKjwWWYcGyjp3oLjbdDlDkj8r9kBhkfLh5MHsiVw865MyAEWSrASo AbGCNT6eNsvRgyYe8aKF6tOaedvg2B8BsfJLiuySPYiXRB7UxOyXOymtU qtzEIpmAPqaTFAPI91+l5bsEzZaZrVKVxR3RReoJKBPu+UUwmXa6Sc8XR C+z2/bz3HIjs4ekJWrwwqU9vhNcBTedypxfS3YtjJTzakvazv5J1pkdNb 1kQYmmxO/8OXiiu2hvp3L3WmLDA1/ydkmbcpV9mIkkMp6AYp14B3LQj9P Q==; X-CSE-ConnectionGUID: zpyFOHR4TLWNqoE4QttS0A== X-CSE-MsgGUID: u0sEa57FR6KyZgTAefhlMw== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="50973660" X-IronPort-AV: E=Sophos;i="6.13,279,1732608000"; d="scan'208";a="50973660" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:14 -0800 X-CSE-ConnectionGUID: bYMC85jISiGWJoEVtyxTvQ== X-CSE-MsgGUID: 64gQpsc7TAarQqA96rFkDw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="116836950" Received: from dalessan-mobl3.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.81]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2025 23:58:13 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , Animesh Manna Subject: [PATCH v7 13/13] drm/i915/psr: Allow DSB usage when PSR is enabled Date: Wed, 12 Feb 2025 09:57:42 +0200 Message-ID: <20250212075742.995022-15-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212075742.995022-1-jouni.hogander@intel.com> References: <20250212075742.995022-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB usage also when PSR is enabled for LunarLake onwards. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_display.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0ba85623835c..a6966a664d87 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7698,6 +7698,7 @@ static void intel_atomic_dsb_prepare(struct intel_atomic_state *state, static void intel_atomic_dsb_finish(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); struct intel_crtc_state *new_crtc_state = @@ -7713,7 +7714,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, new_crtc_state->use_dsb = new_crtc_state->update_planes && !new_crtc_state->do_async_flip && - !new_crtc_state->has_psr && + (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) && !new_crtc_state->scaler_state.scaler_users && !old_crtc_state->scaler_state.scaler_users && !intel_crtc_needs_modeset(new_crtc_state) &&