From patchwork Wed Feb 12 16:18:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13972061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52255C02198 for ; Wed, 12 Feb 2025 16:17:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DAA3B89496; Wed, 12 Feb 2025 16:17:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mItAcNv8"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 187EB89496; Wed, 12 Feb 2025 16:17:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739377073; x=1770913073; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=XpJV35U97FhYK+AL8Yda+oOzRCN0Xjo9cKENv+kQkaA=; b=mItAcNv8mb3XVnqF/ax5sTlzG38N6j6qc1dfvx3ZY9YpcnhdPGm8NUwA P1nEkb/JIRdNHE1DxG599AA0wq9D50YIBAQOEJkt79yn8unyYPzwOl/sB pFV4OEGYPH/+2ibU34NC7sNCeNus0alKvwlxOmghDouofHt8Yw2czYI0M nYp07kBbaeUEnr0McgX1gbYAluTe++ur+N5JXwmZPuGEN1SB2flvXi8YK PJ2vdJoVuLOiugKOj4VSUVmrJ2Wejc7Up3NTkMQCNe+gH8A+njfmX2muX TYLfPMH/tB/KGLFKaGs72EtEHazoK6oh1OjDtEuuDFUxh7qptuuxWCiPK Q==; X-CSE-ConnectionGUID: qWsGiV6FTq23qmOfR2nzzg== X-CSE-MsgGUID: NuSsCd0OTFyis4O+onsxlg== X-IronPort-AV: E=McAfee;i="6700,10204,11343"; a="57447435" X-IronPort-AV: E=Sophos;i="6.13,280,1732608000"; d="scan'208";a="57447435" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Feb 2025 08:17:53 -0800 X-CSE-ConnectionGUID: fL9VmUs1TwKdaDdQMd+ncw== X-CSE-MsgGUID: LzubKaaIS+aLtDS0Qa40/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,280,1732608000"; d="scan'208";a="143710438" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Feb 2025 08:17:51 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Ankit Nautiyal Subject: [PATCH] drm: Fix DSC BPP increment decoding Date: Wed, 12 Feb 2025 18:18:51 +0200 Message-ID: <20250212161851.4007005-1-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Starting with DPCD version 2.0 bits 6:3 of the DP_DSC_BITS_PER_PIXEL_INC DPCD register contains the NativeYCbCr422_MAX_bpp_DELTA field, which can be non-zero as opposed to earlier DPCD versions, hence decoding the bit_per_pixel increment value at bits 2:0 in the same register requires applying a mask, do so. Cc: Ankit Nautiyal Fixes: 0c2287c96521 ("drm/display/dp: Add helper function to get DSC bpp precision") Signed-off-by: Imre Deak Reviewed-by: Jani Nikula --- drivers/gpu/drm/display/drm_dp_helper.c | 2 +- include/drm/display/drm_dp.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index c488d160a3c1f..f5c596234729d 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -2602,7 +2602,7 @@ u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) { u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; - switch (bpp_increment_dpcd) { + switch (bpp_increment_dpcd & DP_DSC_BITS_PER_PIXEL_MASK) { case DP_DSC_BITS_PER_PIXEL_1_16: return 16; case DP_DSC_BITS_PER_PIXEL_1_8: diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 784a32bfbad8f..c413ef68f9a30 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -359,6 +359,7 @@ # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 # define DP_DSC_BITS_PER_PIXEL_1_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_MASK 0x7 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1