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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fbf98b4c52sm1964837a91.4.2025.02.12.14.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2025 14:01:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 1/9] target/microblaze: Split out mb_unaligned_access_internal Date: Wed, 12 Feb 2025 14:01:47 -0800 Message-ID: <20250212220155.1147144-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212220155.1147144-1-richard.henderson@linaro.org> References: <20250212220155.1147144-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use an explicit 64-bit type for the address to store in EAR. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 3 +++ target/microblaze/helper.c | 25 ++++++++++++++++--------- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f6879eee35..45f7f49809 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -372,6 +372,9 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); #endif /* !CONFIG_USER_ONLY */ +G_NORETURN void mb_unaligned_access_internal(CPUState *cs, uint64_t addr, + MMUAccessType access_type, + uintptr_t retaddr); G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5d3259ce31..8b096e3e58 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -268,20 +268,20 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #endif /* !CONFIG_USER_ONLY */ -void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +G_NORETURN +void mb_unaligned_access_internal(CPUState *cs, uint64_t addr, + MMUAccessType access_type, uintptr_t retaddr) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = cpu_env(cs); uint32_t esr, iflags; /* Recover the pc and iflags from the corresponding insn_start. */ cpu_restore_state(cs, retaddr); - iflags = cpu->env.iflags; + iflags = env->iflags; qemu_log_mask(CPU_LOG_INT, - "Unaligned access addr=" TARGET_FMT_lx " pc=%x iflags=%x\n", - (target_ulong)addr, cpu->env.pc, iflags); + "Unaligned access addr=0x%" PRIx64 " pc=%x iflags=%x\n", + addr, env->pc, iflags); esr = ESR_EC_UNALIGNED_DATA; if (likely(iflags & ESR_ESS_FLAG)) { @@ -290,8 +290,15 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n"); } - cpu->env.ear = addr; - cpu->env.esr = esr; + env->ear = addr; + env->esr = esr; cs->exception_index = EXCP_HW_EXCP; cpu_loop_exit(cs); } + +void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + mb_unaligned_access_internal(cs, addr, access_type, retaddr); +} From patchwork Wed Feb 12 22:01:48 2025 Content-Type: text/plain; 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fbf98b4c52sm1964837a91.4.2025.02.12.14.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2025 14:01:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 2/9] target/microblaze: Split out mb_transaction_failed_internal Date: Wed, 12 Feb 2025 14:01:48 -0800 Message-ID: <20250212220155.1147144-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212220155.1147144-1-richard.henderson@linaro.org> References: <20250212220155.1147144-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use an explicit 64-bit type for the address to store in EAR. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/microblaze/op_helper.c | 70 +++++++++++++++++++++-------------- 1 file changed, 42 insertions(+), 28 deletions(-) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f6378030b7..6019c5b2eb 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -394,38 +394,52 @@ void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v) mmu_write(env, ext, rn, v); } +static void mb_transaction_failed_internal(CPUState *cs, hwaddr physaddr, + uint64_t addr, unsigned size, + MMUAccessType access_type, + uintptr_t retaddr) +{ + CPUMBState *env = cpu_env(cs); + MicroBlazeCPU *cpu = env_archcpu(env); + const char *access_name = "INVALID"; + bool take = env->msr & MSR_EE; + uint32_t esr = ESR_EC_DATA_BUS; + + switch (access_type) { + case MMU_INST_FETCH: + access_name = "INST_FETCH"; + esr = ESR_EC_INSN_BUS; + take &= cpu->cfg.iopb_bus_exception; + break; + case MMU_DATA_LOAD: + access_name = "DATA_LOAD"; + take &= cpu->cfg.dopb_bus_exception; + break; + case MMU_DATA_STORE: + access_name = "DATA_STORE"; + take &= cpu->cfg.dopb_bus_exception; + break; + } + + qemu_log_mask(CPU_LOG_INT, "Transaction failed: addr 0x%" PRIx64 + "physaddr 0x" HWADDR_FMT_plx " size %d access-type %s (%s)\n", + addr, physaddr, size, access_name, + take ? "TAKEN" : "DROPPED"); + + if (take) { + env->esr = esr; + env->ear = addr; + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, retaddr); + } +} + void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; - - qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx - " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n", - addr, physaddr, size, - access_type == MMU_INST_FETCH ? "INST_FETCH" : - (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE")); - - if (!(env->msr & MSR_EE)) { - return; - } - - if (access_type == MMU_INST_FETCH) { - if (!cpu->cfg.iopb_bus_exception) { - return; - } - env->esr = ESR_EC_INSN_BUS; - } else { - if (!cpu->cfg.dopb_bus_exception) { - return; - } - env->esr = ESR_EC_DATA_BUS; - } - - env->ear = addr; - cs->exception_index = EXCP_HW_EXCP; - cpu_loop_exit_restore(cs, retaddr); + mb_transaction_failed_internal(cs, physaddr, addr, size, + access_type, retaddr); } #endif From patchwork Wed Feb 12 22:01:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13972475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09B0AC021A0 for ; Wed, 12 Feb 2025 22:03:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiKo1-0006mB-09; Wed, 12 Feb 2025 17:02:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiKny-0006l2-SJ for qemu-devel@nongnu.org; Wed, 12 Feb 2025 17:02:02 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiKnw-0004S5-Lz for qemu-devel@nongnu.org; Wed, 12 Feb 2025 17:02:02 -0500 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-21f49837d36so1904725ad.3 for ; Wed, 12 Feb 2025 14:02:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739397719; x=1740002519; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BYm6yE7hZRuV0xmNrggaqiwHwyUyPJzftvmjuRCP7S4=; b=rjvo12Z5Iel87j9vtjDuvDaadDHd5eAFjv95n75dG09VKDITic1iYFQJx2CqULw2ZQ KZaFqbsdQPKby5TA1s/9vqCri9835kIgZMom80yZt9Y/FGgIG7LywIf6/vtu9PRGduCD SHdHpNvfjPAZtKQ2CpZFAiFoblHwgpWgcL7ACOMCGEtwAUnTpcC75hlCbTz3XEIqXOLG xcWc6UtUH3AnzlxKiNy7gI2ImVO1UeCaT0D86k9HYQ0GpooYoxuMbu6yKdiK7kE1b2G3 nG7qtAPwxaQXH2wZ/zEIxZYbWX0UliftYogyZzXSfgqSnKMIpgpc7M2av8oSz8kvNmJJ 9FtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739397719; x=1740002519; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BYm6yE7hZRuV0xmNrggaqiwHwyUyPJzftvmjuRCP7S4=; b=W9gPKr55vSb4w9wsz0pXVjTsIVSGbEUksUlp3YKH/CVwG7poJY5Z+1hyDLXXwalN7D iONGz9dZ4CR64JZTsqHHizFbo1wDbLCyLbFMlqmECSUdmU90aCzbePf+18qYjEiK3swX 064gGWAfgpYNDdSATrB4uj+vGWUW+PSfbSyFLuUOmf5clBnkbDNmJnAQMXtSjEsW47YP dzmvQ5NUd7Lsrn0mu4qte5SNJ9ENQhNs9KDyPgv4rZtu+oIBvONKRi6Je8XGXNGafjP8 /kfkh6fcyD+zAv6l+ADH390C/O7PaTBo7QJWWji55OAATrnspxN2t2CPm3XsihdPGdog fygA== X-Gm-Message-State: AOJu0YzbMGPIFKLtEMcnV7keCqVA5k7Etc47nUrk08kqPglBakU6h0hq RjSUk4PVBytnSC4yX86Yk5I6UMBVr0OzGjV31yYELAGe5YRf28ooEmPp0ZzrGm2szjwyIyKxJiY s X-Gm-Gg: ASbGncuQMySYaSE5nSMWZd8ZEToh74qKSvRf7Jb1JjHjOiNhr1jEITRDoFDub/85iOB VxGGhWLK/wRHJBrCUDX0eozFK5txlmFY4oADWGcZpVcHHSyKBZRCpyJ90fyTnl88Pr/E0OlAwbs At+CdWnoanty3SCgZK/yJwaylW+4yCRftmyaWSH67DJPFHSKva/AH4czGib9ZxrgRviBdrfGtDo cFudISGGc8kanl8yv/6liL1NSkYyDCb9jMrJFioTzK0H7ZPx1iEohTIYQO5HBFLyEPVXlxNKOVq U1VdzsShsuJzyTjj3V+tK+jiw6FXq8fuTb0xAyRTRG61S6o= X-Google-Smtp-Source: AGHT+IE75qEysW+CxVmVPkxWEKMVpA19U3APVNVdqb39MqwZRLCCEbQl+97/YeuX+PdxUEQlx8zchw== X-Received: by 2002:a17:902:fc8e:b0:21d:ccec:b321 with SMTP id d9443c01a7336-220d2110d0amr13183225ad.34.1739397719163; Wed, 12 Feb 2025 14:01:59 -0800 (PST) Received: from stoup.. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fbf98b4c52sm1964837a91.4.2025.02.12.14.01.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2025 14:01:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 3/9] target/microblaze: Implement extended address load/store out of line Date: Wed, 12 Feb 2025 14:01:49 -0800 Message-ID: <20250212220155.1147144-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212220155.1147144-1-richard.henderson@linaro.org> References: <20250212220155.1147144-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use helpers and address_space_ld/st instead of inline loads and stores. This allows us to perform operations on physical addresses wider than virtual addresses. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 16 ++++-- target/microblaze/op_helper.c | 99 +++++++++++++++++++++++++++++++++++ target/microblaze/translate.c | 42 ++++++++++----- 3 files changed, 140 insertions(+), 17 deletions(-) diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index f740835fcb..f3ef5a3150 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -20,12 +20,18 @@ DEF_HELPER_FLAGS_3(fcmp_ne, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32) -#if !defined(CONFIG_USER_ONLY) -DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32) -#endif - DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_2(get, TCG_CALL_NO_RWG, i32, i32, i32) DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32) + +#if !defined(CONFIG_USER_ONLY) +DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_2(lbuea, TCG_CALL_NO_WG, i32, env, i64) +DEF_HELPER_FLAGS_2(lhuea, TCG_CALL_NO_WG, i32, env, i64) +DEF_HELPER_FLAGS_2(lwea, TCG_CALL_NO_WG, i32, env, i64) +DEF_HELPER_FLAGS_3(sbea, TCG_CALL_NO_WG, void, env, i32, i64) +DEF_HELPER_FLAGS_3(shea, TCG_CALL_NO_WG, void, env, i32, i64) +DEF_HELPER_FLAGS_3(swea, TCG_CALL_NO_WG, void, env, i32, i64) +#endif diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 6019c5b2eb..722810cb9c 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -25,6 +25,7 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/memory.h" #include "fpu/softfloat.h" void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) @@ -442,4 +443,102 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, mb_transaction_failed_internal(cs, physaddr, addr, size, access_type, retaddr); } + +uint32_t HELPER(lbuea)(CPUMBState *env, uint64_t ea) +{ + CPUState *cs = env_cpu(env); + uintptr_t ra = GETPC(); + MemTxResult txres; + uint8_t ret; + + ret = address_space_ldub(cs->as, ea, MEMTXATTRS_UNSPECIFIED, &txres); + if (unlikely(txres != MEMTX_OK)) { + mb_transaction_failed_internal(cs, ea, ea, 1, MMU_DATA_LOAD, ra); + } + return ret; +} + +uint32_t HELPER(lhuea)(CPUMBState *env, uint64_t ea) +{ + CPUState *cs = env_cpu(env); + uintptr_t ra = GETPC(); + MemTxResult txres; + uint16_t ret; + + if (unlikely(ea & 1) + && (env->msr & MSR_EE) + && env_archcpu(env)->cfg.unaligned_exceptions) { + mb_unaligned_access_internal(cs, ea, MMU_DATA_LOAD, ra); + } + ret = address_space_lduw(cs->as, ea, MEMTXATTRS_UNSPECIFIED, &txres); + if (unlikely(txres != MEMTX_OK)) { + mb_transaction_failed_internal(cs, ea, ea, 2, MMU_DATA_LOAD, ra); + } + return ret; +} + +uint32_t HELPER(lwea)(CPUMBState *env, uint64_t ea) +{ + CPUState *cs = env_cpu(env); + uintptr_t ra = GETPC(); + MemTxResult txres; + uint32_t ret; + + if (unlikely(ea & 3) + && (env->msr & MSR_EE) + && env_archcpu(env)->cfg.unaligned_exceptions) { + mb_unaligned_access_internal(cs, ea, MMU_DATA_LOAD, ra); + } + ret = address_space_ldl(cs->as, ea, MEMTXATTRS_UNSPECIFIED, &txres); + if (unlikely(txres != MEMTX_OK)) { + mb_transaction_failed_internal(cs, ea, ea, 4, MMU_DATA_LOAD, ra); + } + return ret; +} + +void HELPER(sbea)(CPUMBState *env, uint32_t data, uint64_t ea) +{ + CPUState *cs = env_cpu(env); + uintptr_t ra = GETPC(); + MemTxResult txres; + + address_space_stb(cs->as, ea, data, MEMTXATTRS_UNSPECIFIED, &txres); + if (unlikely(txres != MEMTX_OK)) { + mb_transaction_failed_internal(cs, ea, ea, 1, MMU_DATA_STORE, ra); + } +} + +void HELPER(shea)(CPUMBState *env, uint32_t data, uint64_t ea) +{ + CPUState *cs = env_cpu(env); + uintptr_t ra = GETPC(); + MemTxResult txres; + + if (unlikely(ea & 1) + && (env->msr & MSR_EE) + && env_archcpu(env)->cfg.unaligned_exceptions) { + mb_unaligned_access_internal(cs, ea, MMU_DATA_STORE, ra); + } + address_space_stw(cs->as, ea, data, MEMTXATTRS_UNSPECIFIED, &txres); + if (unlikely(txres != MEMTX_OK)) { + mb_transaction_failed_internal(cs, ea, ea, 2, MMU_DATA_STORE, ra); + } +} + +void HELPER(swea)(CPUMBState *env, uint32_t data, uint64_t ea) +{ + CPUState *cs = env_cpu(env); + uintptr_t ra = GETPC(); + MemTxResult txres; + + if (unlikely(ea & 3) + && (env->msr & MSR_EE) + && env_archcpu(env)->cfg.unaligned_exceptions) { + mb_unaligned_access_internal(cs, ea, MMU_DATA_STORE, ra); + } + address_space_stl(cs->as, ea, data, MEMTXATTRS_UNSPECIFIED, &txres); + if (unlikely(txres != MEMTX_OK)) { + mb_transaction_failed_internal(cs, ea, ea, 4, MMU_DATA_STORE, ra); + } +} #endif diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 24005f05b2..d5c5e650e0 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -764,10 +764,11 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *arg) return true; } #ifdef CONFIG_USER_ONLY - return true; + g_assert_not_reached(); #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); + gen_helper_lbuea(reg_for_write(dc, arg->rd), tcg_env, addr); + return true; #endif } @@ -795,10 +796,14 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) return true; } #ifdef CONFIG_USER_ONLY - return true; + g_assert_not_reached(); #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + if ((dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { + record_unaligned_ess(dc, arg->rd, MO_16, false); + } + gen_helper_lhuea(reg_for_write(dc, arg->rd), tcg_env, addr); + return true; #endif } @@ -826,10 +831,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) return true; } #ifdef CONFIG_USER_ONLY - return true; + g_assert_not_reached(); #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + if ((dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { + record_unaligned_ess(dc, arg->rd, MO_32, false); + } + gen_helper_lwea(reg_for_write(dc, arg->rd), tcg_env, addr); + return true; #endif } @@ -914,10 +923,11 @@ static bool trans_sbea(DisasContext *dc, arg_typea *arg) return true; } #ifdef CONFIG_USER_ONLY - return true; + g_assert_not_reached(); #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); + gen_helper_sbea(tcg_env, reg_for_read(dc, arg->rd), addr); + return true; #endif } @@ -945,10 +955,14 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) return true; } #ifdef CONFIG_USER_ONLY - return true; + g_assert_not_reached(); #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + if ((dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { + record_unaligned_ess(dc, arg->rd, MO_16, true); + } + gen_helper_shea(tcg_env, reg_for_read(dc, arg->rd), addr); + return true; #endif } @@ -976,10 +990,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) return true; } #ifdef CONFIG_USER_ONLY - return true; + g_assert_not_reached(); #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + if ((dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { + record_unaligned_ess(dc, arg->rd, MO_32, true); + } + gen_helper_swea(tcg_env, reg_for_read(dc, arg->rd), addr); + return true; #endif } From patchwork Wed Feb 12 22:01:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13972473 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66155C02198 for ; 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fbf98b4c52sm1964837a91.4.2025.02.12.14.01.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2025 14:01:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 4/9] target/microblaze: Use uint64_t for CPUMBState.ear Date: Wed, 12 Feb 2025 14:01:50 -0800 Message-ID: <20250212220155.1147144-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212220155.1147144-1-richard.henderson@linaro.org> References: <20250212220155.1147144-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use an explicit 64-bit type for EAR. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 45f7f49809..01571d4f86 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -248,7 +248,7 @@ struct CPUArchState { uint32_t pc; uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */ uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */ - target_ulong ear; + uint64_t ear; uint32_t esr; uint32_t fsr; uint32_t btr; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index d5c5e650e0..549013d25e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1842,7 +1842,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) } qemu_fprintf(f, "\nesr=0x%04x fsr=0x%02x btr=0x%08x edr=0x%x\n" - "ear=0x" TARGET_FMT_lx " slr=0x%x shr=0x%x\n", + "ear=0x%" PRIx64 " slr=0x%x shr=0x%x\n", env->esr, env->fsr, env->btr, env->edr, env->ear, env->slr, env->shr); From patchwork Wed Feb 12 22:01:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13972470 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F354C021A5 for ; Wed, 12 Feb 2025 22:03:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiKo4-0006oX-7P; Wed, 12 Feb 2025 17:02:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiKo0-0006ly-47 for qemu-devel@nongnu.org; Wed, 12 Feb 2025 17:02:04 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiKny-0004SU-8O for qemu-devel@nongnu.org; Wed, 12 Feb 2025 17:02:03 -0500 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-220c8f38febso2692845ad.2 for ; Wed, 12 Feb 2025 14:02:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739397721; x=1740002521; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z46Rzxp1rqHOdnC9w48Zi9qlaZaCm/K3R1IX0q0/ej4=; b=Yt/4/G3LfUbTazORFgpOb1v7nFlbaNPSoQVgbTjKZLx5hSO3WQAbLuIba2y+LYTqcT Bdw5ja5918mws2U83t+q6TenC4STUfT8Ok4JLvk1UFJZv8qq7cSkV4PrB8Z2L9wSUtcM uEqUoJLf5W0AmhS4Z7G4d2YhlaHl75UMRxGQ/fqoV0iKMTFiNt1bVxRLUjw2bK0AuKnn g9M39ClqpMKz/CNI1hoixbKDiIs1Qo8OF2XmpsP+c6uO8LWVGI4fqbHQQo0G9phWilY/ 3LJ51Rlq13gIeofXJQvgQxyIArfR+TD5pAxgPb1/YOtzMIJih8NApDZB/3+PzXiL4wbQ +y8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739397721; x=1740002521; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z46Rzxp1rqHOdnC9w48Zi9qlaZaCm/K3R1IX0q0/ej4=; b=FYMJiUyjaukZvgzYk0l+fHmyN8+32hI9Z4YRI1Jch3VGP4Q24hogleQJNFCWrZ/pID /PfJqXV6eI213DjhAl4UjPviq8K181CS4tbAwvXPoZWR8OCzexC+Tj99VBh4go97Jb31 9wyEh9KvT4xIw/ZgGkyk6fBjcsVG9yheRR0+On/DK0HKKbbgoNPzRzOdEiPtxzSBP/D3 oiXVuuo5J4L8lc1koZlf/DPgLHPUOIEErBTwf0QfrYEgSjqsFLiAA8eZgP9UCGcByrpe uwnisPxCNtj/pgPc9DqeBvzMA8O6sHZeX5Kjfw7Pjbo+wcTQ+o+bFqWjfK2DMxNcMeYt 3bpQ== X-Gm-Message-State: AOJu0YyD+YSYCXzen7xnpKCt5FUg1D5Yothk9CcJmeOHBqsVddJXdj4P iE04M1fmSa+X2k95YOM8WIzh2r9xYIYMwx16jNPcAzeTLr/MgWAxha1X9FVMHqkoCs0ppViI+5U w X-Gm-Gg: ASbGnctIPWxBMJR/hjlZYy4Mse/ae30ycYJvNDS/YXhWlFLCVPKVKJPL+i5PFmgfIMQ /DEymAhSE4rNmboLwFyeA9EWXEUWt1VrxtRu1t5s0Y8lIGwJPsnYUT6dLAtTLL8pzxBKVr+21dP RTk28Vsz3hZAB1uuKYrQ0XTPMCijybgm85pRvULU8FrTwZOum0NedCoH8k51zE+48R0LRSGTggm atUkkLstYxpBtIpYIWdfWrIETYuh9Zd0ZrdCSimjnWPqZfmfP0SXWIK/8B0Wqco8ewDvbbZFKn3 EelN+joZpYWKqy+ofFd3bl5eUA4aUcR3uIWJwREBD0+fBxY= X-Google-Smtp-Source: AGHT+IFgzfTNH39SvTnCVA61TkR3SyPee6oITqld97Ks2FaLLLHcH+sgmHEKKQyJ61AvGBpn0LoCZg== X-Received: by 2002:a17:902:fc8e:b0:215:a05d:fb05 with SMTP id d9443c01a7336-220bdfee6a5mr84096335ad.32.1739397720790; Wed, 12 Feb 2025 14:02:00 -0800 (PST) Received: from stoup.. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fbf98b4c52sm1964837a91.4.2025.02.12.14.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2025 14:02:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 5/9] target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea Date: Wed, 12 Feb 2025 14:01:51 -0800 Message-ID: <20250212220155.1147144-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212220155.1147144-1-richard.henderson@linaro.org> References: <20250212220155.1147144-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use an explicit 64-bit type for extended addresses. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/microblaze/translate.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 549013d25e..a1d81b0166 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -666,23 +666,23 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) } #ifndef CONFIG_USER_ONLY -static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) +static TCGv_i64 compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) { int addr_size = dc->cfg->addr_size; - TCGv ret = tcg_temp_new(); + TCGv_i64 ret = tcg_temp_new_i64(); if (addr_size == 32 || ra == 0) { if (rb) { - tcg_gen_extu_i32_tl(ret, cpu_R[rb]); + tcg_gen_extu_i32_i64(ret, cpu_R[rb]); } else { - tcg_gen_movi_tl(ret, 0); + return tcg_constant_i64(0); } } else { if (rb) { tcg_gen_concat_i32_i64(ret, cpu_R[rb], cpu_R[ra]); } else { - tcg_gen_extu_i32_tl(ret, cpu_R[ra]); - tcg_gen_shli_tl(ret, ret, 32); + tcg_gen_extu_i32_i64(ret, cpu_R[ra]); + tcg_gen_shli_i64(ret, ret, 32); } if (addr_size < 64) { /* Mask off out of range bits. */ @@ -766,7 +766,7 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *arg) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); gen_helper_lbuea(reg_for_write(dc, arg->rd), tcg_env, addr); return true; #endif @@ -798,7 +798,7 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); if ((dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, arg->rd, MO_16, false); } @@ -833,7 +833,7 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); if ((dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, arg->rd, MO_32, false); } @@ -925,7 +925,7 @@ static bool trans_sbea(DisasContext *dc, arg_typea *arg) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); gen_helper_sbea(tcg_env, reg_for_read(dc, arg->rd), addr); return true; #endif @@ -957,7 +957,7 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); if ((dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, arg->rd, MO_16, true); } @@ -992,7 +992,7 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); if ((dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, arg->rd, MO_32, true); } From patchwork Wed Feb 12 22:01:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13972477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 828B0C021A0 for ; Wed, 12 Feb 2025 22:04:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiKo7-0006pS-Dg; Wed, 12 Feb 2025 17:02:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiKo0-0006mF-Vg for qemu-devel@nongnu.org; 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Signed-off-by: Richard Henderson --- target/microblaze/mmu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 2423ac6172..6152fdafd5 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -170,7 +170,8 @@ unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu, } done: qemu_log_mask(CPU_LOG_MMU, - "MMU vaddr=%" PRIx64 " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n", + "MMU vaddr=0x" TARGET_FMT_lx + " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n", vaddr, rw, tlb_wr, tlb_ex, hit); return hit; } From patchwork Wed Feb 12 22:01:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13972472 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B20FC02198 for ; Wed, 12 Feb 2025 22:03:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiKo6-0006pO-Gp; Wed, 12 Feb 2025 17:02:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiKo1-0006n2-Fz for qemu-devel@nongnu.org; Wed, 12 Feb 2025 17:02:05 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiKnz-0004Sw-JT for qemu-devel@nongnu.org; Wed, 12 Feb 2025 17:02:05 -0500 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2fa8ada664fso410756a91.3 for ; Wed, 12 Feb 2025 14:02:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739397722; x=1740002522; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7iYLnqu4pD+pMC95boMC9yu/CGb6NnBO0j8tMSFSt/A=; b=VyYsxyURNr296dWc2Htwfk0cQQwGkuUQ/WpAS3HCMunuLq130YnvXRskWtaTjSWrJH 9v7z0HTMyVdJwLLCQmK+TUnZuc2eGB9SpctnLcML/GjgGJ1Hwn1oL61vTWO3nZvYkPeW j7qlMGJR4UoPiHtK4WnBe99n9q/5DUDjXAr2mif8DJmWYh1lvmmnq0vDwkX/+Wcj159s vYnJyZjdfAV9EtPosYQi0WGs0979EFQFxPaEvSmhPschFZjze4WqzMgv3OiOqpdZAlkE Z9w8eeenN/jddb/ressdO6s324LDeB06MpbGCZlS91bEWkCbm4jXKZJXS9Egq52xg8sm fjGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739397722; x=1740002522; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7iYLnqu4pD+pMC95boMC9yu/CGb6NnBO0j8tMSFSt/A=; b=vUkCVhBkoKbbpMPZ0+iAqqumchBqbWvvPIff10LGQqW6ECGQQ0PDl0J6V+Flre84cQ vJijlKT7XweF0UPSoOwWwrc5n/K4GNV65Gxi964AwZrkKEi6tm+ODkJxbPbqGrwvhcPL GWsiWsMIy563sW0Ha2HYPKUNzKxAwruVHewytGhh+9PMJN/1iXYOIVG2VonCAxihJaAt 9yiXUOeLhvdbG+WGpc4U009Vtwu7gI9m/bDhW1s3YDkfFbXE8HzjXdhz1qF3DbJll1PL qG5samZHaQOnvB7e53LUF58whljSscQ59y1PhPsuW1dRAUyh14SqhPnhsWUz5t/jxs0x eZEA== X-Gm-Message-State: AOJu0Yy4hd4ENa+ArlDSLyr8Mupe7lLO32NNf1SF/W38JPJ+wmD3wbLs Ktvnt2mm1r0tDR57TwgrFG4z0umun7P8ga7WtvkVZQZJU6J/dNVACmo1rPMWteMsoHksOyrHlFJ m X-Gm-Gg: ASbGncsc6yUHpywg9yz/ZugGv6diIdQtBscLFa1LY9pl5YYeil03nJQVfTl5u5qGIAw +JS6gufmzeh5cHm9uSY2s5qCZrxR0Dciqcu1kxL1thGFRJULc999fZ0znk52glq9h/OXoM7ZvZM GRhBCGy4y21kx/TPn1UcSkrDzWZxo5L/E0tIzFmb8vnDWUtG6RcIRmOA/ezbZyUMNmkgrQ9Os9u jzjyj4gnyyXOxajmeAclz2kZJ+Qx9l89Sh8Fkt/KrD/fLaVn4zUxEkibx6Zga7OPcsCVf+BF3wn Bopx0qo9jQCIhTxfdDy3lV2hiqH5vLDp6GvLHBybKy0m5iE= X-Google-Smtp-Source: AGHT+IHFunovOgBZVZYGOmSQkHtca4ZBxnGP+Xye8GNOjcQpdG4GG+hJfo2y0zlRwYT1cD88YofSVw== X-Received: by 2002:a17:90a:d00e:b0:2ee:7c65:ae8e with SMTP id 98e67ed59e1d1-2fbf5bf4948mr7213685a91.11.1739397722159; Wed, 12 Feb 2025 14:02:02 -0800 (PST) Received: from stoup.. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fbf98b4c52sm1964837a91.4.2025.02.12.14.02.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2025 14:02:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 7/9] target/microblaze: Use TARGET_LONG_BITS == 32 for system mode Date: Wed, 12 Feb 2025 14:01:53 -0800 Message-ID: <20250212220155.1147144-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212220155.1147144-1-richard.henderson@linaro.org> References: <20250212220155.1147144-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that the extended address instructions are handled separately from virtual addresses, we can narrow the emulation to 32-bit. Signed-off-by: Richard Henderson --- configs/targets/microblaze-softmmu.mak | 4 +--- configs/targets/microblazeel-softmmu.mak | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/microblaze-softmmu.mak index 99a33ed44a..47e076af91 100644 --- a/configs/targets/microblaze-softmmu.mak +++ b/configs/targets/microblaze-softmmu.mak @@ -4,6 +4,4 @@ TARGET_SUPPORTS_MTTCG=y # needed by boot.c TARGET_NEED_FDT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml -# System mode can address up to 64 bits via lea/sea instructions. -# TODO: These bypass the mmu, so we could emulate these differently. -TARGET_LONG_BITS=64 +TARGET_LONG_BITS=32 diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/microblazeel-softmmu.mak index 52cdeae1a2..1b0e86c4be 100644 --- a/configs/targets/microblazeel-softmmu.mak +++ b/configs/targets/microblazeel-softmmu.mak @@ -3,6 +3,4 @@ TARGET_SUPPORTS_MTTCG=y # needed by boot.c TARGET_NEED_FDT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml -# System mode can address up to 64 bits via lea/sea instructions. -# TODO: These bypass the mmu, so we could emulate these differently. -TARGET_LONG_BITS=64 +TARGET_LONG_BITS=32 From patchwork Wed Feb 12 22:01:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13972476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67A24C02198 for ; Wed, 12 Feb 2025 22:03:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiKo7-0006pT-Ea; Wed, 12 Feb 2025 17:02:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiKo2-0006nA-31 for qemu-devel@nongnu.org; Wed, 12 Feb 2025 17:02:06 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiKo0-0004TA-Cl for qemu-devel@nongnu.org; Wed, 12 Feb 2025 17:02:05 -0500 Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-2fa7465baceso573551a91.0 for ; Wed, 12 Feb 2025 14:02:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739397723; x=1740002523; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MmaajkaaAGIJ5jI2bE/DwNAq4pcqOQSPMALbdv9/6WI=; b=ccv+2o8QQWIfFgvjY94SXiexTUccnzk7GdmRmApH9SucsKkdi0djG2e9VczgDJDOUk epFBFoNPpm0WtrnDPETAk9Lsx5pGY8GtWUljWGimjS4SNNApUNo7bKc8vAY7mver9hT1 m+5iDplbD17mJrO3LA7WVqWiGvKd4VripBy0lxl+W4R5ONB44LGfYrP8vaL/Bv5lAfwC M6vNdHPu/ZfU0v7AyiIpJHfuJyuNNo/B7JTMUePan8zG4qjq5fT/8WTTi4qJTjslQFaZ NwREd+gK1YcOyyamnVduhIF0vhYoGl1Y47iLN3979Xg53irXWSyOcIH/7QhEXZJCNET0 x6Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739397723; x=1740002523; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MmaajkaaAGIJ5jI2bE/DwNAq4pcqOQSPMALbdv9/6WI=; b=BRa28MMiJbnesC+9lMhrpznwwkbsvWq2FjlZi0ZH99AHDT6wEVh3GuxypYFkVbb1DL EksIof/em3Wwi2/mn8DN6tb6iOYf4XsuZdjpmK2P+MmOLQilc0tkVANnMS++swWthmtv yNJlRpzh0LbLLcaIqYrFsvlO0YG6N2/Id54MsYfCSYoASAtJJyXMfvjGgVSiVqXMU6qe BdgcMbDaQq+2lOalbHLXdg2imR2Di6hvuUswTweJ0MkRVWPzXfpn9PFbDK6afMB6c3JM tGTdTL28eA96++0ddY4QiZMP2s97hxZaetL6c/QIIsPGKhmg65xOIItRGnk0otoLmqWl 5eZQ== X-Gm-Message-State: AOJu0YwkKYGFQEcCOP/Nx9JO0fh21VxvAhwN49xerHvjupqtYF81iPye /mXOttXmvn6+ZguWzoAxoiqrlUA3fh2e90L9tXoS45/8I+X586WdQvEWBh3rA18HKE2rrNsWPVB z X-Gm-Gg: ASbGncsow6kdue2008z48IW9IVfHEiEGIpEWG6sPAHTWWyiEHASheR+bTqceaFYmB09 grblZhlZ+IMmsdhW1wb839AUBkZ5uzlYOaRp8j2UUrpYO5L0B8pIr6h7SivHulVzf0yUl5F/VmV XxMzs5b3Xq3u8Zeanef33G3+cNCpLVGLCJ45En9VrFYUlBzoaqThtC0eqAJd2zASYI1P8czHA9t y/PwkSgRS/PPwKqyAJ48ohIGQUhOwg4an9XT5gDOf+Nj8dTszg+ESD20naI81UnHVLstVsWbRNn 88rKSnQhV42aByhvDapNK2Krk6PfgbaYS/956bDlwqQ5fJQ= X-Google-Smtp-Source: AGHT+IHqiZTa8l5XmYTQbepUTIeSsWxZ0UpC5KQcpDsbUHpfJYLZuZw9nPhyB9s5LkG/l70qn8OWWw== X-Received: by 2002:a17:90b:1b0b:b0:2ee:cddd:2454 with SMTP id 98e67ed59e1d1-2fc0e4b9e47mr1251934a91.15.1739397722792; Wed, 12 Feb 2025 14:02:02 -0800 (PST) Received: from stoup.. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fbf98b4c52sm1964837a91.4.2025.02.12.14.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2025 14:02:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 8/9] target/microblaze: Drop DisasContext.r0 Date: Wed, 12 Feb 2025 14:01:54 -0800 Message-ID: <20250212220155.1147144-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212220155.1147144-1-richard.henderson@linaro.org> References: <20250212220155.1147144-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Return a constant 0 from reg_for_read, and a new temporary from reg_for_write. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/microblaze/translate.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a1d81b0166..5750c45dac 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -63,9 +63,6 @@ typedef struct DisasContext { DisasContextBase base; const MicroBlazeCPUConfig *cfg; - TCGv_i32 r0; - bool r0_set; - /* Decoder. */ uint32_t ext_imm; unsigned int tb_flags; @@ -179,14 +176,7 @@ static TCGv_i32 reg_for_read(DisasContext *dc, int reg) if (likely(reg != 0)) { return cpu_R[reg]; } - if (!dc->r0_set) { - if (dc->r0 == NULL) { - dc->r0 = tcg_temp_new_i32(); - } - tcg_gen_movi_i32(dc->r0, 0); - dc->r0_set = true; - } - return dc->r0; + return tcg_constant_i32(0); } static TCGv_i32 reg_for_write(DisasContext *dc, int reg) @@ -194,10 +184,7 @@ static TCGv_i32 reg_for_write(DisasContext *dc, int reg) if (likely(reg != 0)) { return cpu_R[reg]; } - if (dc->r0 == NULL) { - dc->r0 = tcg_temp_new_i32(); - } - return dc->r0; + return tcg_temp_new_i32(); } static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects, @@ -1621,8 +1608,6 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cfg = &cpu->cfg; dc->tb_flags = dc->base.tb->flags; dc->ext_imm = dc->base.tb->cs_base; - dc->r0 = NULL; - dc->r0_set = false; dc->mem_index = cpu_mmu_index(cs, false); dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER; dc->jmp_dest = -1; @@ -1660,11 +1645,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) trap_illegal(dc, true); } - if (dc->r0) { - dc->r0 = NULL; - dc->r0_set = false; - } - /* Discard the imm global when its contents cannot be used. */ if ((dc->tb_flags & ~dc->tb_flags_to_set) & IMM_FLAG) { tcg_gen_discard_i32(cpu_imm); From patchwork Wed Feb 12 22:01:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13972474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2060AC021A4 for ; Wed, 12 Feb 2025 22:03:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiKo8-0006po-7v; Wed, 12 Feb 2025 17:02:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiKo2-0006nJ-M1 for qemu-devel@nongnu.org; Wed, 12 Feb 2025 17:02:06 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tiKo0-0004TQ-O2 for qemu-devel@nongnu.org; Wed, 12 Feb 2025 17:02:06 -0500 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-2f9f6a2fa8dso385368a91.1 for ; Wed, 12 Feb 2025 14:02:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739397723; x=1740002523; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VtWffR29W1lq+y/owEw/cHjeXtzTBtEfWnTjBGb0sKA=; b=yXM1i+HQuFXu8WNXPotrVlc6u4IzdciHjd2O0Eq7jXcq9XyhAARSyuUFBI2BEfUDzA NrD2tVILzTIIXu7NEBLFNN4uY0unes76UNTfXN8QHir7Cb2gDuRgxho2Sz4pi/HDOylY uHc6ismWbV+CIwBLtJJRHaAoOglP5+lgFm5YlnchE71cgy3AjfxcPKV9ecJXs/qR/xOp 2d/09JENJFMATw8VevQXeym5KEy/wSol1N8/QlhbT2HanSpes4kYyvBv87/ubfAZ7qM1 DIIDS5t34Q3ygTwhnK2exQwpS/vbl3q0wr475T0kmsHlSRaJ0AclHNLm04+orlt/5Yy7 j14w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739397723; x=1740002523; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VtWffR29W1lq+y/owEw/cHjeXtzTBtEfWnTjBGb0sKA=; b=GE4+dVGhAaxpQajYkoAgncIf/KN3ccgSWyjO8XeeQKtPs97WwFykv/4+WY4bGsNvpB lO6muOkke9iM6HS5ZnERKXZeC/1ZK5jJMGUOh3CiBf7a5ALZwYo84O98gpduP97qjNu1 mXB6k1KSCimRqQUyScc4bwE2cgDV6tThw96CDJzcSD4Q9flGJ12kVnn9zsgpdhk/NSeq 1XLY12sHFq0frL+HECGIIfH/IPE0Bqo4n9UYcP7pvgsXwCs01wRy0LqZwgXvG3Lvp8fM jB7ePGE0nLzSUCSB/he+l4Mgkk43dPJ4rW7W7Yr57yM/DBRPSrZNghYVZKvMcf0a6rwQ PPGg== X-Gm-Message-State: AOJu0YxShRqhSM2JP3hOBYNkxECdbZboABcZr55pc9o1pR+I5vG/rYFL 49gNh74Zb0JryVOFy7vdICW29LuJiNfNG5orVw50lhATCTrF2+65H0nLUzLvR+04c68qkm3P1EU u X-Gm-Gg: ASbGncuK7KsUxE2pDaR6cp4cJ3DGeGxAsKSE6mwGuZCO4rXTf6cNObYLmCskEIVQ1nM /d1K2Z5ARkdGKUqTi8Bp410jK48r/K9zHjBN5j8cBYLJ54dWo+8HWyiwYYberAI2l/f6taVlXGK eqEs33R+ExbmpHHttsoLVCwABF4vlWwiifBiwTYiUcpQ+s71YQX5M/9nu+cC3qKACUrZL3X7M3D ei/XfBx7kpBWH4s5PWbXcO9WUvRmXV9adf1ek5Tso9w9TW2uFZw++ysaeKJvFzMuh392AV2YLck rZbN1xZX58JPl81+mOEmmj1NDmuBZ0VCDTFI9RgEHWdG85s= X-Google-Smtp-Source: AGHT+IGft4rV9jvl9sq3NbDFnE0+RDbuPHrHsX814KP8PX/t2Ge5z+GmHLySvXkb4aQKcj9bYZiVCw== X-Received: by 2002:a17:90a:e185:b0:2ee:8430:b831 with SMTP id 98e67ed59e1d1-2fbf5bc0249mr8048022a91.2.1739397723371; Wed, 12 Feb 2025 14:02:03 -0800 (PST) Received: from stoup.. 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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fbf98b4c52sm1964837a91.4.2025.02.12.14.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2025 14:02:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 9/9] target/microblaze: Simplify compute_ldst_addr_type{a,b} Date: Wed, 12 Feb 2025 14:01:55 -0800 Message-ID: <20250212220155.1147144-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212220155.1147144-1-richard.henderson@linaro.org> References: <20250212220155.1147144-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Require TCGv_i32 and TCGv be identical, so drop the extensions. Return constants when possible instead of a mov into a temporary. Return register inputs unchanged when possible. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/microblaze/translate.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 5750c45dac..5f3b94e683 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -612,19 +612,18 @@ DO_TYPEBI(xori, false, tcg_gen_xori_i32) static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb) { - TCGv ret = tcg_temp_new(); + TCGv ret; /* If any of the regs is r0, set t to the value of the other reg. */ if (ra && rb) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]); - tcg_gen_extu_i32_tl(ret, tmp); + ret = tcg_temp_new_i32(); + tcg_gen_add_i32(ret, cpu_R[ra], cpu_R[rb]); } else if (ra) { - tcg_gen_extu_i32_tl(ret, cpu_R[ra]); + ret = cpu_R[ra]; } else if (rb) { - tcg_gen_extu_i32_tl(ret, cpu_R[rb]); + ret = cpu_R[rb]; } else { - tcg_gen_movi_tl(ret, 0); + ret = tcg_constant_i32(0); } if ((ra == 1 || rb == 1) && dc->cfg->stackprot) { @@ -635,15 +634,16 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb) static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) { - TCGv ret = tcg_temp_new(); + TCGv ret; /* If any of the regs is r0, set t to the value of the other reg. */ - if (ra) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_addi_i32(tmp, cpu_R[ra], imm); - tcg_gen_extu_i32_tl(ret, tmp); + if (ra && imm) { + ret = tcg_temp_new_i32(); + tcg_gen_addi_i32(ret, cpu_R[ra], imm); + } else if (ra) { + ret = cpu_R[ra]; } else { - tcg_gen_movi_tl(ret, (uint32_t)imm); + ret = tcg_constant_i32(imm); } if (ra == 1 && dc->cfg->stackprot) {