From patchwork Wed Feb 12 22:13:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 13972503 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C7090205AC3; Wed, 12 Feb 2025 22:13:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739398404; cv=none; b=UmGjjPQNQ/M5qT06qPZo+GPvcBtbaVuFdII3eSM2GFdWCnfJhVx4DXExCZTIuPmbeEay1FyffGKt3IjObhvjxoPDyyErLhRY38tGbn7d7XfU/zUqAs0vQTir3pVTCKRLmNlp9Bszp9eyUO8z41cGYWTreuM0tjOWWpJpS9zMy5Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739398404; c=relaxed/simple; bh=d4/O4IqwTDvm3lELgZsxQaM1SWdPgW8MiGY50WKq1wY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=J00t9bQ494o6Nf/0ZyreXk+qaW35/lhEv7VK4jqOxwQuH03K2mnNw9p63cs1wWliTWXxrYgi9tEfxXy3TVQ74ZX7SivMGITZcR6VzWMonp6g09ufq5wRjon0WvLhDvhuM0BM8zpRYiDVnlWOPf0v0Fjpe3kr1X7rRan8qWTtPq4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: TfjP905zR5OWWa3k3WZmiQ== X-CSE-MsgGUID: a6emqeTeT6yzwy2XTa7Uag== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Feb 2025 07:13:21 +0900 Received: from mulinux.example.org (unknown [10.226.93.8]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 79DF340AACC4; Thu, 13 Feb 2025 07:13:17 +0900 (JST) From: Fabrizio Castro To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven Cc: Fabrizio Castro , Magnus Damm , Biju Das , Wolfram Sang , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Lad Prabhakar Subject: [PATCH v2 2/7] dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H Date: Wed, 12 Feb 2025 22:13:00 +0000 Message-Id: <20250212221305.431716-3-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250212221305.431716-1-fabrizio.castro.jz@renesas.com> References: <20250212221305.431716-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Make sure we don't allow for the clocks, clock-names, resets, reset-names. and power-domains properties for the Renesas RZ/A1H SoC because its DMAC doesn't have clocks, resets, and power domains. Fixes: 209efec19c4c ("dt-bindings: dma: rz-dmac: Document RZ/A1H SoC") Signed-off-by: Fabrizio Castro --- v1->v2: * No change. --- .../devicetree/bindings/dma/renesas,rz-dmac.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index b356251de5a8..82de3b927479 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -112,6 +112,14 @@ allOf: - resets - reset-names + else: + properties: + clocks: false + clock-names: false + power-domains: false + resets: false + reset-names: false + additionalProperties: false examples: From patchwork Wed Feb 12 22:13:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 13972504 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3DD8B20408E; Wed, 12 Feb 2025 22:13:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739398408; cv=none; b=jgMFSk3m3ijhBpcfpu6Or/rpnsckRDZdnx1mo/pq+eobXcSLldaKUMLiGoBWi/ES6Jos/IBD/edEjIi0qabtL7YfDyD3/N5jnGPTUBHCcekI/rfm+XPMZRX9pZtUXxcXixQy6RPfetKl7vmex8eNNd1Z6wu4YVGKzlVv+7cQsmI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739398408; c=relaxed/simple; bh=f4MBlcQb3sbXfojEx7n3AR2nbWpUF8H9jvcrxXz03PM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=of9+OIYJBpi619ojCRM49qvcD1mD/vji70b1LmsvYotuW3kQMMNl9Vur9tZ2bHrZjiA2MTi/WJK7o7nyVaFPZhzeXapddhqDxN1FHK1S6w55twbCHmn9HafktJ1qVE5DnQPja7kQzRgboF1Rn1vlOqgbjbMKnteChpuT+/HS34w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: AjB7x6MjTaiJym0sAlMitg== X-CSE-MsgGUID: XG6RUKLcT3yAhp2Jxa+V8Q== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Feb 2025 07:13:26 +0900 Received: from mulinux.example.org (unknown [10.226.93.8]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 2F2A740AACBB; Thu, 13 Feb 2025 07:13:21 +0900 (JST) From: Fabrizio Castro To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven Cc: Fabrizio Castro , Magnus Damm , Biju Das , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Lad Prabhakar Subject: [PATCH v2 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs Date: Wed, 12 Feb 2025 22:13:01 +0000 Message-Id: <20250212221305.431716-4-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250212221305.431716-1-fabrizio.castro.jz@renesas.com> References: <20250212221305.431716-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document the Renesas RZ/V2H(P) family of SoCs DMAC block. The Renesas RZ/V2H(P) DMAC is very similar to the one found on the Renesas RZ/G2L family of SoCs, but there are some differences: * It only uses one register area * It only uses one clock * It only uses one reset * Instead of using MID/IRD it uses REQ NO/ACK NO * It is connected to the Interrupt Control Unit (ICU) Signed-off-by: Fabrizio Castro --- v1->v2: * Removed RZ/V2H DMAC example. * Improved the readability of the `if` statement. --- .../bindings/dma/renesas,rz-dmac.yaml | 107 +++++++++++++++--- 1 file changed, 89 insertions(+), 18 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index 82de3b927479..4b89d199c022 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -11,19 +11,23 @@ maintainers: properties: compatible: - items: - - enum: - - renesas,r7s72100-dmac # RZ/A1H - - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five - - renesas,r9a07g044-dmac # RZ/G2{L,LC} - - renesas,r9a07g054-dmac # RZ/V2L - - renesas,r9a08g045-dmac # RZ/G3S - - const: renesas,rz-dmac + oneOf: + - items: + - enum: + - renesas,r7s72100-dmac # RZ/A1H + - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five + - renesas,r9a07g044-dmac # RZ/G2{L,LC} + - renesas,r9a07g054-dmac # RZ/V2L + - renesas,r9a08g045-dmac # RZ/G3S + - const: renesas,rz-dmac + + - const: renesas,r9a09g057-dmac # RZ/V2H(P) reg: items: - description: Control and channel register block - description: DMA extended resource selector block + minItems: 1 interrupts: maxItems: 17 @@ -52,6 +56,7 @@ properties: items: - description: DMA main clock - description: DMA register access clock + minItems: 1 clock-names: items: @@ -61,14 +66,22 @@ properties: '#dma-cells': const: 1 description: - The cell specifies the encoded MID/RID values of the DMAC port - connected to the DMA client and the slave channel configuration - parameters. + For the RZ/A1H, RZ/Five, RZ/G2{L,LC,UL}, RZ/V2L, and RZ/G3S SoCs, the cell + specifies the encoded MID/RID values of the DMAC port connected to the + DMA client and the slave channel configuration parameters. bits[0:9] - Specifies MID/RID value bit[10] - Specifies DMA request high enable (HIEN) bit[11] - Specifies DMA request detection type (LVL) bits[12:14] - Specifies DMAACK output mode (AM) bit[15] - Specifies Transfer Mode (TM) + For the RZ/V2H(P) SoC the cell specifies the REQ NO, the ACK NO, and the + slave channel configuration parameters. + bits[0:9] - Specifies the REQ NO + bits[10:16] - Specifies the ACK NO + bit[17] - Specifies DMA request high enable (HIEN) + bit[18] - Specifies DMA request detection type (LVL) + bits[19:21] - Specifies DMAACK output mode (AM) + bit[22] - Specifies Transfer Mode (TM) dma-channels: const: 16 @@ -80,12 +93,29 @@ properties: items: - description: Reset for DMA ARESETN reset terminal - description: Reset for DMA RST_ASYNC reset terminal + minItems: 1 reset-names: items: - const: arst - const: rst_async + renesas,icu: + description: + On the RZ/V2H(P) SoC configures the ICU to which the DMAC is connected to. + It must contain the phandle to the ICU, and the index of the DMAC as seen + from the ICU (e.g. parameter k from register ICU_DMkSELy). + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the ICU node. + - description: The DMAC index. + 4 for DMAC0 + 0 for DMAC1 + 1 for DMAC2 + 2 for DMAC3 + 3 for DMAC4 + required: - compatible - reg @@ -98,13 +128,25 @@ allOf: - $ref: dma-controller.yaml# - if: - not: - properties: - compatible: - contains: - enum: - - renesas,r7s72100-dmac + properties: + compatible: + contains: + enum: + - renesas,r9a07g043-dmac + - renesas,r9a07g044-dmac + - renesas,r9a07g054-dmac + - renesas,r9a08g045-dmac then: + properties: + reg: + minItems: 2 + clocks: + minItems: 2 + resets: + minItems: 2 + + renesas,icu: false + required: - clocks - clock-names @@ -112,13 +154,42 @@ allOf: - resets - reset-names - else: + - if: + properties: + compatible: + contains: + const: renesas,r7s72100-dmac + then: properties: clocks: false clock-names: false power-domains: false resets: false reset-names: false + renesas,icu: false + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-dmac + then: + properties: + reg: + maxItems: 1 + clocks: + maxItems: 1 + resets: + maxItems: 1 + + clock-names: false + reset-names: false + + required: + - clocks + - power-domains + - renesas,icu + - resets additionalProperties: false From patchwork Wed Feb 12 22:13:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 13972505 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 97717261579; Wed, 12 Feb 2025 22:13:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739398414; cv=none; b=ptyGlB5/09GxSYliuuGRNktiogjnOamnoEw5bMnOZBQ961kxLrf+4VRxCfC4LRhz/q4WpsWxVfKcpNrhOUEzJOJidQ15b4Q9sYhUQBsDy/qNmsyzwBPidgpBknHLFnCBQIVD80NpDNttdJ0JN2xGM6rr3JiaTQevUt77q2LZvts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739398414; c=relaxed/simple; bh=ZoVCny/kEfXbnFU+Akx9N185+w6wZeQmMk7AAeyEDs4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=P+RHQS7/JnSixfkEpm7fqo9eWu+80E+9yz5qRdQ7iUIEjpBj+LLwW+smZ5hR/helZ987ldOKT9KlMskpgoHwbGIq4af5mzHoHAXLMW8lK28EwO0I3XgasehTvaPLs4J3p0SestI0gA9dNP30nItbnji0mInVHQyeui1nul52nXE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: xi9kV5w1TgCCJ7oTyA45ZQ== X-CSE-MsgGUID: apy+0GLHR26dNCuqcefxrg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Feb 2025 07:13:32 +0900 Received: from mulinux.example.org (unknown [10.226.93.8]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 612E140AACC4; Thu, 13 Feb 2025 07:13:29 +0900 (JST) From: Fabrizio Castro To: Vinod Koul , Geert Uytterhoeven Cc: Fabrizio Castro , Wolfram Sang , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Lad Prabhakar , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 5/7] dmaengine: sh: rz-dmac: Allow for multiple DMACs Date: Wed, 12 Feb 2025 22:13:03 +0000 Message-Id: <20250212221305.431716-6-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250212221305.431716-1-fabrizio.castro.jz@renesas.com> References: <20250212221305.431716-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 dma_request_channel calls into __dma_request_channel with NULL as value for np, which won't allow for the selection of the correct DMAC when multiple DMACs are available. Switch to using __dma_request_channel directly so that we can choose the desired DMA for the channel. This is in preparation of adding DMAC support for the Renesas RZ/V2H(P) and similar SoCs. Signed-off-by: Fabrizio Castro --- v1->v2: * No change. --- drivers/dma/sh/rz-dmac.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 9235db551026..d7a4ce28040b 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -748,7 +748,8 @@ static struct dma_chan *rz_dmac_of_xlate(struct of_phandle_args *dma_spec, dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); - return dma_request_channel(mask, rz_dmac_chan_filter, dma_spec); + return __dma_request_channel(&mask, rz_dmac_chan_filter, dma_spec, + ofdma->of_node); } /* From patchwork Wed Feb 12 22:13:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 13972506 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BDA1B261579; Wed, 12 Feb 2025 22:13:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739398419; cv=none; b=irIHU9Ik1MVcadquo5I53bvhKBFQAn88a1IBoPpKIVz7dQwhTTPIlXqna3us+4Vo/s1Q3maE4Og3+j14wlizKumuCl/tewkGSnRTZHkDJjC/3lbNkUtCwoF1+PeGezYCBeitwQiduQGXXaOw0xgxSGjNKuJ3/9u+qtvH7DRsmk0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739398419; c=relaxed/simple; bh=bA/myihmd5etLQnT0hudcQ1HAKVQHuqnvOhZrB0pBx8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=i1fHunWSZB3Do+sAkn1Hs5OxuE6nr7VGOtjoEyq9TXc4xiWLGkdWSa9uD6MeUA6jrmsdrGlCI77aXylT16noG6l0XxCYHOdHKp8ceR+BNh+fioibsmO0DoyT7Ch+3P/UsZtehuboaLHEKZD4oIpkS+bzxtaZIQbqUv85HguEg4s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: 7Bc8cR0cRTWsyRBY5X2LsA== X-CSE-MsgGUID: Zux17oMOTQmcO7XbLsY51Q== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Feb 2025 07:13:36 +0900 Received: from mulinux.example.org (unknown [10.226.93.8]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 00C4C40AACD7; Thu, 13 Feb 2025 07:13:32 +0900 (JST) From: Fabrizio Castro To: Vinod Koul , Geert Uytterhoeven Cc: Fabrizio Castro , Magnus Damm , Philipp Zabel , Wolfram Sang , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Lad Prabhakar Subject: [PATCH v2 6/7] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support Date: Wed, 12 Feb 2025 22:13:04 +0000 Message-Id: <20250212221305.431716-7-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250212221305.431716-1-fabrizio.castro.jz@renesas.com> References: <20250212221305.431716-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The DMAC IP found on the Renesas RZ/V2H(P) family of SoCs is similar to the version found on the Renesas RZ/G2L family of SoCs, but there are some differences: * It only uses one register area * It only uses one clock * It only uses one reset * Instead of using MID/IRD it uses REQ NO/ACK NO * It is connected to the Interrupt Control Unit (ICU) * On the RZ/G2L there is only 1 DMAC, on the RZ/V2H(P) there are 5 Add specific support for the Renesas RZ/V2H(P) family of SoC by tackling the aforementioned differences. Signed-off-by: Fabrizio Castro --- v1->v2: * Switched to new macros for minimum values. --- drivers/dma/sh/Kconfig | 1 + drivers/dma/sh/rz-dmac.c | 164 +++++++++++++++++++++++++++++++++++---- 2 files changed, 150 insertions(+), 15 deletions(-) diff --git a/drivers/dma/sh/Kconfig b/drivers/dma/sh/Kconfig index 6ea5a880b433..020cf941abc7 100644 --- a/drivers/dma/sh/Kconfig +++ b/drivers/dma/sh/Kconfig @@ -53,6 +53,7 @@ config RZ_DMAC depends on ARCH_R7S72100 || ARCH_RZG2L || COMPILE_TEST select RENESAS_DMA select DMA_VIRTUAL_CHANNELS + select RENESAS_RZV2H_ICU help This driver supports the general purpose DMA controller typically found in the Renesas RZ SoC variants. diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index d7a4ce28040b..24a8c6a337d5 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,11 @@ #include "../dmaengine.h" #include "../virt-dma.h" +enum rz_dmac_type { + RZ_DMAC_RZG2L, + RZ_DMAC_RZV2H, +}; + enum rz_dmac_prep_type { RZ_DMAC_DESC_MEMCPY, RZ_DMAC_DESC_SLAVE_SG, @@ -85,20 +91,32 @@ struct rz_dmac_chan { struct rz_lmdesc *tail; dma_addr_t base_dma; } lmdesc; + + /* RZ/V2H ICU related signals */ + u16 req_no; + u8 ack_no; }; #define to_rz_dmac_chan(c) container_of(c, struct rz_dmac_chan, vc.chan) +struct rz_dmac_icu { + struct platform_device *pdev; + u8 dmac_index; +}; + struct rz_dmac { struct dma_device engine; struct device *dev; struct reset_control *rstc; + struct rz_dmac_icu icu; void __iomem *base; void __iomem *ext_base; unsigned int n_channels; struct rz_dmac_chan *channels; + enum rz_dmac_type type; + DECLARE_BITMAP(modules, 1024); }; @@ -167,6 +185,22 @@ struct rz_dmac { #define RZ_DMAC_MAX_CHANNELS 16 #define DMAC_NR_LMDESC 64 +/* RZ/V2H ICU related */ +#define RZV2H_REQ_NO_MASK GENMASK(9, 0) +#define RZV2H_ACK_NO_MASK GENMASK(16, 10) +#define RZV2H_HIEN_MASK BIT(17) +#define RZV2H_LVL_MASK BIT(18) +#define RZV2H_AM_MASK GENMASK(21, 19) +#define RZV2H_TM_MASK BIT(22) +#define RZV2H_EXTRACT_REQ_NO(x) FIELD_GET(RZV2H_REQ_NO_MASK, (x)) +#define RZV2H_EXTRACT_ACK_NO(x) FIELD_GET(RZV2H_ACK_NO_MASK, (x)) +#define RZVH2_EXTRACT_CHCFG(x) ((FIELD_GET(RZV2H_HIEN_MASK, (x)) << 5) | \ + (FIELD_GET(RZV2H_LVL_MASK, (x)) << 6) | \ + (FIELD_GET(RZV2H_AM_MASK, (x)) << 8) | \ + (FIELD_GET(RZV2H_TM_MASK, (x)) << 22)) + +#define RZV2H_MAX_DMAC_INDEX 4 + /* * ----------------------------------------------------------------------------- * Device access @@ -324,7 +358,15 @@ static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel) lmdesc->chext = 0; lmdesc->header = HEADER_LV; - rz_dmac_set_dmars_register(dmac, channel->index, 0); + if (dmac->type == RZ_DMAC_RZG2L) { + rz_dmac_set_dmars_register(dmac, channel->index, 0); + } else { + rzv2h_icu_register_dma_req_ack(dmac->icu.pdev, + dmac->icu.dmac_index, + channel->index, + RZV2H_ICU_DMAC_REQ_NO_DEFAULT, + RZV2H_ICU_DMAC_ACK_NO_DEFAULT); + } channel->chcfg = chcfg; channel->chctrl = CHCTRL_STG | CHCTRL_SETEN; @@ -375,7 +417,15 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel) channel->lmdesc.tail = lmdesc; - rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid); + if (dmac->type == RZ_DMAC_RZG2L) { + rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid); + } else { + rzv2h_icu_register_dma_req_ack(dmac->icu.pdev, + dmac->icu.dmac_index, + channel->index, channel->req_no, + channel->ack_no); + } + channel->chctrl = CHCTRL_SETEN; } @@ -452,9 +502,15 @@ static void rz_dmac_free_chan_resources(struct dma_chan *chan) list_splice_tail_init(&channel->ld_active, &channel->ld_free); list_splice_tail_init(&channel->ld_queue, &channel->ld_free); - if (channel->mid_rid >= 0) { - clear_bit(channel->mid_rid, dmac->modules); - channel->mid_rid = -EINVAL; + if (dmac->type == RZ_DMAC_RZG2L) { + if (channel->mid_rid >= 0) { + clear_bit(channel->mid_rid, dmac->modules); + channel->mid_rid = -EINVAL; + } + } else { + clear_bit(channel->req_no, dmac->modules); + channel->req_no = RZV2H_ICU_DMAC_REQ_NO_DEFAULT; + channel->ack_no = RZV2H_ICU_DMAC_ACK_NO_DEFAULT; } spin_unlock_irqrestore(&channel->vc.lock, flags); @@ -647,7 +703,15 @@ static void rz_dmac_device_synchronize(struct dma_chan *chan) if (ret < 0) dev_warn(dmac->dev, "DMA Timeout"); - rz_dmac_set_dmars_register(dmac, channel->index, 0); + if (dmac->type == RZ_DMAC_RZG2L) { + rz_dmac_set_dmars_register(dmac, channel->index, 0); + } else { + rzv2h_icu_register_dma_req_ack(dmac->icu.pdev, + dmac->icu.dmac_index, + channel->index, + RZV2H_ICU_DMAC_REQ_NO_DEFAULT, + RZV2H_ICU_DMAC_ACK_NO_DEFAULT); + } } /* @@ -727,13 +791,30 @@ static bool rz_dmac_chan_filter(struct dma_chan *chan, void *arg) struct rz_dmac *dmac = to_rz_dmac(chan->device); struct of_phandle_args *dma_spec = arg; u32 ch_cfg; + u16 req_no; + + if (dmac->type == RZ_DMAC_RZG2L) { + channel->mid_rid = dma_spec->args[0] & MID_RID_MASK; + ch_cfg = (dma_spec->args[0] & CHCFG_MASK) >> 10; + channel->chcfg = CHCFG_FILL_TM(ch_cfg) | CHCFG_FILL_AM(ch_cfg) | + CHCFG_FILL_LVL(ch_cfg) | CHCFG_FILL_HIEN(ch_cfg); + + return !test_and_set_bit(channel->mid_rid, dmac->modules); + } + + req_no = RZV2H_EXTRACT_REQ_NO(dma_spec->args[0]); + if (req_no >= RZV2H_ICU_DMAC_REQ_NO_MIN_FIX_OUTPUT) + return false; + + channel->req_no = req_no; + + channel->ack_no = RZV2H_EXTRACT_ACK_NO(dma_spec->args[0]); + if (channel->ack_no >= RZV2H_ICU_DMAC_ACK_NO_MIN_FIX_OUTPUT) + channel->ack_no = RZV2H_ICU_DMAC_ACK_NO_DEFAULT; - channel->mid_rid = dma_spec->args[0] & MID_RID_MASK; - ch_cfg = (dma_spec->args[0] & CHCFG_MASK) >> 10; - channel->chcfg = CHCFG_FILL_TM(ch_cfg) | CHCFG_FILL_AM(ch_cfg) | - CHCFG_FILL_LVL(ch_cfg) | CHCFG_FILL_HIEN(ch_cfg); + channel->chcfg = RZVH2_EXTRACT_CHCFG(dma_spec->args[0]); - return !test_and_set_bit(channel->mid_rid, dmac->modules); + return !test_and_set_bit(channel->req_no, dmac->modules); } static struct dma_chan *rz_dmac_of_xlate(struct of_phandle_args *dma_spec, @@ -769,6 +850,8 @@ static int rz_dmac_chan_probe(struct rz_dmac *dmac, channel->index = index; channel->mid_rid = -EINVAL; + channel->req_no = RZV2H_ICU_DMAC_REQ_NO_DEFAULT; + channel->ack_no = RZV2H_ICU_DMAC_ACK_NO_DEFAULT; /* Request the channel interrupt. */ scnprintf(pdev_irqname, sizeof(pdev_irqname), "ch%u", index); @@ -824,6 +907,40 @@ static int rz_dmac_chan_probe(struct rz_dmac *dmac, return 0; } +static int rz_dmac_parse_of_icu(struct device *dev, struct rz_dmac *dmac) +{ + struct device_node *icu_np, *np = dev->of_node; + struct of_phandle_args args; + uint32_t dmac_index; + int ret; + + ret = of_parse_phandle_with_fixed_args(np, "renesas,icu", 1, 0, &args); + if (ret) + return ret; + + icu_np = args.np; + dmac_index = args.args[0]; + + if (dmac_index > RZV2H_MAX_DMAC_INDEX) { + dev_err(dev, "DMAC index %u invalid.\n", dmac_index); + ret = -EINVAL; + goto free_icu_np; + } + + dmac->icu.pdev = of_find_device_by_node(icu_np); + if (!dmac->icu.pdev) { + ret = -ENODEV; + goto free_icu_np; + } + + dmac->icu.dmac_index = dmac_index; + +free_icu_np: + of_node_put(icu_np); + + return ret; +} + static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac) { struct device_node *np = dev->of_node; @@ -859,6 +976,7 @@ static int rz_dmac_probe(struct platform_device *pdev) dmac->dev = &pdev->dev; platform_set_drvdata(pdev, dmac); + dmac->type = (enum rz_dmac_type)of_device_get_match_data(dmac->dev); ret = rz_dmac_parse_of(&pdev->dev, dmac); if (ret < 0) @@ -874,9 +992,15 @@ static int rz_dmac_probe(struct platform_device *pdev) if (IS_ERR(dmac->base)) return PTR_ERR(dmac->base); - dmac->ext_base = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(dmac->ext_base)) - return PTR_ERR(dmac->ext_base); + if (dmac->type == RZ_DMAC_RZG2L) { + dmac->ext_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(dmac->ext_base)) + return PTR_ERR(dmac->ext_base); + } else { + ret = rz_dmac_parse_of_icu(&pdev->dev, dmac); + if (ret) + return ret; + } /* Register interrupt handler for error */ irq = platform_get_irq_byname(pdev, irqname); @@ -991,10 +1115,20 @@ static void rz_dmac_remove(struct platform_device *pdev) reset_control_assert(dmac->rstc); pm_runtime_put(&pdev->dev); pm_runtime_disable(&pdev->dev); + + if (dmac->type == RZ_DMAC_RZV2H) + platform_device_put(dmac->icu.pdev); } static const struct of_device_id of_rz_dmac_match[] = { - { .compatible = "renesas,rz-dmac", }, + { + .compatible = "renesas,r9a09g057-dmac", + .data = (void *) RZ_DMAC_RZV2H + }, + { + .compatible = "renesas,rz-dmac", + .data = (void *) RZ_DMAC_RZG2L + }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, of_rz_dmac_match);