From patchwork Fri Feb 14 07:43:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Tseng X-Patchwork-Id: 13974580 X-Patchwork-Delegate: viresh.linux@gmail.com Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 531C32153E1; Fri, 14 Feb 2025 07:44:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739519043; cv=none; b=Lr7I2yunXNkrL45g+vYTABtwCr43jHhB305F/pdLPYfR1Xl2I9nS5sDpD9q0HzTfS0y7/hLD3bjqDVHQ+PI7irNSoMccPFUZQTH17iAIiKciap+YvzRHwhwaN6O0uumZ55cKzrky/1TCddQqZbL8EhuusKbK2nO5GvQu98aamEA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739519043; c=relaxed/simple; bh=dpnzSrNVQ5Sn2enMYiJ+zZux/fL5MEa7//LADi4zEes=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=arRrRnq+yPXXfKK8nuFA0uh6e0TJGyM6sudRQ16kn5vpRlwrGKD12M0Hg/S6Z6cOYQJC5kvF0BqfiW6B4xUUYZe40+HFMCeg2u1cmgbBfgtHiQbzwSEj2a/lcmnQ/hRBYJGmrNwYpgzGMsEGU2ofeZAhIhvU7HFziH3jyxlwyKs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=fWFzqQRG; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="fWFzqQRG" X-UUID: 7134b6f2eaa711efbd192953cf12861f-20250214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=yGx9P0mJqQozpBOCmZwQ+5UxE4Q0iSbhG8oMKQTzU8s=; b=fWFzqQRGObW4P4gC1w8gwsRWpBKonwEy8O2vypG0kwi2GrAZNkAOiKlM7k6ymwIhXiXlGU6D+r9g4o5uLMQL5GlPEkmQp+OzT/pd5bqJJzqBX21Stu7TCh99eiz3LCmZNk6z4CZcPwAT9wx2eCihsYbGFLEU94O4CKK6edWKcDM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46,REQID:76351ebd-f443-4171-8f1d-209379665dbf,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:60aa074,CLOUDID:09de5b88-f9ab-4ac1-951b-e3a689bed90c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 7134b6f2eaa711efbd192953cf12861f-20250214 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 663570915; Fri, 14 Feb 2025 15:43:55 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Fri, 14 Feb 2025 15:43:53 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Fri, 14 Feb 2025 15:43:53 +0800 From: Mark Tseng To: "Rafael J . Wysocki" , Viresh Kumar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Subject: [PATCH v3 1/3] cpufreq: mediatek: using global lock avoid race condition Date: Fri, 14 Feb 2025 15:43:32 +0800 Message-ID: <20250214074353.1169864-2-chun-jen.tseng@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250214074353.1169864-1-chun-jen.tseng@mediatek.com> References: <20250214074353.1169864-1-chun-jen.tseng@mediatek.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In mtk_cpufreq_set_target() is re-enter function but the mutex lock decalre in mtk_cpu_dvfs_info structure for each policy. It should change to global variable for critical session avoid race condition with 2 or more policy. add mtk_cpufreq_get() replace cpufreq_generic_get() and use global lock avoid return wrong clock. Signed-off-by: Mark Tseng --- drivers/cpufreq/mediatek-cpufreq.c | 39 ++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 2656b88db378..07d5958e106a 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -49,8 +49,6 @@ struct mtk_cpu_dvfs_info { bool need_voltage_tracking; int vproc_on_boot; int pre_vproc; - /* Avoid race condition for regulators between notify and policy */ - struct mutex reg_lock; struct notifier_block opp_nb; unsigned int opp_cpu; unsigned long current_freq; @@ -59,6 +57,9 @@ struct mtk_cpu_dvfs_info { bool ccifreq_bound; }; +/* Avoid race condition for regulators between notify and policy */ +static DEFINE_MUTEX(mtk_policy_lock); + static struct platform_device *cpufreq_pdev; static LIST_HEAD(dvfs_info_list); @@ -209,12 +210,12 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, long freq_hz, pre_freq_hz; int vproc, pre_vproc, inter_vproc, target_vproc, ret; + mutex_lock(&mtk_policy_lock); + inter_vproc = info->intermediate_voltage; pre_freq_hz = clk_get_rate(cpu_clk); - mutex_lock(&info->reg_lock); - if (unlikely(info->pre_vproc <= 0)) pre_vproc = regulator_get_voltage(info->proc_reg); else @@ -308,7 +309,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, info->current_freq = freq_hz; out: - mutex_unlock(&info->reg_lock); + mutex_unlock(&mtk_policy_lock); return ret; } @@ -316,19 +317,20 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, unsigned long event, void *data) { - struct dev_pm_opp *opp = data; + struct dev_pm_opp *opp; struct dev_pm_opp *new_opp; struct mtk_cpu_dvfs_info *info; unsigned long freq, volt; struct cpufreq_policy *policy; int ret = 0; + mutex_lock(&mtk_policy_lock); + opp = data; info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb); if (event == OPP_EVENT_ADJUST_VOLTAGE) { freq = dev_pm_opp_get_freq(opp); - mutex_lock(&info->reg_lock); if (info->current_freq == freq) { volt = dev_pm_opp_get_voltage(opp); ret = mtk_cpufreq_set_voltage(info, volt); @@ -336,7 +338,6 @@ static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, dev_err(info->cpu_dev, "failed to scale voltage: %d\n", ret); } - mutex_unlock(&info->reg_lock); } else if (event == OPP_EVENT_DISABLE) { freq = dev_pm_opp_get_freq(opp); @@ -361,6 +362,7 @@ static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, } } } + mutex_unlock(&mtk_policy_lock); return notifier_from_errno(ret); } @@ -495,7 +497,6 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) info->intermediate_voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); - mutex_init(&info->reg_lock); info->current_freq = clk_get_rate(info->cpu_clk); info->opp_cpu = cpu; @@ -607,13 +608,31 @@ static void mtk_cpufreq_exit(struct cpufreq_policy *policy) dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table); } +static unsigned int mtk_cpufreq_get(unsigned int cpu) +{ + struct mtk_cpu_dvfs_info *info; + unsigned long current_freq; + + mutex_lock(&mtk_policy_lock); + info = mtk_cpu_dvfs_info_lookup(cpu); + if (!info) { + mutex_unlock(&mtk_policy_lock); + return 0; + } + + current_freq = info->current_freq / 1000; + mutex_unlock(&mtk_policy_lock); + + return current_freq; +} + static struct cpufreq_driver mtk_cpufreq_driver = { .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | CPUFREQ_HAVE_GOVERNOR_PER_POLICY | CPUFREQ_IS_COOLING_DEV, .verify = cpufreq_generic_frequency_table_verify, .target_index = mtk_cpufreq_set_target, - .get = cpufreq_generic_get, + .get = mtk_cpufreq_get, .init = mtk_cpufreq_init, .exit = mtk_cpufreq_exit, .register_em = cpufreq_register_em_with_opp, From patchwork Fri Feb 14 07:43:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Tseng X-Patchwork-Id: 13974579 X-Patchwork-Delegate: viresh.linux@gmail.com Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 621A51C862B; Fri, 14 Feb 2025 07:43:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739519042; cv=none; b=fYFnLKSGQ3LAyN82zFXTW5LmmzY96KvD5bOFx+FN6EhPYCw7mkQv/BZ3XUTwG6Nc2A9ksKURI2CRLlW2KRUTrNfZnUzJid/DYCuh7qwdMJxrUobaDInravsOkOweVOmu2GtxNzeyAnJH0za0pxEbDU54jJ8y3n3dQKK9STlXD6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739519042; c=relaxed/simple; bh=JhIZhzy/VmNLEI+FVSk0Y8ZZKnaxYR5+1TNzTb1xyd0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LE2fEbfTekBKLk37bh4IDygKPSgbwx6gPjEcI+cy8GXi1kpHnzOWWVNOYnvX+XW2htzsXZt090AnHLt2ulUzejXkFLweiEQ4Woa17WcVvsKn20uygFlcw0aJt33kX5AROeIdCtk2OVuD3T3AqkxyTJoIQ9N9izhoBL3JroNUOVc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=klcsRgQl; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="klcsRgQl" X-UUID: 71512dbeeaa711efbd192953cf12861f-20250214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=9bd1SEl58hRjLit531fXO640LwjMPruVn6dM/zQMBCk=; b=klcsRgQlX7FFDSfPwegFRdsmfui3f8a7uIiCkDVP1SFLrPFoaaSboGMPj9Es9IqTi9m5scQ+ovUBgI+ZmrqovSIwj72C3a+IbZokNpOtKw255GnieX72imLjhPaqFr2jSF8nOMzHQnguZj/1mTjri8R3JKdpcOqV5fboAxfV33w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46,REQID:fe384a7b-3daf-4329-8c81-1701c5398b67,IP:0,U RL:0,TC:0,Content:28,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:28 X-CID-META: VersionHash:60aa074,CLOUDID:90bcbe24-96bd-4ac5-8f2e-15aa1ef9defa,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:4|50,EDM:-3 ,IP:nil,URL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 ,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 71512dbeeaa711efbd192953cf12861f-20250214 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1097142833; Fri, 14 Feb 2025 15:43:55 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Fri, 14 Feb 2025 15:43:53 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Fri, 14 Feb 2025 15:43:53 +0800 From: Mark Tseng To: "Rafael J . Wysocki" , Viresh Kumar , MyungJoo Ham , "Kyungmin Park" , Chanwoo Choi , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Subject: [PATCH v3 2/3] cpufreq: mediatek: Add CPUFREQ_ASYNC_NOTIFICATION flag Date: Fri, 14 Feb 2025 15:43:33 +0800 Message-ID: <20250214074353.1169864-3-chun-jen.tseng@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250214074353.1169864-1-chun-jen.tseng@mediatek.com> References: <20250214074353.1169864-1-chun-jen.tseng@mediatek.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add CPUFREQ_ASYNC_NOTIFICATION flages for cpufreq policy because some of process will get CPU frequency by cpufreq sysfs node. It may get wrong frequency then call cpufreq_out_of_sync() to fixed frequency. Signed-off-by: Mark Tseng --- drivers/cpufreq/mediatek-cpufreq.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 07d5958e106a..68fcb6fcbe48 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -209,12 +209,12 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, struct dev_pm_opp *opp; long freq_hz, pre_freq_hz; int vproc, pre_vproc, inter_vproc, target_vproc, ret; + struct cpufreq_freqs freqs; mutex_lock(&mtk_policy_lock); inter_vproc = info->intermediate_voltage; - - pre_freq_hz = clk_get_rate(cpu_clk); + pre_freq_hz = policy->cur * 1000; if (unlikely(info->pre_vproc <= 0)) pre_vproc = regulator_get_voltage(info->proc_reg); @@ -307,6 +307,10 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, } info->current_freq = freq_hz; + freqs.old = policy->cur; + freqs.new = freq_table[index].frequency; + cpufreq_freq_transition_begin(policy, &freqs); + cpufreq_freq_transition_end(policy, &freqs, false); out: mutex_unlock(&mtk_policy_lock); @@ -629,6 +633,7 @@ static unsigned int mtk_cpufreq_get(unsigned int cpu) static struct cpufreq_driver mtk_cpufreq_driver = { .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | CPUFREQ_HAVE_GOVERNOR_PER_POLICY | + CPUFREQ_ASYNC_NOTIFICATION | CPUFREQ_IS_COOLING_DEV, .verify = cpufreq_generic_frequency_table_verify, .target_index = mtk_cpufreq_set_target, From patchwork Fri Feb 14 07:43:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Tseng X-Patchwork-Id: 13974581 X-Patchwork-Delegate: viresh.linux@gmail.com Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 808D42153FA; Fri, 14 Feb 2025 07:44:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739519043; cv=none; b=ImXckasYvY8L2LEur5Y2ZsYhLUd4FWa/KJ1mm7Wn4515Msjs5Z3vH3rjG5QP8FGyTIAcs/liJS7qB1J7jkoH27k8iUluFYbrunBFl4eY0UGy8esie3h9vwj8RiUiq2RdweVdvy9P01WZJ5Hn7uaUdNTxqdl3EmtXL7RJoCrU2Ao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739519043; c=relaxed/simple; bh=TTTXWahj9vnNhXUW3BbTkDdH/JC5WYcR0eoYpe7uoFw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mBCHHE4jLDqKmXzoVR/UMDhLp+ldw7V2bD66myIUe+MqUfBT25PiPQR2fXOI9cPLQVbUj/DUVLsjx0UpEqxzb0lIo4mmdCmf1p6mz8KEa7UgemIx5fY3zwNpfoW0v/Fx7VcS+kxiq7igo0q0O0O7YoNibeThZhUfP7cUdbt+Jes= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=DHRE9W03; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="DHRE9W03" X-UUID: 71626fc0eaa711efb8f9918b5fc74e19-20250214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Av2lEU68lYQ0S7L92vfD2pewctBQ4t+HkHiry0seZP8=; b=DHRE9W03+4Q6KpGc4CZizp8GR1RKNo5in8W42CZw2D02Mnl6h4tXz1Ks3kL6Oqomz4N1Z/dbbqPj20nOBJeXExBy3XJuvXIIvqBEsj3W1NTCMdRRLVi232U2RaTbcLKImp1qmQqz9N/R8U12F1I8q36g33R1r3hd26LeAW9HbqU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46,REQID:b784bc57-ca9b-4f4e-b915-bb97077f08e4,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:60aa074,CLOUDID:a3bcbe24-96bd-4ac5-8f2e-15aa1ef9defa,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 71626fc0eaa711efb8f9918b5fc74e19-20250214 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 252830353; Fri, 14 Feb 2025 15:43:55 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Fri, 14 Feb 2025 15:43:54 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Fri, 14 Feb 2025 15:43:54 +0800 From: Mark Tseng To: "Rafael J . Wysocki" , Viresh Kumar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Subject: [PATCH v3 3/3] cpufreq: mediatek: data safety protect Date: Fri, 14 Feb 2025 15:43:34 +0800 Message-ID: <20250214074353.1169864-4-chun-jen.tseng@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250214074353.1169864-1-chun-jen.tseng@mediatek.com> References: <20250214074353.1169864-1-chun-jen.tseng@mediatek.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 get policy data in global lock session avoid get wrong data. Signed-off-by: Mark Tseng --- drivers/cpufreq/mediatek-cpufreq.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 68fcb6fcbe48..37b929e81f70 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -201,11 +201,11 @@ static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info) static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, unsigned int index) { - struct cpufreq_frequency_table *freq_table = policy->freq_table; - struct clk *cpu_clk = policy->clk; - struct clk *armpll = clk_get_parent(cpu_clk); - struct mtk_cpu_dvfs_info *info = policy->driver_data; - struct device *cpu_dev = info->cpu_dev; + struct cpufreq_frequency_table *freq_table; + struct clk *cpu_clk; + struct clk *armpll; + struct mtk_cpu_dvfs_info *info; + struct device *cpu_dev; struct dev_pm_opp *opp; long freq_hz, pre_freq_hz; int vproc, pre_vproc, inter_vproc, target_vproc, ret; @@ -213,6 +213,11 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, mutex_lock(&mtk_policy_lock); + freq_table = policy->freq_table; + cpu_clk = policy->clk; + armpll = clk_get_parent(cpu_clk); + info = policy->driver_data; + cpu_dev = info->cpu_dev; inter_vproc = info->intermediate_voltage; pre_freq_hz = policy->cur * 1000;