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These values needs to be programmed before link training. Signed-off-by: Krishna Chaitanya Chundru --- dtschema/schemas/pci/pci-bus-common.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml index 94b648f..a9309af 100644 --- a/dtschema/schemas/pci/pci-bus-common.yaml +++ b/dtschema/schemas/pci/pci-bus-common.yaml @@ -150,6 +150,12 @@ properties: description: Disables ASPM L0s capability type: boolean + aspm-l0s-entry-delay-ns: + description: ASPM L0s entry delay + + aspm-l1-entry-delay-ns: + description: ASPM L1 entry delay + vpcie12v-supply: description: 12v regulator phandle for the slot From patchwork Sun Feb 16 01:45:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13976307 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AFBFBA50 for ; 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Sat, 15 Feb 2025 17:45:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IEOZ+s1hML65+t/oMtnG25500NghTCO06Dip85+ffWni6ZFpcXj+VIoxImhNSiQ1ejvbPABEw== X-Received: by 2002:a17:902:e5d0:b0:215:89a0:416f with SMTP id d9443c01a7336-22104058b35mr58608675ad.30.1739670343430; Sat, 15 Feb 2025 17:45:43 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-220d536455esm49896955ad.74.2025.02.15.17.45.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Feb 2025 17:45:42 -0800 (PST) From: Krishna Chaitanya Chundru To: andersson@kernel.org, robh@kernel.org, dmitry.baryshkov@linaro.org, manivannan.sadhasivam@linaro.org, krzk@kernel.org, helgaas@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, lpieralisi@kernel.org, kw@linux.com, conor+dt@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree-spec@vger.kernel.org, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru Subject: [PATCH V3 2/2] schemas: pci: bridge: Document PCIe N_FTS Date: Sun, 16 Feb 2025 07:15:10 +0530 Message-Id: <20250216014510.3990613-3-krishna.chundru@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250216014510.3990613-1-krishna.chundru@oss.qualcomm.com> References: <20250216014510.3990613-1-krishna.chundru@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: qq0pBwoo9EcVjv12rJbJDBLYyudRciFc X-Proofpoint-GUID: qq0pBwoo9EcVjv12rJbJDBLYyudRciFc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-15_09,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 adultscore=0 suspectscore=0 bulkscore=0 impostorscore=0 clxscore=1015 malwarescore=0 mlxlogscore=950 lowpriorityscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502160014 Per PCIe r6.0, sec 4.2.5.1, during Link training, a PCIe component captures the N_FTS value it receives. Per 4.2.5.6, when transitioning the Link from L0s to L0, it must transmit N_FTS Fast Training Sequences to enable the receiver to obtain bit and Symbol lock. Components may have device-specific ways to configure N_FTS values to advertise during Link training. Define an n_fts array with an entry for each supported data rate. Signed-off-by: Krishna Chaitanya Chundru --- dtschema/schemas/pci/pci-bus-common.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml index a9309af..ca97a00 100644 --- a/dtschema/schemas/pci/pci-bus-common.yaml +++ b/dtschema/schemas/pci/pci-bus-common.yaml @@ -128,6 +128,16 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 1, 2, 4, 8, 16, 32 ] + n-fts: + description: + The number of Fast Training Sequences (N_FTS) required by the + Receiver (this component) when transitioning the Link from L0s + to L0; advertised during initial Link training. Each entry in + the array specifies a PCIe data rate + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 1 + maxItems: 5 + reset-gpios: description: GPIO controlled connection to PERST# signal maxItems: 1