From patchwork Tue Mar 19 08:30:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10858971 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77B0A6C2 for ; Tue, 19 Mar 2019 08:05:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0C792292ED for ; Tue, 19 Mar 2019 08:05:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 001DB2933D; Tue, 19 Mar 2019 08:05:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 98548292ED for ; Tue, 19 Mar 2019 08:05:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 896C4899DC; Tue, 19 Mar 2019 08:05:18 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 00F8389487 for ; Tue, 19 Mar 2019 08:05:14 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2019 01:05:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,497,1544515200"; d="scan'208";a="329900365" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.134]) by fmsmga005.fm.intel.com with ESMTP; 19 Mar 2019 01:05:12 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Tue, 19 Mar 2019 14:00:12 +0530 Message-Id: <1552984218-3357-2-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> References: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v1 1/7] drm/i915: Add gamma mode property X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Gen platforms support multiple gamma modes, currently it's hard coded to operate only in 1 specific mode. This patch adds a property to make gamma mode programmable. User can select which mode should be used for a particular usecase or scenario. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_color.c | 46 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 3 +++ 3 files changed, 51 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c65c2e6..02231ae 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1735,6 +1735,8 @@ struct drm_i915_private { struct drm_property *broadcast_rgb_property; struct drm_property *force_audio_property; + struct drm_property *gamma_mode_property; + /* hda/i915 audio component */ struct i915_audio_component *audio_component; bool audio_component_registered; diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 467fd1a..9d43d19 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -92,6 +92,19 @@ 0x0800, 0x0100, 0x0800, }; +#define LEGACY_PALETTE_MODE_8BIT BIT(0) +#define PRECISION_PALETTE_MODE_10BIT BIT(1) +#define INTERPOLATED_GAMMA_MODE_12BIT BIT(2) +#define MULTI_SEGMENTED_GAMMA_MODE_12BIT BIT(3) +#define SPLIT_GAMMA_MODE_12BIT BIT(4) + +#define INTEL_GAMMA_MODE_MASK (\ + LEGACY_PALETTE_MODE_8BIT | \ + PRECISION_PALETTE_MODE_10BIT | \ + INTERPOLATED_GAMMA_MODE_12BIT | \ + MULTI_SEGMENTED_GAMMA_MODE_12BIT | \ + BIT_SPLIT_GAMMA_MODE_12BIT) + static bool lut_is_legacy(const struct drm_property_blob *lut) { return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; @@ -105,6 +118,37 @@ static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state lut_is_legacy(crtc_state->base.gamma_lut); } +static const struct drm_prop_enum_list gamma_mode_supported[] = { + { LEGACY_PALETTE_MODE_8BIT, "8 Bit Legacy Palette Mode" }, + { PRECISION_PALETTE_MODE_10BIT, "10 Bit Precision Palette Mode" }, + { INTERPOLATED_GAMMA_MODE_12BIT, "12 Bit Interploated Gamma Mode" }, + { MULTI_SEGMENTED_GAMMA_MODE_12BIT, + "12 Bit Multi Segmented Gamma Mode" }, + { SPLIT_GAMMA_MODE_12BIT, "12 Bit Split Gamma Mode" }, +}; + +void +intel_attach_gamma_mode_property(struct intel_crtc *crtc) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_property *prop; + + prop = dev_priv->gamma_mode_property; + if (!prop) { + prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, + "Gamma Mode", + gamma_mode_supported, + ARRAY_SIZE(gamma_mode_supported)); + if (!prop) + return; + + dev_priv->gamma_mode_property = prop; + } + + drm_object_attach_property(&crtc->base.base, prop, 0); +} + /* * When using limited range, multiply the matrix given by userspace by * the matrix that we would use for the limited range. @@ -907,4 +951,6 @@ void intel_color_init(struct intel_crtc *crtc) INTEL_INFO(dev_priv)->color.degamma_lut_size, true, INTEL_INFO(dev_priv)->color.gamma_lut_size); + + intel_attach_gamma_mode_property(crtc); } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d9f188e..fd84fe9 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1034,6 +1034,9 @@ struct intel_crtc_state { u8 nv12_planes; u8 c8_planes; + /* Gamma mode type programmed on the pipe */ + u32 gamma_mode_type; + /* bitmask of planes that will be updated during the commit */ u8 update_planes; From patchwork Tue Mar 19 08:30:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10858969 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2186E139A for ; Tue, 19 Mar 2019 08:05:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3F7D929050 for ; Tue, 19 Mar 2019 08:05:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 316D12933D; Tue, 19 Mar 2019 08:05:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C5B7329050 for ; Tue, 19 Mar 2019 08:05:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A730889971; Tue, 19 Mar 2019 08:05:17 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0654289971 for ; Tue, 19 Mar 2019 08:05:16 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2019 01:05:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,497,1544515200"; d="scan'208";a="329900393" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.134]) by fmsmga005.fm.intel.com with ESMTP; 19 Mar 2019 01:05:15 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Tue, 19 Mar 2019 14:00:13 +0530 Message-Id: <1552984218-3357-3-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> References: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v1 2/7] drm/i915: Add intel crtc set and get property callback X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add intel crtc set and get property callbacks. Currently added for gamma mode property set and get implementation. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_display.c | 58 ++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 61acbaf..7604f16 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13679,6 +13679,62 @@ static int intel_atomic_commit(struct drm_device *dev, return 0; } +/** + * intel_crtc_atomic_get_property - hook for crtc->atomic_get_property. + * @crtc: Crtc to get the property for. + * @state: Crtc state to retrieve the property from. + * @property: Property to retrieve. + * @val: Return value for the property. + * + * Returns the atomic property value for a crtc. + */ +int intel_crtc_atomic_get_property(struct drm_crtc *crtc, + const struct drm_crtc_state *state, + struct drm_property *property, + uint64_t *val) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(state); + + if (property == dev_priv->gamma_mode_property) { + *val = intel_crtc_state->gamma_mode_type; + } else { + DRM_DEBUG_ATOMIC("Unknown property %s\n", property->name); + return -EINVAL; + } + + return 0; +} + +/** + * intel_crtc_atomic_set_property - hook for crtc->atomic_set_property. + * @crtc: Crtc to set the property for. + * @state: Crtc state to set the property on. + * @property: Property to set. + * @val: New value for the property. + * + * Sets the atomic property value for a crtc. + */ +int intel_crtc_atomic_set_property(struct drm_crtc *crtc, + struct drm_crtc_state *state, + struct drm_property *property, + uint64_t val) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(state); + + if (property == dev_priv->gamma_mode_property) { + intel_crtc_state->gamma_mode_type = val; + state->color_mgmt_changed |= replaced; + return 0; + } + + DRM_DEBUG_ATOMIC("Unknown property %s\n", property->name); + return -EINVAL; +} + static const struct drm_crtc_funcs intel_crtc_funcs = { .gamma_set = drm_atomic_helper_legacy_gamma_set, .set_config = drm_atomic_helper_set_config, @@ -13689,6 +13745,8 @@ static int intel_atomic_commit(struct drm_device *dev, .set_crc_source = intel_crtc_set_crc_source, .verify_crc_source = intel_crtc_verify_crc_source, .get_crc_sources = intel_crtc_get_crc_sources, + .atomic_get_property = intel_crtc_atomic_get_property, + .atomic_set_property = intel_crtc_atomic_set_property, }; struct wait_rps_boost { From patchwork Tue Mar 19 08:30:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10858975 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A90BD139A for ; Tue, 19 Mar 2019 08:05:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 105FC292ED for ; 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Tue, 19 Mar 2019 08:05:19 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2019 01:05:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,497,1544515200"; d="scan'208";a="329900415" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.134]) by fmsmga005.fm.intel.com with ESMTP; 19 Mar 2019 01:05:17 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Tue, 19 Mar 2019 14:00:14 +0530 Message-Id: <1552984218-3357-4-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> References: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v1 3/7] drm/i915: Add Support for Multi Segment Gamma Mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Multi Segment Gamma Mode is added in Gen11+ platforms. Added a property interface to enable that. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_color.c | 23 +++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 14 ++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 02231ae..f20d418 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1736,6 +1736,7 @@ struct drm_i915_private { struct drm_property *force_audio_property; struct drm_property *gamma_mode_property; + struct drm_property *multi_segment_gamma_mode_property; /* hda/i915 audio component */ struct i915_audio_component *audio_component; diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 9d43d19..399d63d 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -149,6 +149,26 @@ static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state drm_object_attach_property(&crtc->base.base, prop, 0); } +void +intel_attach_multi_segment_gamma_mode_property(struct intel_crtc *crtc) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_property *prop; + + prop = dev_priv->multi_segment_gamma_mode_property; + if (!prop) { + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, + "Multi-segment Gamma", 0); + if (!prop) + return; + + dev_priv->multi_segment_gamma_mode_property = prop; + } + + drm_object_attach_property(&crtc->base.base, prop, 0); +} + /* * When using limited range, multiply the matrix given by userspace by * the matrix that we would use for the limited range. @@ -953,4 +973,7 @@ void intel_color_init(struct intel_crtc *crtc) INTEL_INFO(dev_priv)->color.gamma_lut_size); intel_attach_gamma_mode_property(crtc); + + if (INTEL_GEN(dev_priv) >= 11) + intel_attach_multi_segment_gamma_mode_property(crtc); } diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index aa2d4c7..8f1974e 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1842,6 +1842,20 @@ struct drm_i915_query_topology_info { __u8 data[]; }; +/* + * Structure for muti segmented gamma lut + */ +struct multi_segment_gamma_lut { + /* Number of Lut Segments */ + __u8 segment_cnt; + /* Precison of LUT entries in bits */ + __u8 precision_bits; + /* Pointer having number of LUT elements in each segment */ + __u32 *segment_lut_cnt_ptr; + /* Pointer to store exact lut values for each segment */ + __u32 *segment_lut_ptr; +}; + #if defined(__cplusplus) } #endif From patchwork Tue Mar 19 08:30:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10858977 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BD2B76C2 for ; Tue, 19 Mar 2019 08:05:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 93F5F29050 for ; Tue, 19 Mar 2019 08:05:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 885202933D; Tue, 19 Mar 2019 08:05:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9B89D29050 for ; Tue, 19 Mar 2019 08:05:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E808A899DE; Tue, 19 Mar 2019 08:05:23 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1538F899EA for ; Tue, 19 Mar 2019 08:05:21 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2019 01:05:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,497,1544515200"; d="scan'208";a="329900437" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.134]) by fmsmga005.fm.intel.com with ESMTP; 19 Mar 2019 01:05:19 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Tue, 19 Mar 2019 14:00:15 +0530 Message-Id: <1552984218-3357-5-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> References: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v1 4/7] drm/i915: Implement get set property handler for multi segment gamma X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Implement get and set property handler for multi segment gamma mode. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_display.c | 46 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 12 ++++++++++ 2 files changed, 58 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7604f16..8ac9728 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13679,6 +13679,39 @@ static int intel_atomic_commit(struct drm_device *dev, return 0; } +static int +intel_atomic_replace_property_blob_from_id(struct drm_device *dev, + struct drm_property_blob **blob, + u64 blob_id, + ssize_t expected_size, + ssize_t expected_elem_size, + bool *replaced) +{ + struct drm_property_blob *new_blob = NULL; + + if (blob_id != 0) { + new_blob = drm_property_lookup_blob(dev, blob_id); + if (!new_blob) + return -EINVAL; + + if (expected_size > 0 && + new_blob->length != expected_size) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + if (expected_elem_size > 0 && + new_blob->length % expected_elem_size != 0) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + } + + *replaced |= drm_property_replace_blob(blob, new_blob); + drm_property_blob_put(new_blob); + + return 0; +} + /** * intel_crtc_atomic_get_property - hook for crtc->atomic_get_property. * @crtc: Crtc to get the property for. @@ -13699,6 +13732,9 @@ int intel_crtc_atomic_get_property(struct drm_crtc *crtc, if (property == dev_priv->gamma_mode_property) { *val = intel_crtc_state->gamma_mode_type; + } else if (property == dev_priv->multi_segment_gamma_mode_property) { + *val = (intel_crtc_state->multi_segment_gamma_lut) ? + intel_crtc_state->multi_segment_gamma_lut->base.id : 0; } else { DRM_DEBUG_ATOMIC("Unknown property %s\n", property->name); return -EINVAL; @@ -13724,11 +13760,21 @@ int intel_crtc_atomic_set_property(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(state); + bool replaced = false; + int ret; if (property == dev_priv->gamma_mode_property) { intel_crtc_state->gamma_mode_type = val; state->color_mgmt_changed |= replaced; return 0; + } else if (property == dev_priv->multi_segment_gamma_mode_property) { + ret = intel_atomic_replace_property_blob_from_id(dev, + &intel_crtc_state->multi_segment_gamma_lut, + val, -1, + sizeof(struct multi_segment_gamma_lut), + &replaced); + state->color_mgmt_changed |= replaced; + return ret; } DRM_DEBUG_ATOMIC("Unknown property %s\n", property->name); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index fd84fe9..7fccd28 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1037,6 +1037,18 @@ struct intel_crtc_state { /* Gamma mode type programmed on the pipe */ u32 gamma_mode_type; + /** + * @multi_segment_gamma_lut: + * + * Lookup table for converting pixel data after the color conversion + * matrix @ctm. See drm_crtc_enable_color_mgmt(). The blob (if not + * NULL) is an array of &struct drm_color_lut. + */ + struct drm_property_blob *multi_segment_gamma_lut; + + /* State to check for Gamma Mode Color Changes */ + bool color_mgmt_changed : 1; + /* bitmask of planes that will be updated during the commit */ u8 update_planes; From patchwork Tue Mar 19 08:30:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10858979 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D8A6C6C2 for ; Tue, 19 Mar 2019 08:05:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A8BEF292ED for ; Tue, 19 Mar 2019 08:05:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9CFEB2933D; Tue, 19 Mar 2019 08:05:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5E4FB292ED for ; Tue, 19 Mar 2019 08:05:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C28A6899BB; Tue, 19 Mar 2019 08:05:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0FE55899E6 for ; Tue, 19 Mar 2019 08:05:23 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2019 01:05:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,497,1544515200"; d="scan'208";a="329900459" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.134]) by fmsmga005.fm.intel.com with ESMTP; 19 Mar 2019 01:05:21 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Tue, 19 Mar 2019 14:00:16 +0530 Message-Id: <1552984218-3357-6-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> References: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v1 5/7] drm/i915/icl: Add register definitions for Multi Segmented gamma X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add macros to define multi segmented gamma registers Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 31a3020..44ca13b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7209,6 +7209,7 @@ enum { #define GAMMA_MODE_MODE_10BIT (1 << 0) #define GAMMA_MODE_MODE_12BIT (2 << 0) #define GAMMA_MODE_MODE_SPLIT (3 << 0) +#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* DMC/CSR */ #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) @@ -10147,6 +10148,22 @@ enum skl_power_gate { #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) +/* Add registers for Gen11 Multi Segmented Gamma Mode */ +#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 +#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 +#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT BIT(15) +#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK (0x1f << 0) + +#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C +#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C + +#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ + _PAL_PREC_MULTI_SEG_INDEX_A, \ + _PAL_PREC_MULTI_SEG_INDEX_B) +#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ + _PAL_PREC_MULTI_SEG_DATA_A, \ + _PAL_PREC_MULTI_SEG_DATA_B) + /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) From patchwork Tue Mar 19 08:30:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10858983 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 156196C2 for ; Tue, 19 Mar 2019 08:05:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8514429050 for ; Tue, 19 Mar 2019 08:05:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 796EF2933D; Tue, 19 Mar 2019 08:05:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CE45029334 for ; Tue, 19 Mar 2019 08:05:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A8F4899F0; Tue, 19 Mar 2019 08:05:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 63955899E7 for ; Tue, 19 Mar 2019 08:05:25 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2019 01:05:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,497,1544515200"; d="scan'208";a="329900486" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.134]) by fmsmga005.fm.intel.com with ESMTP; 19 Mar 2019 01:05:23 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Tue, 19 Mar 2019 14:00:17 +0530 Message-Id: <1552984218-3357-7-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> References: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v1 6/7] drm/i915/icl: Add support for multi segmented gamma mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Gen11 introduced a new gamma mode i.e, multi segmented gamma mode. Added support for the same. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_color.c | 105 +++++++++++++++++++++++++++++++------ 1 file changed, 90 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 399d63d..7733c256 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -105,6 +105,9 @@ MULTI_SEGMENTED_GAMMA_MODE_12BIT | \ BIT_SPLIT_GAMMA_MODE_12BIT) +#define GEN11_GET_MS10BITS_OF_LUT(lut) (((lut) >> 6) & 0x3FF) +#define GEN11_GET_LS6BITS_OF_LUT(lut) ((lut) & 0x3F) + static bool lut_is_legacy(const struct drm_property_blob *lut) { return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; @@ -538,6 +541,10 @@ static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state) if (degamma_lut) { const struct drm_color_lut *lut = degamma_lut->data; + if (crtc_state->gamma_mode_type == + MULTI_SEGMENTED_GAMMA_MODE_12BIT) + lut += 9; + for (i = 0; i < lut_size; i++) { u32 word = drm_color_lut_extract(lut[i].red, 10) << 20 | @@ -563,6 +570,7 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; u32 i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; enum pipe pipe = crtc->pipe; + u32 word; WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK); @@ -574,13 +582,32 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of if (gamma_lut) { const struct drm_color_lut *lut = gamma_lut->data; - for (i = 0; i < lut_size; i++) { - u32 word = - (drm_color_lut_extract(lut[i].red, 10) << 20) | - (drm_color_lut_extract(lut[i].green, 10) << 10) | - drm_color_lut_extract(lut[i].blue, 10); - - I915_WRITE(PREC_PAL_DATA(pipe), word); + if (crtc_state->gamma_mode_type == + MULTI_SEGMENTED_GAMMA_MODE_12BIT) { + lut_size = 9 + 512; + for (i = 9; i < lut_size; i++) { + /* For Even Index */ + word = (GEN11_GET_LS6BITS_OF_LUT(lut[i].red) << 20) | + (GEN11_GET_LS6BITS_OF_LUT(lut[i].green) << 10)| + GEN11_GET_LS6BITS_OF_LUT(lut[i].blue); + + I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), word); + + /* For ODD index */ + word = (GEN11_GET_MS10BITS_OF_LUT(lut[i].red) << 20) | + (GEN11_GET_MS10BITS_OF_LUT(lut[i].green) << 10) | + GEN11_GET_MS10BITS_OF_LUT(lut[i].blue); + + I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), word); + } + } else { + for (i = 0; i < lut_size; i++) { + word = (drm_color_lut_extract(lut[i].red, 10) << 20) | + (drm_color_lut_extract(lut[i].green, 10) << 10) | + drm_color_lut_extract(lut[i].blue, 10); + + I915_WRITE(PREC_PAL_DATA(pipe), word); + } } /* Program the max register to clamp values > 1.0. */ @@ -685,15 +712,57 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state) bdw_load_gamma_lut(crtc_state, 0); } +static void icl_load_gamma_multi_segmented_lut(const struct intel_crtc_state + *crtc_state, u32 offset) +{ + struct drm_crtc *crtc = crtc_state->base.crtc; + struct drm_device *dev = crtc_state->base.crtc->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + u32 i, lut_size = 9; + + WARN_ON(offset & ~PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK); + + I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), + (PAL_PREC_AUTO_INCREMENT | offset)); + + if (crtc_state->base.gamma_lut) { + struct drm_color_lut *lut = + (struct drm_color_lut *)crtc_state->base.gamma_lut->data; + + for (i = 0; i < lut_size; i++) { + u32 word; + + /* For Even Index */ + word = (GEN11_GET_LS6BITS_OF_LUT(lut[i].red) << 20) | + (GEN11_GET_LS6BITS_OF_LUT(lut[i].green) << 10) | + GEN11_GET_LS6BITS_OF_LUT(lut[i].blue); + I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), word); + + /* For ODD index */ + word = (GEN11_GET_MS10BITS_OF_LUT(lut[i].red) << 20) | + (GEN11_GET_MS10BITS_OF_LUT(lut[i].green) << 10) | + GEN11_GET_MS10BITS_OF_LUT(lut[i].blue); + I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), word); + } + } + + bdw_load_gamma_lut(crtc_state, 0); +} + static void icl_load_luts(const struct intel_crtc_state *crtc_state) { glk_load_degamma_lut(crtc_state); - if (crtc_state_is_legacy_gamma(crtc_state)) + if (crtc_state_is_legacy_gamma(crtc_state)) { i9xx_load_luts(crtc_state); - else + } else if (crtc_state->gamma_mode_type == + MULTI_SEGMENTED_GAMMA_MODE_12BIT) { + icl_load_gamma_multi_segmented_lut(crtc_state, 0); + } else { /* ToDo: Add support for multi segment gamma LUT */ bdw_load_gamma_lut(crtc_state, 0); + } } static void cherryview_load_luts(const struct intel_crtc_state *crtc_state) @@ -910,16 +979,22 @@ int intel_color_check(struct intel_crtc_state *crtc_state) drm_color_lut_check(gamma_lut, gamma_tests)) return -EINVAL; - if (INTEL_GEN(dev_priv) >= 11) - crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT | - PRE_CSC_GAMMA_ENABLE | + if (INTEL_GEN(dev_priv) >= 11) { + crtc_state->gamma_mode = PRE_CSC_GAMMA_ENABLE | POST_CSC_GAMMA_ENABLE; - else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + if (crtc_state->gamma_mode_type == + MULTI_SEGMENTED_GAMMA_MODE_12BIT) + crtc_state->gamma_mode |= + GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; + else + crtc_state->gamma_mode |= GAMMA_MODE_MODE_10BIT; + } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT; - else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) + } else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT; - else + } else { crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; + } if (INTEL_GEN(dev_priv) >= 11) { if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || From patchwork Tue Mar 19 08:30:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10858981 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 124626C2 for ; Tue, 19 Mar 2019 08:05:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C390729050 for ; Tue, 19 Mar 2019 08:05:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B7AC82933D; Tue, 19 Mar 2019 08:05:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3F98E29349 for ; Tue, 19 Mar 2019 08:05:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9419F899E9; Tue, 19 Mar 2019 08:05:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5DBD5899E8 for ; Tue, 19 Mar 2019 08:05:27 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2019 01:05:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,497,1544515200"; d="scan'208";a="329900507" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.134]) by fmsmga005.fm.intel.com with ESMTP; 19 Mar 2019 01:05:25 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Tue, 19 Mar 2019 14:00:18 +0530 Message-Id: <1552984218-3357-8-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> References: <1552984218-3357-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v1 7/7] drm/i915: Add multi segment gamma for icl X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Added support for ICL platform multi segment gamma capabilties and attached the property, exposing the same to userspace. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_color.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 7733c256..1e9f784 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -1011,6 +1011,8 @@ int intel_color_check(struct intel_crtc_state *crtc_state) void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct multi_segment_gamma_lut multi_segment_lut; + drm_mode_crtc_set_gamma_size(&crtc->base, 256); @@ -1049,6 +1051,24 @@ void intel_color_init(struct intel_crtc *crtc) intel_attach_gamma_mode_property(crtc); - if (INTEL_GEN(dev_priv) >= 11) + if (IS_ICELAKE(dev_priv)) { + multi_segment_lut.segment_cnt = 3; + multi_segment_lut.precision_bits = 16; + multi_segment_lut.segment_lut_cnt_ptr = kzalloc(3 * sizeof(int), + GFP_KERNEL); + if (!multi_segment_lut.segment_lut_cnt_ptr) + return; + multi_segment_lut.segment_lut_cnt_ptr[0] = 9; + multi_segment_lut.segment_lut_cnt_ptr[1] = 256; + multi_segment_lut.segment_lut_cnt_ptr[2] = 256; + intel_attach_multi_segment_gamma_mode_property(crtc); + + drm_property_replace_global_blob(crtc->base.dev, + &crtc->config->multi_segment_gamma_lut, + sizeof(struct multi_segment_gamma_lut), + &multi_segment_lut, + &crtc->base.base, + dev_priv->multi_segment_gamma_mode_property); + } }