From patchwork Sun Feb 16 18:46:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= X-Patchwork-Id: 13976672 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C8BC18A6AB; Sun, 16 Feb 2025 18:47:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739731622; cv=none; b=eImnHLGCuwf7peaU9PmNH+MWsx0uGmXHAlaeQ6+36pCicWHH0nr+gNY6gXjkyZ/hfIhbfEWQXxI0LTOiDn+dKdJVWyvvSCgkprfjK4GqYS36KJspk2e4i95JsWzvnzyiM6muLll/LnNot2XpP9c8JC9MzeFLvRECyoQKVEgi1Io= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739731622; c=relaxed/simple; bh=jPv0Cs97xsT0crtZmnsVyj4K8wdMsbE9n67dgBc3bu8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UbQ3ct4c7oAodJ6aeV5zncOiFHa3Aju8o0H3JqDTuegMXaFDSRkMPvrx1dIzw30dZkA3rR5KPAEDY21neY2yOZvA/YVc1xJF4GYFCgzW4VdQ83yhGwxQtl8g4FAejPK5hd83NocS8wr8lciuNK9odKmPZ56/2X9AwWe6LL2yIMA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=T7up8pTg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="T7up8pTg" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9DF4EC4CEE8; Sun, 16 Feb 2025 18:47:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739731621; bh=jPv0Cs97xsT0crtZmnsVyj4K8wdMsbE9n67dgBc3bu8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=T7up8pTgqkg1ksVfgHgfeWOi2/LLQ95vzRLs8Vzqkw7WcfgK6XTIJV4ng7tOCBZHa y4vaPfNSzjLHPUaiy9ngWmPT6ozFXygVxKdFYV07pXDIEmt4EjbazuBHGAXSb7ywDT jBiReDJqRZZcHt1Ofe40SKuPqyPIMfENxo3ce+GS7UNJIC3z8Mr+jcGJ//UTZ9d55e D2QXPBZv16Bum5oMNpA3u+dO39MMMN33DBAVbRavj6xt6OigU+5o/mpOoQxbb3MRvP 2xTrwQr6Jfiefdb2lwYqmNlf7ToH5EX+Wqm0/YajfwsQfmeMkoa03Mi+O2GZdKtoUm pTkmhkN6/WqTQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88ABAC021A6; Sun, 16 Feb 2025 18:47:01 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Sun, 16 Feb 2025 19:46:44 +0100 Subject: [PATCH 1/4] media: i2c: imx214: Calculate link bit rate from clock frequency Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250216-imx214_clk_freq-v1-1-812f40f07db3@apitzsch.eu> References: <20250216-imx214_clk_freq-v1-0-812f40f07db3@apitzsch.eu> In-Reply-To: <20250216-imx214_clk_freq-v1-0-812f40f07db3@apitzsch.eu> To: Ricardo Ribalda , Sakari Ailus , Mauro Carvalho Chehab Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr?= =?utf-8?q?=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739731620; l=4568; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=CrC/VI4OhUDXF04VluXMQqpjXLZSHaubF6hdre/ipkc=; b=E4YknhTo8FWC7oNLZ4uXVZOBCREQJafUXAYwpqgv62Mw+jMOtN5x7ZexV4KBzjo38RNNyB41N HXqL8kWTQ6PCiOZuZmNn7cPOmHuoP8J4RfzL/UQB68E7g6g8zlN4FnI X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: André Apitzsch Replace the magic link bit rate number (4800) by its calculation based on the used parameters and the provided external clock frequency. The link bit rate is output bitrate multiplied by the number lanes. The output bitrate is the OPPXCK clock frequency multiplied by the number of bits per pixel. The OPPXCK clock frequency is OPCK multiplied by the OPPXCK clock division ratio. And OPCK is the external clock frequency multiplied by the PreDivider setting and the PLL multiple setting. Signed-off-by: André Apitzsch --- drivers/media/i2c/imx214.c | 51 +++++++++++++++++++++++++++++++++------------- 1 file changed, 37 insertions(+), 14 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 6c3f6f3c8b1f7724110dc55fead0f8a168edf35b..14a4c5094799014da38ab1beec401f0d923c2152 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -84,6 +84,7 @@ #define IMX214_CSI_DATA_FORMAT_RAW10 0x0A0A #define IMX214_CSI_DATA_FORMAT_COMP6 0x0A06 #define IMX214_CSI_DATA_FORMAT_COMP8 0x0A08 +#define IMX214_BITS_PER_PIXEL_MASK 0xFF #define IMX214_REG_CSI_LANE_MODE CCI_REG8(0x0114) #define IMX214_CSI_2_LANE_MODE 1 @@ -104,11 +105,23 @@ /* PLL settings */ #define IMX214_REG_VTPXCK_DIV CCI_REG8(0x0301) +#define IMX214_DEFAULT_VTPXCK_DIV 5 + #define IMX214_REG_VTSYCK_DIV CCI_REG8(0x0303) +#define IMX214_DEFAULT_VTSYCK_DIV 2 + #define IMX214_REG_PREPLLCK_VT_DIV CCI_REG8(0x0305) +#define IMX214_DEFAULT_PREPLLCK_VT_DIV 3 + #define IMX214_REG_PLL_VT_MPY CCI_REG16(0x0306) +#define IMX214_DEFAULT_PLL_VT_MPY 150 + #define IMX214_REG_OPPXCK_DIV CCI_REG8(0x0309) +#define IMX214_DEFAULT_OPPXCK_DIV 10 + #define IMX214_REG_OPSYCK_DIV CCI_REG8(0x030b) +#define IMX214_DEFAULT_OPSYCK_DIV 1 + #define IMX214_REG_PLL_MULT_DRIV CCI_REG8(0x0310) #define IMX214_PLL_SINGLE 0 #define IMX214_PLL_DUAL 1 @@ -204,6 +217,14 @@ #define IMX214_PIXEL_ARRAY_WIDTH 4208U #define IMX214_PIXEL_ARRAY_HEIGHT 3120U +/* Link bit rate for a given input clock frequency in single PLL mode */ +#define IMX214_LINK_BIT_RATE(clk_freq) \ + (((clk_freq) / 1000000) / IMX214_DEFAULT_PREPLLCK_VT_DIV \ + * IMX214_DEFAULT_PLL_VT_MPY \ + / (IMX214_DEFAULT_OPSYCK_DIV * IMX214_DEFAULT_OPPXCK_DIV) \ + * (IMX214_CSI_DATA_FORMAT_RAW10 & IMX214_BITS_PER_PIXEL_MASK) \ + * (IMX214_CSI_4_LANE_MODE + 1)) + static const char * const imx214_supply_name[] = { "vdda", "vddd", @@ -299,15 +320,16 @@ static const struct cci_reg_sequence mode_4096x2304[] = { { IMX214_REG_DIG_CROP_WIDTH, 4096 }, { IMX214_REG_DIG_CROP_HEIGHT, 2304 }, - { IMX214_REG_VTPXCK_DIV, 5 }, - { IMX214_REG_VTSYCK_DIV, 2 }, - { IMX214_REG_PREPLLCK_VT_DIV, 3 }, - { IMX214_REG_PLL_VT_MPY, 150 }, - { IMX214_REG_OPPXCK_DIV, 10 }, - { IMX214_REG_OPSYCK_DIV, 1 }, + { IMX214_REG_VTPXCK_DIV, IMX214_DEFAULT_VTPXCK_DIV }, + { IMX214_REG_VTSYCK_DIV, IMX214_DEFAULT_VTSYCK_DIV }, + { IMX214_REG_PREPLLCK_VT_DIV, IMX214_DEFAULT_PREPLLCK_VT_DIV }, + { IMX214_REG_PLL_VT_MPY, IMX214_DEFAULT_PLL_VT_MPY }, + { IMX214_REG_OPPXCK_DIV, IMX214_DEFAULT_OPPXCK_DIV }, + { IMX214_REG_OPSYCK_DIV, IMX214_DEFAULT_OPSYCK_DIV }, { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE }, - { IMX214_REG_REQ_LINK_BIT_RATE, IMX214_LINK_BIT_RATE_MBPS(4800) }, + { IMX214_REG_REQ_LINK_BIT_RATE, + IMX214_LINK_BIT_RATE_MBPS(IMX214_LINK_BIT_RATE(IMX214_DEFAULT_CLK_FREQ)) }, { CCI_REG8(0x3A03), 0x09 }, { CCI_REG8(0x3A04), 0x50 }, @@ -362,15 +384,16 @@ static const struct cci_reg_sequence mode_1920x1080[] = { { IMX214_REG_DIG_CROP_WIDTH, 1920 }, { IMX214_REG_DIG_CROP_HEIGHT, 1080 }, - { IMX214_REG_VTPXCK_DIV, 5 }, - { IMX214_REG_VTSYCK_DIV, 2 }, - { IMX214_REG_PREPLLCK_VT_DIV, 3 }, - { IMX214_REG_PLL_VT_MPY, 150 }, - { IMX214_REG_OPPXCK_DIV, 10 }, - { IMX214_REG_OPSYCK_DIV, 1 }, + { IMX214_REG_VTPXCK_DIV, IMX214_DEFAULT_VTPXCK_DIV }, + { IMX214_REG_VTSYCK_DIV, IMX214_DEFAULT_VTSYCK_DIV }, + { IMX214_REG_PREPLLCK_VT_DIV, IMX214_DEFAULT_PREPLLCK_VT_DIV }, + { IMX214_REG_PLL_VT_MPY, IMX214_DEFAULT_PLL_VT_MPY }, + { IMX214_REG_OPPXCK_DIV, IMX214_DEFAULT_OPPXCK_DIV }, + { IMX214_REG_OPSYCK_DIV, IMX214_DEFAULT_OPSYCK_DIV }, { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE }, - { IMX214_REG_REQ_LINK_BIT_RATE, IMX214_LINK_BIT_RATE_MBPS(4800) }, + { IMX214_REG_REQ_LINK_BIT_RATE, + IMX214_LINK_BIT_RATE_MBPS(IMX214_LINK_BIT_RATE(IMX214_DEFAULT_CLK_FREQ)) }, { CCI_REG8(0x3A03), 0x04 }, { CCI_REG8(0x3A04), 0xF8 }, From patchwork Sun Feb 16 18:46:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= X-Patchwork-Id: 13976671 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C92519C54C; Sun, 16 Feb 2025 18:47:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739731622; cv=none; b=UzdiuBvuWqVf3cIRzJ4FZ1mdvn8A2cEKeibQkYEB4fxfvwcASNfSUdSfc0iVGgVNC5T1rq0nzLLgNiL9HLQFEXQYJF51qCarBKTJJ4Sprvli4yzOCRxYEsWIUexcGFYLNgQIaA/tyqC6NnyeQBu8xx1EbUe3FLyS9Zs5egSgi1I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739731622; c=relaxed/simple; bh=47xG7Y+lb+4ABdnenz4kurDLlo2rPsaUAq/8f0C92aA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Sun, 16 Feb 2025 18:47:01 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Sun, 16 Feb 2025 19:46:45 +0100 Subject: [PATCH 2/4] media: i2c: imx214: Prepare for variable clock frequency Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250216-imx214_clk_freq-v1-2-812f40f07db3@apitzsch.eu> References: <20250216-imx214_clk_freq-v1-0-812f40f07db3@apitzsch.eu> In-Reply-To: <20250216-imx214_clk_freq-v1-0-812f40f07db3@apitzsch.eu> To: Ricardo Ribalda , Sakari Ailus , Mauro Carvalho Chehab Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr?= =?utf-8?q?=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739731620; l=4555; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=0VLQFdt57U21JoCzJC3hL0IqNVqlpzlXR87qVLWi7UY=; b=63DWIVZfaVclDY5K3AXOrJFf7zKhJf6liaucDA/x6JsA2NA0e9aRLM3s69jE95V605Ia21zrs 8KVZF+yClr6BZKQaqBNbKY+kqoq7sHQ6KOpfNce+jdopoKikQd7ynuF X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: André Apitzsch Move clock frequency related parameters out of the constant register sequences, such that the hard coded external clock frequency can be replaced by a variable in the next commit. Signed-off-by: André Apitzsch --- drivers/media/i2c/imx214.c | 64 ++++++++++++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 25 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 14a4c5094799014da38ab1beec401f0d923c2152..53b6b427f263a8ad7e3a0d1f711ece234601100e 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -320,17 +320,6 @@ static const struct cci_reg_sequence mode_4096x2304[] = { { IMX214_REG_DIG_CROP_WIDTH, 4096 }, { IMX214_REG_DIG_CROP_HEIGHT, 2304 }, - { IMX214_REG_VTPXCK_DIV, IMX214_DEFAULT_VTPXCK_DIV }, - { IMX214_REG_VTSYCK_DIV, IMX214_DEFAULT_VTSYCK_DIV }, - { IMX214_REG_PREPLLCK_VT_DIV, IMX214_DEFAULT_PREPLLCK_VT_DIV }, - { IMX214_REG_PLL_VT_MPY, IMX214_DEFAULT_PLL_VT_MPY }, - { IMX214_REG_OPPXCK_DIV, IMX214_DEFAULT_OPPXCK_DIV }, - { IMX214_REG_OPSYCK_DIV, IMX214_DEFAULT_OPSYCK_DIV }, - { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE }, - - { IMX214_REG_REQ_LINK_BIT_RATE, - IMX214_LINK_BIT_RATE_MBPS(IMX214_LINK_BIT_RATE(IMX214_DEFAULT_CLK_FREQ)) }, - { CCI_REG8(0x3A03), 0x09 }, { CCI_REG8(0x3A04), 0x50 }, { CCI_REG8(0x3A05), 0x01 }, @@ -384,17 +373,6 @@ static const struct cci_reg_sequence mode_1920x1080[] = { { IMX214_REG_DIG_CROP_WIDTH, 1920 }, { IMX214_REG_DIG_CROP_HEIGHT, 1080 }, - { IMX214_REG_VTPXCK_DIV, IMX214_DEFAULT_VTPXCK_DIV }, - { IMX214_REG_VTSYCK_DIV, IMX214_DEFAULT_VTSYCK_DIV }, - { IMX214_REG_PREPLLCK_VT_DIV, IMX214_DEFAULT_PREPLLCK_VT_DIV }, - { IMX214_REG_PLL_VT_MPY, IMX214_DEFAULT_PLL_VT_MPY }, - { IMX214_REG_OPPXCK_DIV, IMX214_DEFAULT_OPPXCK_DIV }, - { IMX214_REG_OPSYCK_DIV, IMX214_DEFAULT_OPSYCK_DIV }, - { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE }, - - { IMX214_REG_REQ_LINK_BIT_RATE, - IMX214_LINK_BIT_RATE_MBPS(IMX214_LINK_BIT_RATE(IMX214_DEFAULT_CLK_FREQ)) }, - { CCI_REG8(0x3A03), 0x04 }, { CCI_REG8(0x3A04), 0xF8 }, { CCI_REG8(0x3A05), 0x02 }, @@ -428,9 +406,6 @@ static const struct cci_reg_sequence mode_table_common[] = { /* ATR setting */ { IMX214_REG_ATR_FAST_MOVE, 2 }, - /* external clock setting */ - { IMX214_REG_EXCK_FREQ, IMX214_EXCK_FREQ(IMX214_DEFAULT_CLK_FREQ / 1000000) }, - /* global setting */ /* basic config */ { IMX214_REG_MASK_CORR_FRAMES, IMX214_CORR_FRAMES_MASK }, @@ -800,6 +775,30 @@ static int imx214_entity_init_state(struct v4l2_subdev *subdev, return 0; } +static int imx214_set_clock(struct imx214 *imx214) +{ + int ret = 0; + + cci_write(imx214->regmap, IMX214_REG_VTPXCK_DIV, + IMX214_DEFAULT_VTPXCK_DIV, &ret); + cci_write(imx214->regmap, IMX214_REG_VTSYCK_DIV, + IMX214_DEFAULT_VTSYCK_DIV, &ret); + cci_write(imx214->regmap, IMX214_REG_PREPLLCK_VT_DIV, + IMX214_DEFAULT_PREPLLCK_VT_DIV, &ret); + cci_write(imx214->regmap, IMX214_REG_PLL_VT_MPY, + IMX214_DEFAULT_PLL_VT_MPY, &ret); + cci_write(imx214->regmap, IMX214_REG_OPPXCK_DIV, + IMX214_DEFAULT_OPPXCK_DIV, &ret); + cci_write(imx214->regmap, IMX214_REG_OPSYCK_DIV, + IMX214_DEFAULT_OPSYCK_DIV, &ret); + cci_write(imx214->regmap, IMX214_REG_PLL_MULT_DRIV, + IMX214_PLL_SINGLE, &ret); + cci_write(imx214->regmap, IMX214_REG_EXCK_FREQ, + IMX214_EXCK_FREQ(IMX214_DEFAULT_CLK_FREQ / 1000000), &ret); + + return ret; +} + static int imx214_update_digital_gain(struct imx214 *imx214, u32 val) { int ret = 0; @@ -1032,6 +1031,7 @@ static int imx214_start_streaming(struct imx214 *imx214) const struct v4l2_mbus_framefmt *fmt; struct v4l2_subdev_state *state; const struct imx214_mode *mode; + int link_bit_rate; int ret; ret = cci_multi_reg_write(imx214->regmap, mode_table_common, @@ -1041,6 +1041,20 @@ static int imx214_start_streaming(struct imx214 *imx214) return ret; } + ret = imx214_set_clock(imx214); + if (ret) { + dev_err(imx214->dev, "failed to configure clock %d\n", ret); + return ret; + } + + link_bit_rate = IMX214_LINK_BIT_RATE(IMX214_DEFAULT_CLK_FREQ); + ret = cci_write(imx214->regmap, IMX214_REG_REQ_LINK_BIT_RATE, + IMX214_LINK_BIT_RATE_MBPS(link_bit_rate), NULL); + if (ret) { + dev_err(imx214->dev, "failed to configure link bit rate\n"); + return ret; + } + ret = cci_write(imx214->regmap, IMX214_REG_CSI_LANE_MODE, IMX214_CSI_4_LANE_MODE, NULL); if (ret) { From patchwork Sun Feb 16 18:46:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= X-Patchwork-Id: 13976670 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C86E1624E7; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="q675W2uW" Received: by smtp.kernel.org (Postfix) with ESMTPS id BBFC3C4CEEB; Sun, 16 Feb 2025 18:47:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739731621; bh=tAV0H/YfQkrwePED/61Mj0lYo/eE2jYkmketuS26SII=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=q675W2uW04UISF1jdMv8NhutvzYlkujBDoetd8qDZo5eGe5Fhy9oElOY+2eCXR4DZ uXKKMSEVm4Bl3KLyfm+LwGnDNAmsmRAsAPj2ELzX3+1dp1OwanL7gOVhhpOCJSaCAb C8yFQ75SrZZMeEUuI5TF8+JtoSm4lHdmcMx+WU56yMnJ5SH2iD4kQh7GHsg4u7DBOQ LQycVG2Sc+FwQDzRz13Uwxi49oTbIdjC/+1LU85qHBTUfDShuA1Ku4dTbunztTAXHA IQ2dh9f0QvrZnTzZH4lUQSqWVkryOKsj+LhN78lGG3oqDQudZVaHFaZp1YHgOBFtCp l+kK/2hs+DiZA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB8ACC021A4; Sun, 16 Feb 2025 18:47:01 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Sun, 16 Feb 2025 19:46:46 +0100 Subject: [PATCH 3/4] media: i2c: imx214: Read clock frequency from device tree Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250216-imx214_clk_freq-v1-3-812f40f07db3@apitzsch.eu> References: <20250216-imx214_clk_freq-v1-0-812f40f07db3@apitzsch.eu> In-Reply-To: <20250216-imx214_clk_freq-v1-0-812f40f07db3@apitzsch.eu> To: Ricardo Ribalda , Sakari Ailus , Mauro Carvalho Chehab Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr?= =?utf-8?q?=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739731620; l=7210; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=grVCuiPNEUTKhmrGuULv55LCFhY0R7bLn+Lg7E4eRXU=; b=Euvh4M4uJ5TN0bhzzwbMTN2ocemsb7KjzTp0n3Z1oA4yR7qszwDPyRaAKebtMl7IbkhJL8tI7 eLGZzLrX3cCAFvTEC718Ac6n4wvBZKiooAb8FgN69QZUoVra3Rbc4Ss X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: André Apitzsch Replace the hard coded external clock frequency by the one read from device tree. Signed-off-by: André Apitzsch --- drivers/media/i2c/imx214.c | 99 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 79 insertions(+), 20 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 53b6b427f263a8ad7e3a0d1f711ece234601100e..c3d55259d6fd1c4ca96f52833864bdfe6bedf13a 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -30,11 +30,10 @@ #define IMX214_REG_FAST_STANDBY_CTRL CCI_REG8(0x0106) -#define IMX214_DEFAULT_CLK_FREQ 24000000 -#define IMX214_DEFAULT_LINK_FREQ 600000000 +#define IMX214_CLK_FREQ_24000KHZ 24000000 +#define IMX214_LINK_FREQ_600MHZ 600000000 /* Keep wrong link frequency for backward compatibility */ #define IMX214_DEFAULT_LINK_FREQ_LEGACY 480000000 -#define IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10) #define IMX214_FPS 30 /* V-TIMING internal */ @@ -233,6 +232,22 @@ static const char * const imx214_supply_name[] = { #define IMX214_NUM_SUPPLIES ARRAY_SIZE(imx214_supply_name) +static const s64 link_freq[] = { + IMX214_LINK_FREQ_600MHZ, +}; + +struct imx214_clk_params { + u32 clk_freq; + u64 link_freq; +}; + +static const struct imx214_clk_params imx214_clk_params[] = { + { + .clk_freq = IMX214_CLK_FREQ_24000KHZ, + .link_freq = IMX214_LINK_FREQ_600MHZ, + }, +}; + /* * The supported formats. * This table MUST contain 4 entries per format, to cover the various flip @@ -270,6 +285,8 @@ struct imx214 { struct clk *xclk; struct regmap *regmap; + const struct imx214_clk_params *clk_params; + struct v4l2_subdev sd; struct media_pad pad; @@ -794,7 +811,7 @@ static int imx214_set_clock(struct imx214 *imx214) cci_write(imx214->regmap, IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE, &ret); cci_write(imx214->regmap, IMX214_REG_EXCK_FREQ, - IMX214_EXCK_FREQ(IMX214_DEFAULT_CLK_FREQ / 1000000), &ret); + IMX214_EXCK_FREQ(imx214->clk_params->clk_freq / 1000000), &ret); return ret; } @@ -899,9 +916,6 @@ static const struct v4l2_ctrl_ops imx214_ctrl_ops = { static int imx214_ctrls_init(struct imx214 *imx214) { - static const s64 link_freq[] = { - IMX214_DEFAULT_LINK_FREQ - }; static const struct v4l2_area unit_size = { .width = 1120, .height = 1120, @@ -910,6 +924,7 @@ static int imx214_ctrls_init(struct imx214 *imx214) struct v4l2_fwnode_device_properties props; struct v4l2_ctrl_handler *ctrl_hdlr; int exposure_max, exposure_def; + int pixel_rate; int hblank; int i, ret; @@ -922,15 +937,25 @@ static int imx214_ctrls_init(struct imx214 *imx214) if (ret) return ret; + pixel_rate = imx214->clk_params->link_freq * 8 / 10; imx214->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, NULL, V4L2_CID_PIXEL_RATE, 0, - IMX214_DEFAULT_PIXEL_RATE, 1, - IMX214_DEFAULT_PIXEL_RATE); + pixel_rate, 1, pixel_rate); + + for (i = 0; i < ARRAY_SIZE(link_freq); ++i) { + if (imx214->clk_params->link_freq == link_freq[i]) + break; + } + if (i == ARRAY_SIZE(link_freq)) { + dev_err(imx214->dev, "link frequency %lld not supported\n", + imx214->clk_params->link_freq); + return -EINVAL; + } imx214->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, NULL, V4L2_CID_LINK_FREQ, ARRAY_SIZE(link_freq) - 1, - 0, link_freq); + i, link_freq); if (imx214->link_freq) imx214->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; @@ -1047,7 +1072,7 @@ static int imx214_start_streaming(struct imx214 *imx214) return ret; } - link_bit_rate = IMX214_LINK_BIT_RATE(IMX214_DEFAULT_CLK_FREQ); + link_bit_rate = IMX214_LINK_BIT_RATE(imx214->clk_params->clk_freq); ret = cci_write(imx214->regmap, IMX214_REG_REQ_LINK_BIT_RATE, IMX214_LINK_BIT_RATE_MBPS(link_bit_rate), NULL); if (ret) { @@ -1238,7 +1263,20 @@ static int imx214_identify_module(struct imx214 *imx214) return 0; } -static int imx214_parse_fwnode(struct device *dev) +static int imx214_has_link_freq(struct imx214 *imx214, u64 link_frequency) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(imx214_clk_params); ++i) { + if (imx214_clk_params[i].link_freq == link_frequency) { + imx214->clk_params = &imx214_clk_params[i]; + break; + } + } + return (i < ARRAY_SIZE(imx214_clk_params)); +} + +static int imx214_parse_fwnode(struct device *dev, struct imx214 *imx214) { struct fwnode_handle *endpoint; struct v4l2_fwnode_endpoint bus_cfg = { @@ -1268,13 +1306,14 @@ static int imx214_parse_fwnode(struct device *dev) dev_warn(dev, "Only one link-frequency supported, please review your DT. Continuing anyway\n"); for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) { - if (bus_cfg.link_frequencies[i] == IMX214_DEFAULT_LINK_FREQ) + if (imx214_has_link_freq(imx214, bus_cfg.link_frequencies[i])) break; if (bus_cfg.link_frequencies[i] == IMX214_DEFAULT_LINK_FREQ_LEGACY) { dev_warn(dev, "link-frequencies %d not supported, please review your DT. Continuing anyway\n", - IMX214_DEFAULT_LINK_FREQ); + IMX214_LINK_FREQ_600MHZ); + imx214->clk_params = &imx214_clk_params[1]; break; } } @@ -1282,7 +1321,7 @@ static int imx214_parse_fwnode(struct device *dev) if (i == bus_cfg.nr_of_link_frequencies) ret = dev_err_probe(dev, -EINVAL, "link-frequencies %d not supported, please review your DT\n", - IMX214_DEFAULT_LINK_FREQ); + IMX214_LINK_FREQ_600MHZ); done: v4l2_fwnode_endpoint_free(&bus_cfg); @@ -1294,16 +1333,17 @@ static int imx214_probe(struct i2c_client *client) { struct device *dev = &client->dev; struct imx214 *imx214; + u32 xclk_freq; int ret; - ret = imx214_parse_fwnode(dev); - if (ret) - return ret; - imx214 = devm_kzalloc(dev, sizeof(*imx214), GFP_KERNEL); if (!imx214) return -ENOMEM; + ret = imx214_parse_fwnode(dev, imx214); + if (ret) + return ret; + imx214->dev = dev; imx214->xclk = devm_clk_get(dev, NULL); @@ -1311,7 +1351,26 @@ static int imx214_probe(struct i2c_client *client) return dev_err_probe(dev, PTR_ERR(imx214->xclk), "failed to get xclk\n"); - ret = clk_set_rate(imx214->xclk, IMX214_DEFAULT_CLK_FREQ); + ret = device_property_read_u32(dev, "clock-frequency", &xclk_freq); + if (ret) { + dev_warn(dev, + "clock-frequency not set, please review your DT. Fallback to default\n"); + xclk_freq = IMX214_CLK_FREQ_24000KHZ; + } + + switch (xclk_freq) { + case IMX214_CLK_FREQ_24000KHZ: + if (imx214->clk_params->clk_freq != xclk_freq) + return dev_err_probe(imx214->dev, -EINVAL, + "combination of clock and link frequency is not supported\n"); + break; + default: + return dev_err_probe(imx214->dev, -EINVAL, + "external clock frequency %u is not supported\n", + xclk_freq); + } + + ret = clk_set_rate(imx214->xclk, xclk_freq); if (ret) return dev_err_probe(dev, ret, "failed to set xclk frequency\n"); From patchwork Sun Feb 16 18:46:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= X-Patchwork-Id: 13976674 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53D8132C8B; Sun, 16 Feb 2025 18:47:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739731622; cv=none; b=UVX5BG6TwXCZryuu+TtXN8Z5xv9haUm4tQwD9HXa58AwW+Jl8Ds4BmoRD+yqSGjVeyEmk1amhQ69mkEtyZJ60vK7Q5IOWzNwqGNOKAYs2FWFauqq3h65vl85C7Y1J63wBY7vtj9SxZ38nUK2nWwITQDeYG2ecYLrBdliOhAXuhY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739731622; c=relaxed/simple; bh=NBkyLSUP9n9Ax4+7aC60v72hjL1RvF641HX71E/k+i8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RqdWhBc+MgWkJT6pNNqbKq9Cvgmpr3vQir8k7PoJAd8vs3V4DotOtPD98z+bFAqI52djAacst2q1xoTXIj1svoIEwRelGBLk+gGt3V8CGxy/y8oOkl4i/AV3GKFsWvFD2aJ1oQNwpm5nk6RqC78sSAzOA4WJRm6eXYWmZi2JYM4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MIhZYaZ3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MIhZYaZ3" Received: by smtp.kernel.org (Postfix) with ESMTPS id CAE0EC4CEEE; Sun, 16 Feb 2025 18:47:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739731621; bh=NBkyLSUP9n9Ax4+7aC60v72hjL1RvF641HX71E/k+i8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MIhZYaZ3tLTZUlFRLPquLLedClEatwHqI1HH46K4/f6h32get/Uq8jefv/3fRUBYC Tf9xB3ooNSNflo6mJQINlizyaiVc58t2sJs2nb3zNg4TCLpVH8BMiG11xzlwh/bRWm 0KHicL3HROtCBTzNMuNKKqo6JVENDwgfJvqteF6H31Owd0mfy/3ZvjZoR/06A5nagJ g2x9GDlN6sYb/uLCyNOB4WijzjPDOEnGyAVRh/y4CxJxP5sA9zvfGWiq0A4Cy/gbi+ MD9hy5k8bV94Oy9RtpAeUK9TQo3RuQPanZQiiNmKsddd1HsXHCaPVV6SvpPrti+sMv Yq5XHV46/e0Jg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF0E3C02198; Sun, 16 Feb 2025 18:47:01 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Sun, 16 Feb 2025 19:46:47 +0100 Subject: [PATCH 4/4] media: i2c: imx214: Add support for 23.88MHz clock Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250216-imx214_clk_freq-v1-4-812f40f07db3@apitzsch.eu> References: <20250216-imx214_clk_freq-v1-0-812f40f07db3@apitzsch.eu> In-Reply-To: <20250216-imx214_clk_freq-v1-0-812f40f07db3@apitzsch.eu> To: Ricardo Ribalda , Sakari Ailus , Mauro Carvalho Chehab Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr?= =?utf-8?q?=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739731620; l=2166; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=WazSPfo9iHxmaDrm3SErM4Vh2VDI2d/EHPhwKDpeOK0=; b=BoyYCYkxO//ewUb9c7pOCpeeStR0dHu5eekomgEGJ/18Mc+UzekMg0rTJBYYMRtU59/G3WqLu dqSnzYLJfqMBpauXbMRRAAdBwHU8X0wquKgiHnzTAYP1sXqeDoc0dSy X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: André Apitzsch Qualcomm MSM8916 devices only provide an external clock of 23.88MHz. Make the sensor usable by those devices by adding support for this frequency. Signed-off-by: André Apitzsch --- drivers/media/i2c/imx214.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index c3d55259d6fd1c4ca96f52833864bdfe6bedf13a..e24c76e01ab5070c073d082b1a2969cff3e17f9f 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -30,7 +30,10 @@ #define IMX214_REG_FAST_STANDBY_CTRL CCI_REG8(0x0106) +#define IMX214_CLK_FREQ_23880KHZ 23880000 #define IMX214_CLK_FREQ_24000KHZ 24000000 + +#define IMX214_LINK_FREQ_597MHZ 597000000 #define IMX214_LINK_FREQ_600MHZ 600000000 /* Keep wrong link frequency for backward compatibility */ #define IMX214_DEFAULT_LINK_FREQ_LEGACY 480000000 @@ -233,6 +236,7 @@ static const char * const imx214_supply_name[] = { #define IMX214_NUM_SUPPLIES ARRAY_SIZE(imx214_supply_name) static const s64 link_freq[] = { + IMX214_LINK_FREQ_597MHZ, IMX214_LINK_FREQ_600MHZ, }; @@ -242,6 +246,10 @@ struct imx214_clk_params { }; static const struct imx214_clk_params imx214_clk_params[] = { + { + .clk_freq = IMX214_CLK_FREQ_23880KHZ, + .link_freq = IMX214_LINK_FREQ_597MHZ, + }, { .clk_freq = IMX214_CLK_FREQ_24000KHZ, .link_freq = IMX214_LINK_FREQ_600MHZ, @@ -1320,8 +1328,7 @@ static int imx214_parse_fwnode(struct device *dev, struct imx214 *imx214) if (i == bus_cfg.nr_of_link_frequencies) ret = dev_err_probe(dev, -EINVAL, - "link-frequencies %d not supported, please review your DT\n", - IMX214_LINK_FREQ_600MHZ); + "provided link-frequencies not supported, please review your DT\n"); done: v4l2_fwnode_endpoint_free(&bus_cfg); @@ -1359,6 +1366,7 @@ static int imx214_probe(struct i2c_client *client) } switch (xclk_freq) { + case IMX214_CLK_FREQ_23880KHZ: case IMX214_CLK_FREQ_24000KHZ: if (imx214->clk_params->clk_freq != xclk_freq) return dev_err_probe(imx214->dev, -EINVAL,