From patchwork Mon Feb 17 08:17:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13977263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85F43C021A6 for ; Mon, 17 Feb 2025 08:18:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tjwKC-0001ya-2x; Mon, 17 Feb 2025 03:17:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tjwK9-0001y8-Rq for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:17:54 -0500 Received: from mail-qv1-xf30.google.com ([2607:f8b0:4864:20::f30]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tjwK8-0000zX-5n for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:17:53 -0500 Received: by mail-qv1-xf30.google.com with SMTP id 6a1803df08f44-6e672a21b9dso15955896d6.1 for ; Mon, 17 Feb 2025 00:17:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1739780271; x=1740385071; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=XmLG5UQJV7cOfmKz1oOTzmfuK6M6OFxQ8TpTbwfoB7Q=; b=YCVQ8iP0F37aXlVVeCjjSPzzg6x9/fvFF0NC8Hm7KcuJ3a1/dA9kYygxcYdLdObN3M q+qBqTvjhiDpKR97k2wpXDCUkdSvLojO1ty8K9ezf1vO1YEZsABPP7MicjGvV4i2va/y Hnza+IcC6sx93USrai1iiDjEHm9XoFw+PCt9XSkYd7Rw7ltuC7anFkYuJVv5gXI2TZLd B3hf23t1EtEMlegXWUM5GSkHfAQwV2hDrAiGbr/Dd6e/x2LQtDdouNmWkBjK2hAiPMvT f0BCUYUabTXZBTmBnQ+AJpHyq4mKuGxGQ5tYb6n0ar6lrPi6UK9kMY97JADtNZhruRAH 9s4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739780271; x=1740385071; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=XmLG5UQJV7cOfmKz1oOTzmfuK6M6OFxQ8TpTbwfoB7Q=; b=ahbkUTVdXHLRWEcRxks7IgVlpMVoB8S0Vn5XH4YHVPzozzzpTDF0NONPUtDbOedAb0 D9C6PjDy9kBiuXjwZU1u2w4Z1rwYxJZf1yMBdreabSEAkXMwXvnSl6z7WG499GF5Dnz4 Xji24+hTbyTWVMoxv7CiLSMeGNJhT5lhKaPB1ytSr6Wa8o8Zkc4G80bIDuPo2UtjTYJf iDwbPsZhBEIykyrAZyVGGlF07OOAMOLqYe2G8sG5gcW8CH4S3ua5XK9TBJgNVPOd1E9W nO8WfLdXetirqbG1QfAPhxxZegB3P+IDOghtgBaoxzNQEobi4tqfSXQQbVcRY3jQ02v2 tS2g== X-Gm-Message-State: AOJu0YxYPNoNuHIs3luWhtglwieFjnBSVQIEVOMw7ouMnR0VBM06Styv ukASyaN9fUsQvTtM3NKVQz4fWCGHIuSwvVJGSTNNcwv433o1WCUQRNnOVYlzPg2GkGjB0xRyJTL 9DMB5Pqw3LWHNhyqhPlJQd/KCOs9EoShWAZVGJHOzt8fKJ1KZ2ZRbBTEzmxtbWdjViuAyuMBT88 fK2bb637Ud2Kz+x3tnLy477SMXpA+Tu4QOv4T6sznlFA== X-Gm-Gg: ASbGncsXpD7z8t2kxzB+6gAQxcUQfhqWAcmSo6XJC6kTCtQGmrwGt4Ra1q1nQmzm+d8 hAAIi24BRElNw+qj7HOO/6N/dX+w3Gu5XPTHIZVa9AgMGR5+NFbAyr8WUTjVc2HIZ+d3i5N/KCQ cbYU1zlZC4jytt2/PFDxJuVqd61+zPBrsNamhKVmrY0wPVTi+4TDrZTqEWfzDTR8AmBeaQNpe7G 4B4AgwQ5zkXyx/v73oP7151cLz13Y/XCxvEVo5LOXiFumfc8bUrUEBvbe+Tl5CC47YdN4gwFfFL V6fcBYv6BoyVxnSZebhSb3MHx8dWUYRTrOHieqELvy4BZA== X-Google-Smtp-Source: AGHT+IFce0ent2uBbLukL8x0M56RKYBaZm4XiBGTPGtm2Dhp9QYczsv+ZkZni+JuM4bKnQyoKziQ5Q== X-Received: by 2002:ad4:5de8:0:b0:6e6:61f1:457f with SMTP id 6a1803df08f44-6e66ccc1198mr139344766d6.18.1739780270540; Mon, 17 Feb 2025 00:17:50 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e65d9f38absm49673346d6.88.2025.02.17.00.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2025 00:17:50 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 1/8] target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR Date: Mon, 17 Feb 2025 16:17:21 +0800 Message-Id: <20250217081730.9000-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250217081730.9000-1-yongxuan.wang@sifive.com> References: <20250217081730.9000-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::f30; envelope-from=yongxuan.wang@sifive.com; helo=mail-qv1-xf30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org As KVM_REG_RISCV_CSR includes several subtypes of CSR, rewrite the related macros and functions to prepare for other subtypes. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 70 +++++++++++++++++++++++--------------- 1 file changed, 43 insertions(+), 27 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 23ce77935940..e315fea46973 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -111,9 +111,8 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ KVM_REG_RISCV_CORE_REG(name)) -#define RISCV_CSR_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ - KVM_REG_RISCV_CSR_REG(name)) +#define RISCV_CSR_REG(env, idx) \ + kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, idx) #define RISCV_CONFIG_REG(env, name) \ kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ @@ -130,17 +129,20 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ KVM_REG_RISCV_VECTOR_CSR_REG(name)) -#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ +#define RISCV_GENERAL_CSR_REG(name) \ + (KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(name)) + +#define KVM_RISCV_GET_CSR(cs, env, idx, reg) \ do { \ - int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \ if (_ret) { \ return _ret; \ } \ } while (0) -#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ +#define KVM_RISCV_SET_CSR(cs, env, idx, reg) \ do { \ - int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \ if (_ret) { \ return _ret; \ } \ @@ -605,36 +607,50 @@ static int kvm_riscv_put_regs_core(CPUState *cs) return ret; } -static int kvm_riscv_get_regs_csr(CPUState *cs) +static int kvm_riscv_get_regs_general_csr(CPUState *cs) { CPURISCVState *env = &RISCV_CPU(cs)->env; - KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); - KVM_RISCV_GET_CSR(cs, env, sie, env->mie); - KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); - KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); - KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); - KVM_RISCV_GET_CSR(cs, env, scause, env->scause); - KVM_RISCV_GET_CSR(cs, env, stval, env->stval); - KVM_RISCV_GET_CSR(cs, env, sip, env->mip); - KVM_RISCV_GET_CSR(cs, env, satp, env->satp); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sstatus), env->mstatus); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sie), env->mie); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stvec), env->stvec); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sscratch), env->sscratch); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sepc), env->sepc); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(scause), env->scause); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stval), env->stval); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sip), env->mip); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(satp), env->satp); return 0; } -static int kvm_riscv_put_regs_csr(CPUState *cs) +static int kvm_riscv_put_regs_general_csr(CPUState *cs) { CPURISCVState *env = &RISCV_CPU(cs)->env; - KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); - KVM_RISCV_SET_CSR(cs, env, sie, env->mie); - KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); - KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); - KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); - KVM_RISCV_SET_CSR(cs, env, scause, env->scause); - KVM_RISCV_SET_CSR(cs, env, stval, env->stval); - KVM_RISCV_SET_CSR(cs, env, sip, env->mip); - KVM_RISCV_SET_CSR(cs, env, satp, env->satp); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sstatus), env->mstatus); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sie), env->mie); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stvec), env->stvec); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sscratch), env->sscratch); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sepc), env->sepc); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(scause), env->scause); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stval), env->stval); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sip), env->mip); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(satp), env->satp); + + return 0; +} + +static int kvm_riscv_get_regs_csr(CPUState *cs) +{ + kvm_riscv_get_regs_general_csr(cs); + + return 0; +} + +static int kvm_riscv_put_regs_csr(CPUState *cs) +{ + kvm_riscv_put_regs_general_csr(cs); return 0; } From patchwork Mon Feb 17 08:17:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13977265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 220B2C021A4 for ; Mon, 17 Feb 2025 08:18:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tjwKO-00025C-PH; Mon, 17 Feb 2025 03:18:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tjwKG-0001zL-7D for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:00 -0500 Received: from mail-qv1-xf2e.google.com ([2607:f8b0:4864:20::f2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tjwKE-000107-1B for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:17:59 -0500 Received: by mail-qv1-xf2e.google.com with SMTP id 6a1803df08f44-6e41e17645dso42262826d6.2 for ; Mon, 17 Feb 2025 00:17:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1739780277; x=1740385077; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=s8x/AUhlMa+i1pxB//o187dxahL7hFDjq4fu/AmY4EU=; b=fsLz0MA+/l7MN+8F8Sjq8Al3KWMQObmGIGsbm3yEerjR0FQWrDNwVod3cBuA6ibLK4 yH5R7hj7/6UtandLJxcqIQQDsT8+L7MIMuMfuDw/ExKGHeABpQnkG1QgYqpP+Rbg6VlU pQ/Fyv/xCvRZZxRsZkelB/eBwzdrSNvyVulQw+WPgxu86+/i73H0auFfX+/0G2hQgTmU z9VXYuVtPlza9w3CSYk64EQpreiwPvaMwg8VHCj10SFaUlBlXO6evxft/9MghVBQ7AOV DtBxTdJGlJALlXkIrC2e1PjsBcZJx6TLrnp2h0HgzMaEPzf9GoerAg3prcOuqbmA4gzd BVmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739780277; x=1740385077; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=s8x/AUhlMa+i1pxB//o187dxahL7hFDjq4fu/AmY4EU=; b=ev4zAqkmIk6PfyNmvDZJdF0UN1nzEEOrBE4lOA9XXle1x6dKBDVmju1J9MshrycCzm ITSh/31XMTUC22fyHxb+7VdnjmMpWpwBbLFCr+1Hecw2I5XwP98+G7PnTu9v1C3YFkoh EaHidFtbeLuB+zbwtaJZEZ6oU/e/nYkXthdrDPkQRQwhV7OuAbiQUCVCOXFfPJxHmmiv LgL89yInnF7GKUsyhJ5sc6lTRMfzNHzNfi4lFBrxI1NbHbJJnzkVpNJpy/GEOVMhdhUF l8snW4zH0HIuD87yvWrNR9oqZoyxUrkBpX1Li/zd3Z3XJxGSNTAvtFZaFAqgkL3CYSXQ HnYg== X-Gm-Message-State: AOJu0YyEMusd9VNfwUwidqRDPJI2ZrZm9hgLaR+x1i0Dr9hU3Zg0Nd6l 0NvdLupv4TfCjyH2srb6WlvVtqRPcxh53oP9wcC81dz1/U/4g4KjJogiYpDnwwg6v5G/AANGWdC B5PO8eCW6qu+Wr7pW3sU7AAGhW/DUEt6mG/B+DxDTL5/k/o+hbfhljbP/3PRIE9nPzH+xaBsDd5 A3rOfq2gFqBoV0J1BnQpInDIkeMqIJhjUTdMcqN+LU5Q== X-Gm-Gg: ASbGnctL3QOjUoqMYCly0ZAzlC/28DgHEBIeENi279WaVJSGKDH27I5DrutyIdZ1edr FN/Ep7C1WrwdkEQJH3qml3/MPlM0kh0xUh6Im6Qp31FcC7kbKP0lvH999biDyVvBE/meB9n8ZOJ 7ltsQpxGFOOSEppKrP9RIgPIL/961xUE3i+Ni5DZzu8maELo55wXwQC91YxDOFyqEwQnaQajCz5 j5+v2Ushzl86fh1Ef8xaXiVdAAEao8EOjq1xjCC/y/CmqW9vkm5kuvsfM95stWe9U00/tFU04Kj QbnG7K+uny29CePEX6ANfTMaXvjvsedZr8RX9ANdw0HjFQ== X-Google-Smtp-Source: AGHT+IHESTeJBCnbLB/7Px+mUg+wKxnOm1fKtPgG0Bp/rz+E/ijmCPv+2q1nl0fUS2aZG3e7x/YExA== X-Received: by 2002:a05:6214:c4b:b0:6e6:646e:a0f8 with SMTP id 6a1803df08f44-6e66ccb7abamr128248356d6.16.1739780276749; Mon, 17 Feb 2025 00:17:56 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e65d9f38absm49673346d6.88.2025.02.17.00.17.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2025 00:17:56 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA Date: Mon, 17 Feb 2025 16:17:22 +0800 Message-Id: <20250217081730.9000-3-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250217081730.9000-1-yongxuan.wang@sifive.com> References: <20250217081730.9000-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=yongxuan.wang@sifive.com; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add KVM_REG_RISCV_CSR_AIA support to get/set the context of AIA extension in VS mode. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 45 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index e315fea46973..e74c1d7cdcee 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -132,6 +132,9 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, #define RISCV_GENERAL_CSR_REG(name) \ (KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(name)) +#define RISCV_AIA_CSR_REG(name) \ + (KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(name)) + #define KVM_RISCV_GET_CSR(cs, env, idx, reg) \ do { \ int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \ @@ -641,9 +644,50 @@ static int kvm_riscv_put_regs_general_csr(CPUState *cs) return 0; } +static int kvm_riscv_get_regs_aia_csr(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + uint64_t mask = MAKE_64BIT_MASK(32, 32); + uint64_t val; + + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(siselect), env->siselect); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1), env->siprio[0]); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1h), env->siprio[8]); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2), env->siprio[16]); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2h), env->siprio[24]); + + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(sieh), val); + env->sie = set_field(env->sie, mask, val); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(siph), val); + riscv_cpu_update_mip(env, mask, val); + + return 0; +} + +static int kvm_riscv_put_regs_aia_csr(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + uint64_t mask = MAKE_64BIT_MASK(32, 32); + uint64_t val; + + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(siselect), env->siselect); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1), env->siprio[0]); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1h), env->siprio[8]); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2), env->siprio[16]); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2h), env->siprio[24]); + + val = get_field(env->sie, mask); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(sieh), val); + val = get_field(env->mip, mask); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(siph), val); + + return 0; +} + static int kvm_riscv_get_regs_csr(CPUState *cs) { kvm_riscv_get_regs_general_csr(cs); + kvm_riscv_get_regs_aia_csr(cs); return 0; } @@ -651,6 +695,7 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) static int kvm_riscv_put_regs_csr(CPUState *cs) { kvm_riscv_put_regs_general_csr(cs); + kvm_riscv_put_regs_aia_csr(cs); return 0; } From patchwork Mon Feb 17 08:17:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13977270 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19602C021A7 for ; Mon, 17 Feb 2025 08:19:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tjwKW-0002Gn-5r; Mon, 17 Feb 2025 03:18:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tjwKS-0002Ah-0d for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:12 -0500 Received: from mail-qv1-xf35.google.com ([2607:f8b0:4864:20::f35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tjwKK-00011G-Kw for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:11 -0500 Received: by mail-qv1-xf35.google.com with SMTP id 6a1803df08f44-6e67fad4671so5279856d6.1 for ; Mon, 17 Feb 2025 00:18:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1739780283; x=1740385083; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=Q3Bh+vRBI9kfj9ST5eVx6et/EgzdN8R/GNSb/Gp3tTc=; b=AR4t6kSdBbCbrfWDp2C3jGUae6hAmlFF/q4AStgkCXHt6VFaXNl70Rpo/EtXrvWszh uPNDL7oT1DpRRGy60zYo87YcSJzDbJhz9M8FJylKT9Vfh+UymP0bUkPBccoPPIuZjFZJ Lna9WssefCbLh1zbjz/6CjKgJRyuT0D30eakmqS1tPfJbs25Rgj9oFtkWMHHKQFyDqOL uIrvOQICS0dnTtygNnyP10B5PuT2W8SFZhWunQOstvu4LTpB+oNf1pfGk1PXghCQ60Hh LUA507/tlj3lw29FT8UL1MZNaWNZxRXv5qf2dUVwjwNYiyDZfewjf8UTfcbti9m4k+lI r4+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739780283; x=1740385083; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Q3Bh+vRBI9kfj9ST5eVx6et/EgzdN8R/GNSb/Gp3tTc=; b=LGzukSWxkM5Lpr3QNSQgAHuG3lUm7nlLJmrR4/aPY3jOyMRIBCc/ns5YYXHdLVpQu7 e8sXEr1C8n4Y8DxKTbiNxI/T6TBwRuqXgfM6Jd4bb5zQwff0ii/qyaymREN+Kea2SAT9 6W3NjruqmXo+sE1t0256iePvE43LLvuFU90nxK/lHj0MF4HvKXpR3v0OwzUbhIs0EsMv 6w9bKEIM3sJOaTGp7v/W8fxD9Cm+subso0raK5TND1GRYsNhUKMo1pZyTRnVc6J+ujZy Dtv4zWs+QAa57OyDKVH7RjXtQ6zWb9myA7bhX/a6Y5Qnbk8SbmJ0eV1bE8HI8axKEnSj zyCQ== X-Gm-Message-State: AOJu0YyBtOx9S+6ZdLMyZCCR9mCj1aw4w8swp3TnZXWdlZ969Qa7LyZP /PGJCd2KFXcsDkb24Zkiy9nuy6i2VV+bxKII+M70kGgxqKOcG8M8D2QUIm6odpNYaDT3gtnTRBk ApnxFdfGrgKF0YfQbvR6d4Ct6HYN8m4PQgW3ztQ5CjSie5urUYX2dzMtsKEZ3tml/1u8KHyr8LO 6bYyvAo9hWxpodGiAreEI/il5BCWehjqLPUGlBFVKuqQ== X-Gm-Gg: ASbGnctPqAfmKZmpuGwCfo/g/8kInppHQO7wQDERxYCBSVDuGptr1bkUvzh2whCxJ6C WElJt1ixbd9Y31Ict84a2ltBDubUPak9yOYlcPmL6DbqoEvT2qc1XPJY+JRjHkLYxv8jkNdYu+2 tCpJbOgTKy0zNJHDIMxpd2DcMjpEhFsm6NXx6eOD8lGn18Il5VAqRqfPkeuCjab64q8lZhdSCVD oEANTyUp8KaRykDom3xCyAsZ4GssM8pTWQscRNfqsyd85/L+yv08wUhyQ5AryLkLN3+mfyGF7ex kk7nxjqKz2D58xNBxNFnnfAURU8JBYG8hY9QyvR6IT0MZA== X-Google-Smtp-Source: AGHT+IELU3mvD3QGaGLyVLLCYxlaAzw2k6zmPzfP4iFKRKx5g0Z/GQMRrS41GCT/aq/PTxQfoKWdyA== X-Received: by 2002:a05:6214:29cb:b0:6e4:2ef4:2a01 with SMTP id 6a1803df08f44-6e66ccccc72mr131501216d6.22.1739780283120; Mon, 17 Feb 2025 00:18:03 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e65d9f38absm49673346d6.88.2025.02.17.00.17.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2025 00:18:02 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 3/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN Date: Mon, 17 Feb 2025 16:17:23 +0800 Message-Id: <20250217081730.9000-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250217081730.9000-1-yongxuan.wang@sifive.com> References: <20250217081730.9000-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=yongxuan.wang@sifive.com; helo=mail-qv1-xf35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add KVM_REG_RISCV_CSR_SMSTATEEN support to get/set the context of Smstateen extension in VS mode. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index e74c1d7cdcee..79e80cdf7406 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -135,6 +135,9 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, #define RISCV_AIA_CSR_REG(name) \ (KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(name)) +#define RISCV_SMSTATEEN_CSR_REG(name) \ + (KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(name)) + #define KVM_RISCV_GET_CSR(cs, env, idx, reg) \ do { \ int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \ @@ -684,10 +687,31 @@ static int kvm_riscv_put_regs_aia_csr(CPUState *cs) return 0; } +static int kvm_riscv_get_regs_smstateen_csr(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + + KVM_RISCV_GET_CSR(cs, env, + RISCV_SMSTATEEN_CSR_REG(sstateen0), env->sstateen[0]); + + return 0; +} + +static int kvm_riscv_put_regs_smstateen_csr(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + + KVM_RISCV_SET_CSR(cs, env, + RISCV_SMSTATEEN_CSR_REG(sstateen0), env->sstateen[0]); + + return 0; +} + static int kvm_riscv_get_regs_csr(CPUState *cs) { kvm_riscv_get_regs_general_csr(cs); kvm_riscv_get_regs_aia_csr(cs); + kvm_riscv_get_regs_smstateen_csr(cs); return 0; } @@ -696,6 +720,7 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) { kvm_riscv_put_regs_general_csr(cs); kvm_riscv_put_regs_aia_csr(cs); + kvm_riscv_put_regs_smstateen_csr(cs); return 0; } From patchwork Mon Feb 17 08:17:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13977267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59DD6C021A0 for ; Mon, 17 Feb 2025 08:19:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tjwKU-0002Es-VR; Mon, 17 Feb 2025 03:18:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tjwKS-0002Bo-Cm for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:13 -0500 Received: from mail-qv1-xf29.google.com ([2607:f8b0:4864:20::f29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tjwKP-00011k-TE for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:12 -0500 Received: by mail-qv1-xf29.google.com with SMTP id 6a1803df08f44-6e67f377236so5729076d6.1 for ; Mon, 17 Feb 2025 00:18:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1739780289; x=1740385089; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=CIOoUkbjk51N51acNzDriCfyDC8X79FyXFjaBdinybo=; b=fqX7TDd+On4XSKBsKIVBgrG7w7ssHrSo+jj2zIRXaxfhRB29xtqt9Al8yH7a5UvZNw eqMsbT/y0J4cT89O7XbwR9idbtH9+K/9MC28pJkfVlP7lzy7Xd8xgtMolOJil3ocrRb0 RLA3JVdHbfx8bMINoT+B4oB91mQzRARfolGGoolz2Z1nGedkLbgxRknr0oLh0d10CJ5V XTZolUOdY0LwFK9/KFqkmw+UyCD9D2tPGj8pDB8y/EPgddMYsTvmDc+3hjG7GHXnqQ3e FOBMaOsQTT9XEL6ncNGWeV2wcFN28BGvuDJ+221zzmdMycJjDzMqJ6dhzVWZgArfnL5K x1Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739780289; x=1740385089; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=CIOoUkbjk51N51acNzDriCfyDC8X79FyXFjaBdinybo=; b=VaWuvTaKRCxxpBJzKmFO3zz72ItZyK/cEIDb7Km+ldAimqfd/botrqqxbGTu/2SYDf jC8XckcX7pPu0uQPXq3v0ogrIsFlLs1kGN657HUrWP3aN1K7ph9HgAsndI59+lL0y/AF giNqoFOzpLA1GVUMM6HXNXGio+kSWnh9MDNIQP40ubsK4+H09WDeD28CC0wKFjHgzLFV t2sxn/oPstopKQBcdT1TrdDgr/J8xI9sEbCavNH7RmMx9IwI5vrCMEe8UL37ldaBte9Y n6zCWs0DEh2zb0Gmrk6YZrDV8w5CuLJsIomvD+19zL1AYviarrWP9QEl9sHvs+saTf2f 0LYg== X-Gm-Message-State: AOJu0Yx6meCu6mQUJZaKUr7vm1Vhr/dEehx2dHYHHRR0CXMdXXZh7Ow/ g6Nw1o0oPpNrCcV27+40Fv3AGe64cULOk4y1ReJd7g1TFJ2hI+eKR9fbI09Pw8MSt2sdVsERQBv jYsxWu+pcgBW2KDjk69/bFPvidAzxLHmUTYEvvm3HEIkbXtY2z0d+sIjqi+eIbg2Rg2Mp/v8Xoc QtYBezQerIQ0LQUdEicFInR1ZJr566MXxwtn/rN+1P2w== X-Gm-Gg: ASbGncuq9novyPLsoKpxSbi69CDWJ7cwRj51/sYcmzanHFe/U6jBmb2g90ywrLPVh/9 ARSAvtXjZLCZ5kZzZbDOGmGfJARSA/QHCB1py0OJ5I7QDPo3EMWuoorKhr9dzLkxQLXyr/r6QTe m+f6vTgyxFuOAzRZ+bVpwf5rrxmZTmYXcI7tC35G3EAeyGuxoBl50fcMnt/t7hoSnKAKQ+flnil 0W0aYWNL4Iib94vJDAxQjAf9RpYxa29hGu36tqZzbSxrGGvObKIBIUoQ/OkZD6B5tnkgW3cUwMa 0hs7kloQn8kfjfBf6p306jh+nsUVZwKMlB4MQdaE3UnSrA== X-Google-Smtp-Source: AGHT+IEfZANQhcZDUv0bTis6sSavH9H1aY3LSqVQvrgPQLJ8aH649IbHLwd7nLcMsDV/2jlrYwF8Gw== X-Received: by 2002:a05:6214:262c:b0:6dd:d317:e0aa with SMTP id 6a1803df08f44-6e66cc85b7emr143122026d6.8.1739780288589; Mon, 17 Feb 2025 00:18:08 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e65d9f38absm49673346d6.88.2025.02.17.00.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2025 00:18:08 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH 4/8] target/riscv: add helper to get CSR name Date: Mon, 17 Feb 2025 16:17:24 +0800 Message-Id: <20250217081730.9000-5-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250217081730.9000-1-yongxuan.wang@sifive.com> References: <20250217081730.9000-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::f29; envelope-from=yongxuan.wang@sifive.com; helo=mail-qv1-xf29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add a helper function to get CSR name from CSR number. Signed-off-by: Yong-Xuan Wang --- target/riscv/cpu.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 616c3bdc1c24..133d1852ee1e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -920,8 +920,12 @@ extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); -void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); +static inline const char *riscv_get_csr_name(int csr_no) +{ + return csr_ops[csr_no & (CSR_TABLE_SIZE - 1)].name; +} +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); target_ulong riscv_new_csr_seed(target_ulong new_value, target_ulong write_mask); From patchwork Mon Feb 17 08:17:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13977272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2C28C021A0 for ; Mon, 17 Feb 2025 08:19:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tjwKc-0002Jc-9G; Mon, 17 Feb 2025 03:18:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tjwKZ-0002JD-Mx for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:21 -0500 Received: from mail-qk1-x72f.google.com ([2607:f8b0:4864:20::72f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tjwKX-00012D-SI for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:19 -0500 Received: by mail-qk1-x72f.google.com with SMTP id af79cd13be357-7c09a30e14dso142784585a.0 for ; Mon, 17 Feb 2025 00:18:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1739780296; x=1740385096; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=WSMPQ783pz0wo6KPO/CsW7bAJCl7WJZGQCgE4WKR3Zk=; b=i5xHQ8pEF/UEUxr2ZSmtXyP5LNFzh+mdTsQC7P8LLG8VW+t/vWl7UTgPK7UlatpSB/ T1GyKZm5OvN0tR8DCOVVkEwOj4x9tbEX/+wXN69qLXa8BURouweN2n1it1jgCYT3mjpB KNJNTSpS38630mwolTR78plpGgjPdPLEVwViv9I86JS6z92aNUNfJDZlz7a3uWm/JgpT TFd5aPXvfjd0MwJAuyayTTOllxgW3Nn1AJSX/y8R+5q4BGgkHQDShqSL5OA+B1tITJ8P 0N49JyYW5RB2AvyO3Xv8P4YM/pBc4kceaqfAeOpLueo1qQ9Uve3Z8mfMYxI/A4ismFaO 5fAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739780296; x=1740385096; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=WSMPQ783pz0wo6KPO/CsW7bAJCl7WJZGQCgE4WKR3Zk=; b=WfcaSuGEWdgo/d9gKhOz1QiFGVjfo13iNTtRrPulehxvaz59Oh8xigZaZ249CkJL/X MYat6+lx1tvTn3ASwnuSWvuHdiV+CeMzQUWZt07IwcKGQecFSxu8Epx4Y8M5fC5YlUNO YS16t9Pwzor1LaMY+g6Swzue82Ag4CtpWtt6GUnnrV5C8e5sStKVqacwyttk0v0mS+UU jDJmrbfqic2LlV60pl+UzzHy61nZlSeZu7xqfcFOTuVy2yS7Ln793SbDvhmYBm5J0DeZ m04tYK8i0j64KpqlpQFgwor+RgaNwNtzvtvVbWAekLDPAwVJYXWeNUI+eW5qu1SUy+SY 1b4w== X-Gm-Message-State: AOJu0YwJlsaoW7VJFqRz0Q/+9kSqLNxiyWvpxI6293/tMnEbhDM7/vFS a/LnFd2+0+meH/DvDyi8UhM7gMgfitFKD9SVjBzE8hzvNMSa+EWvYkDVUUn0oaqvj5ukgfg4nL0 AhGaHfZUYwtKx6Fqb2ELtVhgKeNOBuadBVDCvJ9docNMWz+K00rCaC/iWjc7hNaJ+gZpNovkcMC LPwpV1mqv9/7EzFLlfnFuu3rCrrPwby+JiDzBd2EQwww== X-Gm-Gg: ASbGnctazh/YQ9xStOVzYVZA3pMwMr2Dqj29fMT5wx4hzoZ8elPWpHAZ3Bvg1qeuUjz z4m8qO9fDslIWeFcmURnAp1lOaNwFuzT1ilD6RYOb/034aD4Vnot61jqbaM7C1kfsLaKcMC1Ddb p2cnzvGnL+kbuA8xY16mVkRiq0N2sgN6QKO0onDJ1MyML07QrRC9jnawCfTbuKumRueHbcMVhyI GWJZDZKg5UxNsU0JGivJHptj7piXEFiViWiAftC8soFzFB7iDNqkh/5u8w9aEs4V6mhzJNNij99 nNcXmwtG0rYHzjKJdye8qgrxHEV57aypIC35s+pgFi6M0g== X-Google-Smtp-Source: AGHT+IHM6UE0Sdy5iJb7kr/1XKQMxNFWhtrYASUGG9yY/wUN/Pk1itW9CuXbu/pvDa8RKrYve4H4qA== X-Received: by 2002:a05:620a:439e:b0:7c0:6045:b8ad with SMTP id af79cd13be357-7c08a9c890amr1131653485a.15.1739780296016; Mon, 17 Feb 2025 00:18:16 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e65d9f38absm49673346d6.88.2025.02.17.00.18.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2025 00:18:15 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 5/8] target/riscv/kvm: rewrite kvm_riscv_handle_csr Date: Mon, 17 Feb 2025 16:17:25 +0800 Message-Id: <20250217081730.9000-6-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250217081730.9000-1-yongxuan.wang@sifive.com> References: <20250217081730.9000-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::72f; envelope-from=yongxuan.wang@sifive.com; helo=mail-qk1-x72f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Rewrite the kvm_riscv_handle_csr() to support additional CSR emulation in user space with KVM acceleration. This update reuses the TCG CSR emulation function to simplify the implementation and reduce the redundant work. Also it introduces two hook functions for certain CSRs. Before emulation, the related VS mode context of the CSR can be loaded from host in context_load() hook. After the CSR handling, the modified VS context is written back in context_put() hook. Signed-off-by: Yong-Xuan Wang --- target/riscv/cpu.h | 2 -- target/riscv/csr.c | 18 +++------- target/riscv/kvm/kvm-cpu.c | 68 ++++++++++++++++++++++++++++++++------ 3 files changed, 61 insertions(+), 27 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 133d1852ee1e..e30c4aa0e778 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -926,8 +926,6 @@ static inline const char *riscv_get_csr_name(int csr_no) } void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask); uint8_t satp_mode_max_from_map(uint32_t map); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a62c50f057f4..df724575a5a0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5241,8 +5241,10 @@ static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) #endif /* Crypto Extension */ -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask) +static RISCVException rmw_seed(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask) { uint16_t random_v; Error *random_e = NULL; @@ -5266,18 +5268,6 @@ target_ulong riscv_new_csr_seed(target_ulong new_value, rval = random_v | SEED_OPST_ES16; } - return rval; -} - -static RISCVException rmw_seed(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, - target_ulong write_mask) -{ - target_ulong rval; - - rval = riscv_new_csr_seed(new_value, write_mask); - if (ret_value) { *ret_value = rval; } diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 79e80cdf7406..bcd28a355a66 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1623,26 +1623,72 @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) return ret; } +/* User-space CSR emulation */ +struct kvm_riscv_emu_csr_data { + target_ulong csr_num; + int (*context_load)(CPUState *cs); + int (*context_put)(CPUState *cs); +}; + +struct kvm_riscv_emu_csr_data kvm_riscv_emu_csr_data[] = { + { CSR_SEED, NULL, NULL }, +}; + static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) { + CPURISCVState *env = cpu_env(cs); target_ulong csr_num = run->riscv_csr.csr_num; target_ulong new_value = run->riscv_csr.new_value; target_ulong write_mask = run->riscv_csr.write_mask; - int ret = 0; + struct kvm_riscv_emu_csr_data *emu_csr_data = NULL; + target_ulong ret_value; + RISCVException ret_excp; + int i, ret; - switch (csr_num) { - case CSR_SEED: - run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); - break; - default: + for (i = 0; i < ARRAY_SIZE(kvm_riscv_emu_csr_data); i++) { + if (csr_num == kvm_riscv_emu_csr_data[i].csr_num) { + emu_csr_data = &kvm_riscv_emu_csr_data[i]; + + break; + } + } + + if (!emu_csr_data) { qemu_log_mask(LOG_UNIMP, - "%s: un-handled CSR EXIT for CSR %lx\n", - __func__, csr_num); - ret = -1; - break; + "%s: un-handled CSR EXIT for CSR %s\n", + __func__, riscv_get_csr_name(csr_num)); + + return -1; } - return ret; + if (emu_csr_data->context_load) { + ret = emu_csr_data->context_load(cs); + if (ret) { + goto handle_failed; + } + } + + ret_excp = riscv_csrrw(env, csr_num, &ret_value, new_value, write_mask); + if (ret_excp != RISCV_EXCP_NONE) { + goto handle_failed; + } + run->riscv_csr.ret_value = ret_value; + + if (emu_csr_data->context_put) { + ret = emu_csr_data->context_put(cs); + if (ret) { + goto handle_failed; + } + } + + return 0; + +handle_failed: + qemu_log_mask(LOG_UNIMP, + "%s: failed to handle CSR EXIT for CSR %s\n", + __func__, riscv_get_csr_name(csr_num)); + + return -1; } static bool kvm_riscv_handle_debug(CPUState *cs) From patchwork Mon Feb 17 08:17:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13977288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E82DC021A7 for ; Mon, 17 Feb 2025 08:20:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tjwKg-0002ME-Ny; Mon, 17 Feb 2025 03:18:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tjwKf-0002KT-D7 for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:25 -0500 Received: from mail-qv1-xf2e.google.com ([2607:f8b0:4864:20::f2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tjwKd-00012c-IR for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:25 -0500 Received: by mail-qv1-xf2e.google.com with SMTP id 6a1803df08f44-6e66a7e2754so17547996d6.3 for ; Mon, 17 Feb 2025 00:18:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1739780302; x=1740385102; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=EDqmSZADlm9MRwQGQNXH9b0njTbR5RxIBA++PzJx4XE=; b=SCegvbxGPn+z4yp/S05TQxZWu262f6lIa0RmVpbuP6+S3RntDR7fN6ccmeBVALzWQ5 TAGdP3ltlP9r6ZlczPtVdXAuyAtNLOmBnmiC6djpBKfEENFshELVU8JpJaJdzkY488DO f2O30+iNaeSZw8btc0qVQ5jeySVKrQPTUQo8egyv1yEnvOkNxoyTicFxzwbYjEu/qPZS BWa100B9Ok1jxSQFJP57eE2eUL6eQMnMPc7FHyLMj3vc/+kpVFs7466AhZSWrnxnEse7 GzezpLnmYK5u3Hz+ZTshNXO3h+AD+/D+oD3jRiG3rnjK45zwMl/5jo3FrebWtCiExIvi ghtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739780302; x=1740385102; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=EDqmSZADlm9MRwQGQNXH9b0njTbR5RxIBA++PzJx4XE=; b=ZwBOmeiIC9FiBVHVzX5V/prk2XpKdYAPiXIp/sCPoSB3I+RIpY9qjpdgFo2jvVoXP3 cCTkfnMtoUt0tHGoxEcltzfVJ1DUuPjCGJ6IHsc2JimbyXc3lashSMUUETr7DeOZqlTb 0gZSCsrBchT9hCEbbTu8brz+iKBqQ8RSFO7lBT5Y/VzdG611xJtNjILzIJAtuYGiyY07 GQvCSXnUcAfMremTj+J3cQqY9yYrv+SH5qiropXJln1elxWht8mAInAcIG8wWvdRUouW /dygEB/IqFuMK1mlWgV4VsN6mA4UI9Q3ZPM2d8FSLVedLkNEfqTILt5KdC2FYnNQ3NMx QchQ== X-Gm-Message-State: AOJu0Yz8+o1EL64ffLNtyL5/znvNO+arNoROvyfXCX2PG4Ulu6spJm/N Kh+JqUOaIxDIhs+7Z4chG5hsxQ3w/e8JJWB1SF1XnjE/ZYRq0KBPXQ0n+/RHCk03uhsfoWteJPk IIxAbYuI2R8GnFst0vA72yi7+HxJ2WvXAxkN9zMkKhzqVtcXZpEWBlFUbBMoNJHw+AvvjNTB1/z DDX0cA7pL5eiUTNiCjZ+9ekmXhoHxpWpByq+Ave1Bylg== X-Gm-Gg: ASbGncuUJGaztSZ4af54O7PEGDO9Hk/FJLdgqjZ5MFjYA5OkKu1483hpoNuYx1AwVl2 Y42I7gZrJLLLLOFt8mQAH9AjLj+zyHy9m8Pb5jAamEvO8zTLmIdluYBq5Fw2OfTtfD0M0Cqo3RD ScQJcz8bqi4aEkKwHQTGg4HWmF4a/SwYXoStSv4WvIOm1CYt8D9CR5GJyZclI7LgFrQy92HJdJi NHwKW2PxtYldkkfmH2BqRqGCJj/o7UyaTGHquLaw3xNdf1nPguuxqVPl/GAttTrE+3x/W5iRD6R tBFbIik0QKbUM4JSjKpYl25VIsnUG6VK+3Tf5o2zW9Uz6Q== X-Google-Smtp-Source: AGHT+IG71vS1Fax0pu9PH1lFY5laXyQXYeBvySClwVF+W1PQ054tyXmd3Y3rWR63HFZY/n1xf9jgJQ== X-Received: by 2002:a05:6214:27c7:b0:6e1:700e:487a with SMTP id 6a1803df08f44-6e66cf3db3dmr120145506d6.40.1739780302200; Mon, 17 Feb 2025 00:18:22 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e65d9f38absm49673346d6.88.2025.02.17.00.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2025 00:18:21 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 6/8] target/riscv/kvm: add CSR_SIREG and CSR_STOPEI emulation Date: Mon, 17 Feb 2025 16:17:26 +0800 Message-Id: <20250217081730.9000-7-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250217081730.9000-1-yongxuan.wang@sifive.com> References: <20250217081730.9000-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=yongxuan.wang@sifive.com; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Support user-space emulation of SIREG and STOPEI CSR with KVM acceleration. For SIREG emulation, the SISELECT CSR value and iprio array must be loaded before handling, and since the iprio array might be modified, it must be written back after the emulation. When running with KVM acceleration, the machine lacks M-mode CSRs and does not report S-mode support in its environment configuration, even though some S-mode CSRs are accessible. This patch adds kvm_enabled() checks in relevant predicates to ensure proper handling and validation. Signed-off-by: Yong-Xuan Wang --- target/riscv/csr.c | 12 +++++++++--- target/riscv/kvm/kvm-cpu.c | 27 +++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index df724575a5a0..95841ce65730 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -27,6 +27,7 @@ #include "exec/exec-all.h" #include "exec/tb-flush.h" #include "system/cpu-timers.h" +#include "system/kvm.h" #include "qemu/guest-random.h" #include "qapi/error.h" #include @@ -42,6 +43,11 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; } +static bool riscv_has_ext_s(CPURISCVState *env) +{ + return riscv_has_ext(env, RVS) || kvm_enabled(); +} + /* Predicates */ #if !defined(CONFIG_USER_ONLY) RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) @@ -52,7 +58,7 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) return RISCV_EXCP_NONE; } - if (!(env->mstateen[index] & bit)) { + if (!kvm_enabled() && !(env->mstateen[index] & bit)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -66,7 +72,7 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) } } - if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { + if (env->priv == PRV_U && riscv_has_ext_s(env)) { if (!(env->sstateen[index] & bit)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -326,7 +332,7 @@ static RISCVException csrind_or_aia_any(CPURISCVState *env, int csrno) static RISCVException smode(CPURISCVState *env, int csrno) { - if (riscv_has_ext(env, RVS)) { + if (riscv_has_ext_s(env)) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index bcd28a355a66..c047d5f36951 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1624,6 +1624,31 @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) } /* User-space CSR emulation */ +static int kvm_riscv_emu_sireg_ctx_load(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(siselect), env->siselect); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1), env->siprio[0]); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1h), env->siprio[8]); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2), env->siprio[16]); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2h), env->siprio[24]); + + return 0; +} + +static int kvm_riscv_emu_sireg_ctx_put(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1), env->siprio[0]); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1h), env->siprio[8]); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2), env->siprio[16]); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2h), env->siprio[24]); + + return 0; +} + struct kvm_riscv_emu_csr_data { target_ulong csr_num; int (*context_load)(CPUState *cs); @@ -1632,6 +1657,8 @@ struct kvm_riscv_emu_csr_data { struct kvm_riscv_emu_csr_data kvm_riscv_emu_csr_data[] = { { CSR_SEED, NULL, NULL }, + { CSR_SIREG, kvm_riscv_emu_sireg_ctx_load, kvm_riscv_emu_sireg_ctx_put }, + { CSR_STOPEI, NULL, NULL }, }; static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) From patchwork Mon Feb 17 08:17:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13977289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19C05C021A4 for ; Mon, 17 Feb 2025 08:20:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tjwKv-0002Qh-CS; Mon, 17 Feb 2025 03:18:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tjwKt-0002Px-HE for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:39 -0500 Received: from mail-qv1-xf30.google.com ([2607:f8b0:4864:20::f30]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tjwKr-00013K-Be for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:38 -0500 Received: by mail-qv1-xf30.google.com with SMTP id 6a1803df08f44-6e6698667c7so32311796d6.2 for ; Mon, 17 Feb 2025 00:18:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1739780316; x=1740385116; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=kpVywB6YQYdl9MWDctfNmlq9T5N7Yd18fL8TXZluVxo=; b=PE4mo33xXJ7N2TVSD6yN2g53Y08yY9UcjXLiYS0egQHO59u2Eb3HUL/H13YrS/hD+6 mbfS+TE4Lr+HSSl59yHSQfb5cUMY7bXWgDCu/eKnBN9yubVCmQ1llJ29RqztYDypHaIM H6uLBb6pvfHgYzgR+sDnjgp+m1wOxGeELVSwhsApyOo2TYUbk1g7/ju0fGWCffdtZls0 NpvutYZ2B76jkZmFl8kXKbrt5IhiBrfHyeZ0bB9fDglQ9Ia93DhdONxMGUqSFsSx1MOb hMZttVD3rghvzXKBN9AM+p3b7NQo/2q+q0oWpTVErE/fYvZea92lexCA3AwISB8CAa4Q 19CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739780316; x=1740385116; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=kpVywB6YQYdl9MWDctfNmlq9T5N7Yd18fL8TXZluVxo=; b=b1WxFmubxlDRcqLf0gMnN1sLAyJYo/HrJcmQNWjKn8HhxHk6SoflcCMszW+aPrqaOb +/JTzJxKpyoeoip3+yZzz0ngXKKTiIXd9X+6VjHub0m/07GSH8V6mOfurg3YeItHhyu8 XznQwGeXpd+Boxp/9ldaoiswAz8X60E/x4LyoZcf9lzTAn7cfB+mLN9Wc9ke/Kf5YD74 VpZoq1VcUkpEFIMhGnAGJ3/icrTYLgSnf/axAUeuxwAASDUl3BA8LVo9nsDhOFzflO4s auIb/Zo3I1m/EstGJaNltKC6CK+MQeUUavyeOIi0Bythk/IzgGjAhUn90dZBdt2Vs5rX BORQ== X-Gm-Message-State: AOJu0YwnaOlakgVTWrPRDTcr+RTXQS9PFOo3C5fuSsI2EWrgTIMdKZxx QqdDIDvN/pyA5sgVy1QsYSPA2cMeQiBg5R4rtvvcegwzQ7Nd/0+rsLGPb+XTOn+GS0boXJ1CCqQ Yy+b9CjaONQdaX0Xpd76mY1grKK7U0sYXL7RMiUBin192f0SCHuGutbU6ksJgFPokOALvllU8tq ImGrGStt8Ty4zS1QQBnuNRw0yh6zi1f2HYnwlR1SgnrQ== X-Gm-Gg: ASbGncvBkpry6kAq5gaytwIjIhYbCE9GHLx5o4b+RgR7lsd1pupTVzOL0+0x5aSuOSJ PhgpnljVplpjguLG356HVLsI+EGUsIohJWadLWvr1+OchFanM00N/GPaThxnUiuOHWk3Ukhn/Sh ttXuMW+96+fw097i8nt2nKTMd19mQ+SHcw10QMcnR2BUwpnpcaJEInMrEmg2z4GpCibXMTyCnIC fF8Q1iJZl+1//ZZwawAuRH98BmjKUzVYbuTF4wdTU8hqtZK5HBA9nDEZ1BddtzIZIme8Rb2O286 +S2vgVOTnkA/Fo0s28fKdSioOv2KPwHg3npIUm8KkTg3Gw== X-Google-Smtp-Source: AGHT+IFwP0HYUZtij50ZgVk3V1h2EfvdsdEmU5/7kKLRWMRNrbd7uNHzkWsVpDWX1A5yaQYdwkCyTg== X-Received: by 2002:a05:6214:21cb:b0:6e4:6ff6:bac2 with SMTP id 6a1803df08f44-6e66ce2c480mr108033076d6.40.1739780316142; Mon, 17 Feb 2025 00:18:36 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e65d9f38absm49673346d6.88.2025.02.17.00.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2025 00:18:35 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 7/8] target/riscv/kvm: rename riscv-aia to riscv-imsic Date: Mon, 17 Feb 2025 16:17:27 +0800 Message-Id: <20250217081730.9000-8-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250217081730.9000-1-yongxuan.wang@sifive.com> References: <20250217081730.9000-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::f30; envelope-from=yongxuan.wang@sifive.com; helo=mail-qv1-xf30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The riscv-aia property only controls the in-kernel IMSIC mode, the emulation of AIA MSI mode is controlled by the kernel-irqchip property. Rename the riscv-aia property to riscv-imsic to prevent the confusion. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 52 ++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index c047d5f36951..ab53b76ab81f 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1798,9 +1798,9 @@ void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) } } -static int aia_mode; +static int imsic_mode; -static const char *kvm_aia_mode_str(uint64_t mode) +static const char *kvm_imsic_mode_str(uint64_t mode) { switch (mode) { case KVM_DEV_RISCV_AIA_MODE_EMUL: @@ -1813,19 +1813,19 @@ static const char *kvm_aia_mode_str(uint64_t mode) }; } -static char *riscv_get_kvm_aia(Object *obj, Error **errp) +static char *riscv_get_kvm_imsic(Object *obj, Error **errp) { - return g_strdup(kvm_aia_mode_str(aia_mode)); + return g_strdup(kvm_imsic_mode_str(imsic_mode)); } -static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) +static void riscv_set_kvm_imsic(Object *obj, const char *val, Error **errp) { if (!strcmp(val, "emul")) { - aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; + imsic_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; } else if (!strcmp(val, "hwaccel")) { - aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; + imsic_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; } else if (!strcmp(val, "auto")) { - aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; + imsic_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; } else { error_setg(errp, "Invalid KVM AIA mode"); error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); @@ -1834,13 +1834,15 @@ static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) void kvm_arch_accel_class_init(ObjectClass *oc) { - object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, - riscv_set_kvm_aia); - object_class_property_set_description(oc, "riscv-aia", - "Set KVM AIA mode. Valid values are 'emul', 'hwaccel' and 'auto'. " - "Changing KVM AIA modes relies on host support. Defaults to 'auto' " - "if the host supports it"); - object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), + object_class_property_add_str(oc, "riscv-imsic", riscv_get_kvm_imsic, + riscv_set_kvm_imsic); + object_class_property_set_description(oc, "riscv-imsic", + "Set KVM IMSIC mode. Valid values are 'emul', 'hwaccel' and 'auto'. " + "Changing KVM IMSIC modes relies on host support. Defaults to 'auto' " + "if the host supports it. This property only takes effect when the " + "kernel-irqchip=on|split when using AIA MSI."); + object_property_set_default_str(object_class_property_find(oc, + "riscv-imsic"), "auto"); } @@ -1851,7 +1853,7 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, { int ret, i; int aia_fd = -1; - uint64_t default_aia_mode; + uint64_t default_imsic_mode; uint64_t socket_count = riscv_socket_count(machine); uint64_t max_hart_per_socket = 0; uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; @@ -1867,24 +1869,24 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, KVM_DEV_RISCV_AIA_CONFIG_MODE, - &default_aia_mode, false, NULL); + &default_imsic_mode, false, NULL); if (ret < 0) { - error_report("KVM AIA: failed to get current KVM AIA mode"); + error_report("KVM AIA: failed to get current KVM IMSIC mode"); exit(1); } - if (default_aia_mode != aia_mode) { + if (default_imsic_mode != imsic_mode) { ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, KVM_DEV_RISCV_AIA_CONFIG_MODE, - &aia_mode, true, NULL); + &imsic_mode, true, NULL); if (ret < 0) { - warn_report("KVM AIA: failed to set KVM AIA mode '%s', using " + warn_report("KVM AIA: failed to set KVM IMSIC mode '%s', using " "default host mode '%s'", - kvm_aia_mode_str(aia_mode), - kvm_aia_mode_str(default_aia_mode)); + kvm_imsic_mode_str(imsic_mode), + kvm_imsic_mode_str(default_imsic_mode)); - /* failed to change AIA mode, use default */ - aia_mode = default_aia_mode; + /* failed to change IMSIC mode, use default */ + imsic_mode = default_imsic_mode; } } From patchwork Mon Feb 17 08:17:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13977266 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6600AC021A4 for ; Mon, 17 Feb 2025 08:18:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tjwL6-0002d2-Fx; Mon, 17 Feb 2025 03:18:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tjwL2-0002Xc-Si for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:49 -0500 Received: from mail-qv1-xf29.google.com ([2607:f8b0:4864:20::f29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tjwKw-00014N-Gp for qemu-devel@nongnu.org; Mon, 17 Feb 2025 03:18:46 -0500 Received: by mail-qv1-xf29.google.com with SMTP id 6a1803df08f44-6dcdf23b4edso36914666d6.0 for ; Mon, 17 Feb 2025 00:18:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1739780321; x=1740385121; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=Avllbujkgt9jGISnFqk3eNbI7THZ3CoG/MVM08xKPXc=; b=HjCpZeTZu/x/rZ84zPwHL4UHRcyOpSCQGb2OkG1Qns7zmxmiMfaen4Xx7ohQhUmhyw eKqe9kgcAL2JZ5h9Aw7ixRQv0QVCgt2Wpb1C+HYLToRc43TzIFGyfZoonq7qTgo6gzmw S/xhhx+SlTFmssKrJdno85YaF43FpZOqy6giY1OlNcCghFsF0gi877ep0IYvhYFKe/n0 gaAcyE17Bayp0h/Ak9D4A6ENPgX5yumG0VQCYbNSKJf6CL218isEE80Oj8sLR+pTcrq9 brJadFPcxIEG3GyxZlB8sLnCq2N6MhZYHdG8fZOBqHiFC2c2/mIZbGKOOpVeVVdiL4Pa JK3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739780321; x=1740385121; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Avllbujkgt9jGISnFqk3eNbI7THZ3CoG/MVM08xKPXc=; b=SwoKjdzyiLu/C8WqWiE9SCPF23vs/lngtBPMu3IrdhhJnLtd3bZJ9yExxVzRjhK6rG iOOHDTVTmxqj0ZqgHy1AX7e01SzaBiUtUQd4T5NFu9s8Qu7NgXAChTNMLow4OAjhi+hC Nekp8e5PpoulkW/kxwkYrSXnatgMZ8Zj8/aYVZe+zzFzgQxvjICqQvUWAOGrFzCPJX10 iol3Lvt1/mQFwxPdgDZFLhc6o3zpZwXCaJMgKGO/vyPT39kjchJltgDcEkVeLxDXxtDP i23HUPlCxrn5jS/zEXMD/dFNILH2INkZ+9xOfGqxy0TkrZGRuxJgyOqnYqnq12ZIAvN/ kDkA== X-Gm-Message-State: AOJu0Yxnzzm8B3NlR0ZLl5ypCWDQ/p3WIAErdX6MjKiAhe9fRDbgNy0m MDIXiRdaGaqxwSRo2xqDrNUqjNq+Xzip4sv/uo2Lofbsi7gh/4y+esTlHWvGILFGtC51NYiLRlP vZk5tF9kukhf5M9CYlA3HRBrv2mevSuqQ+Fkuh5bgarcJLe/qPefKrNyNpH11UtUsvNc4uIAKh8 1WWxN7o5rURFhr+d0al9yjdNSgf6oCAcnwt5Wmydr/4Q== X-Gm-Gg: ASbGnctuO7rRW+sWgbp3dvbBN0kkU3SUoXX9RcPvtZMZUtvFlQF7TwJng90p5x36Tdu drCunlEwakA6vxHm0i5eM2CmxzSx3BqOMAuwRrN+Rb572HyUERam867Ly/DzBkEHpsPj6gmPrnn 7pj572hcs5QSfE/T0QXUPKPJJUPTHYpxQXDgobSJZdctjA8htGOgnRjLrU+Jgj7U1Y0FYUfGj33 5JXi/pO9bC4LQxttQ99yZ1honLFtXbnES5+xdFWxsRgxr9aZGxMcmKkElKN3KHtI2Gnn6BuX4OC FibANMgMRdVpRSxpjGTjFhlweTCMBKvciFNtelyF58GgSA== X-Google-Smtp-Source: AGHT+IHisylNRgoOuNrWbD/d5X+eESRzBVFM6AyDkkDeGTsOM1Q1w4iNdFMyFkzeWLLY2UBq8aORzA== X-Received: by 2002:a05:6214:1c4a:b0:6e6:6713:3ea8 with SMTP id 6a1803df08f44-6e66cccc3aemr140345816d6.23.1739780321066; Mon, 17 Feb 2025 00:18:41 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e65d9f38absm49673346d6.88.2025.02.17.00.18.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2025 00:18:40 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Alistair Francis , Daniel Henrique Barboza Subject: [PATCH 8/8] docs: update the description about RISC-V AIA Date: Mon, 17 Feb 2025 16:17:28 +0800 Message-Id: <20250217081730.9000-9-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250217081730.9000-1-yongxuan.wang@sifive.com> References: <20250217081730.9000-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::f29; envelope-from=yongxuan.wang@sifive.com; helo=mail-qv1-xf29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add the description about "-accel kvm,kernel-irqchip=off" into docs/specs/riscv-aia.rst and docs/system/riscv/virt.rst. Signed-off-by: Yong-Xuan Wang --- docs/specs/riscv-aia.rst | 24 ++++++++++++++++++------ docs/system/riscv/virt.rst | 10 ++++++---- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/docs/specs/riscv-aia.rst b/docs/specs/riscv-aia.rst index 8097e2f89744..38797cca4998 100644 --- a/docs/specs/riscv-aia.rst +++ b/docs/specs/riscv-aia.rst @@ -25,11 +25,16 @@ When running KVM: - no m-mode is provided, so there is no m-mode APLIC or IMSIC emulation regardless of the AIA mode chosen - with "aia=aplic", s-mode APLIC will be emulated by userspace -- with "aia=aplic-imsic" there are two possibilities. If no additional KVM option - is provided there will be no APLIC or IMSIC emulation in userspace, and the virtual - machine will use the provided in-kernel APLIC and IMSIC controllers. If the user - chooses to use the irqchip in split mode via "-accel kvm,kernel-irqchip=split", - s-mode APLIC will be emulated while using the s-mode IMSIC from the irqchip +- with "aia=aplic-imsic" there are three possibilities. + - If no additional KVM option is provided there will be no APLIC or IMSIC emulation + in userspace, and the virtual machine will use the provided in-kernel APLIC and + IMSIC controllers. + - If the user chooses to use the irqchip in split mode via + "-accel kvm,kernel-irqchip=split", s-mode APLIC will be emulated while using + the s-mode IMSIC from the irqchip. + - If the user disables the in-kernel irqchip via "-accel kvm,kernel-irqchip=off", + both s-mode APLIC and IMSIC controller will be emulated. + The following table summarizes how the AIA and accelerator options defines what we will emulate in userspace: @@ -75,9 +80,16 @@ we will emulate in userspace: - in-kernel - in-kernel * - kvm - - irqchip=split + - kernel-irqchip=split - aplic-imsic - n/a - n/a - emul - in-kernel + * - kvm + - kernel-irqchip=off + - aplic-imsic + - n/a + - n/a + - emul + - emul diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 60850970ce83..96d7ee1ebc64 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -129,12 +129,14 @@ The following machine-specific options are supported: MSIs. When not specified, this option is assumed to be "none" which selects SiFive PLIC to handle wired interrupts. - This option also interacts with '-accel kvm'. When using "aia=aplic-imsic" - with KVM, it is possible to set the use of the kernel irqchip in split mode + This option also interacts with '-accel kvm', when using "aia=aplic-imsic" + with KVM. It is possible to set the use of the kernel irqchip in split mode by using "-accel kvm,kernel-irqchip=split". In this case the ``virt`` machine will emulate the APLIC controller instead of using the APLIC controller from - the irqchip. See :ref:`riscv-aia` for more details on all available AIA - modes. + the in-kernel irqchip. Or the kernel irqchip can be disabled by using + "-accel kvm,kernel-irqchip=off". In this case the ``virt`` machine will + emulate the APLIC and IMSIC controller in user-space instead of using in-kernel + irqchip. See :ref:`riscv-aia` for more details on all available AIA modes. - aia-guests=nnn