From patchwork Mon Feb 17 12:57:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yixun Lan X-Patchwork-Id: 13977749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0308CC021AA for ; Mon, 17 Feb 2025 12:58:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:In-Reply-To:References:Message-Id: MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JpBd/kkDEX15ubb3c+0ZeUgXQK5Nlgbp7uQBZ1USdFI=; b=4mJSoeX5z6jpdD M2wY95d1QVjGCbvNmF92/uzpaYDIlnt/C7fJflSKg0/RIQvFAx9/WTECHKAAh553vDtE0k4mOWLA/ S6/pqbVBzMDuKr+rkGJwAsB2InH5/pAkD8L4bZYh/mLSdQazfOgVRsiSNmFWMutUgjkEhZ11ZqWCt /1ie+gD3ZwvxluSQ3jsJB5lm8+5448BQlFJEUaZBIwi7BmW/l3khiZmmMb2+ulUFN0x//XAUdTkCs +YZpg0LBCdcHVFmLtdKJawFxSrO3WKp33iPqh7ofhp3/xH5Ykrfa4TqBkT8ZliQF6ZVuJc6ZHspte qtd9g8msPjFDpzaLybGA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tk0hl-00000004Xwo-1GJu; Mon, 17 Feb 2025 12:58:33 +0000 Received: from woodpecker.gentoo.org ([2001:470:ea4a:1:5054:ff:fec7:86e4] helo=smtp.gentoo.org) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tk0hj-00000004Xvv-1LnY for linux-riscv@lists.infradead.org; Mon, 17 Feb 2025 12:58:32 +0000 Received: from [127.0.0.1] (unknown [180.172.76.141]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dlan) by smtp.gentoo.org (Postfix) with ESMTPSA id 02793343083; Mon, 17 Feb 2025 12:58:24 +0000 (UTC) From: Yixun Lan Date: Mon, 17 Feb 2025 20:57:44 +0800 Subject: [PATCH v5 1/5] gpio: of: support to add custom add pin range function MIME-Version: 1.0 Message-Id: <20250217-03-k1-gpio-v5-1-2863ec3e7b67@gentoo.org> References: <20250217-03-k1-gpio-v5-0-2863ec3e7b67@gentoo.org> In-Reply-To: <20250217-03-k1-gpio-v5-0-2863ec3e7b67@gentoo.org> To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Conor Dooley , Paul Walmsley , Palmer Dabbelt X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1478; i=dlan@gentoo.org; h=from:subject:message-id; bh=SnBbFKKogB6q+Vfb+jj9D2g8pT9iPHj1lIkWDDf73vU=; b=owEBzQIy/ZANAwAKATGq6kdZTbvtAcsmYgBnszJZrRNIp7anNjnH/aex/U9yqm+zBBqIhG0UO 70eO8vlSJSJApMEAAEKAH0WIQS1urjJwxtxFWcCI9wxqupHWU277QUCZ7MyWV8UgAAAAAAuAChp c3N1ZXItZnByQG5vdGF0aW9ucy5vcGVucGdwLmZpZnRoaG9yc2VtYW4ubmV0QjVCQUI4QzlDMzF CNzExNTY3MDIyM0RDMzFBQUVBNDc1OTREQkJFRAAKCRAxqupHWU277T1qEACUaWQ2Yh3Eyo4GHf M926L5dBdaPRFOEH9/qyF0vb3PKCzwYT6CN87Ko/nLpf7KP3PI3CZFY/dvo1+vB47iw2rC5h0Cj T1HgI2dmu+mk/uXZsH5Ky5kFO90ehQOxSYCvaTdcRyThI3oejMO4KhaCab5U+CSgDRl6dCeoAa9 Frd11USieyet8rAz+8J8GZK7XhLI99sdi36o6zd+MzGWjmJGc9lCQli/jY6wK6nyD3zn6uSPXl+ 70WdKwjJeba/ANsA+pd/o/hgwUTtOQWutHmdgkdAb5BYQAffhBmxehQ+ClFwquCTtIOKESAdjKg iPQcEr83zWj88bNbX1oN/5OP1WmEsg4EJ0Vk7uObqczrK/ekzXRbp3PmOZrvM1k5Z5OoxMz4Fky 8Aaj/6cxEqKd2bhkpLFJGeF8uzLZjG+bx1p4e3wg1In5AmucGd9n0SgVRoLlZ74QWi/1OMSHiFT UpqEgKY8e19f05DaaaMMgdSUs4Mjuv250ES1sfpCvyZQAyycUqmLzswGDbW+ZRsEO7rklpX6Gfk cQPsaWoo226evDaNjfmSK47cJjHTvO0sTOpj9j/2AK1mHq/PR/M9mSfSG30hrwpkI/iIPh/80ge 3XHB3YW1VLLfzlbESpUv4tUKSdm/b2GzPEQzy0k0xD/NvZibsUkBVmDSghcCDFtMMWWQ== X-Developer-Key: i=dlan@gentoo.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250217_045831_393002_5DDCDCEA X-CRM114-Status: GOOD ( 11.69 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Meng Zhang , Yixun Lan , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Jesse Taube , Yangyu Chen , Inochi Amaoto , Jisheng Zhang , linux-riscv@lists.infradead.org, spacemit@lists.linux.dev Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Export custom function to add gpio pin range from pinctrl subsystem. This would make it possible to add pins to multi gpio chips. Signed-off-by: Yixun Lan --- drivers/gpio/gpiolib-of.c | 5 ++++- include/linux/gpio/driver.h | 7 +++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index 2e537ee979f3e2b6e8d5f86f3e121a66f2a8e083..64c8a153b823d65faebed9c4cd87952359b42765 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -1170,7 +1170,10 @@ int of_gpiochip_add(struct gpio_chip *chip) if (chip->of_gpio_n_cells > MAX_PHANDLE_ARGS) return -EINVAL; - ret = of_gpiochip_add_pin_range(chip); + if (!chip->of_add_pin_range) + chip->of_add_pin_range = of_gpiochip_add_pin_range; + + ret = chip->of_add_pin_range(chip); if (ret) return ret; diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 2dd7cb9cc270a68ddedbcdd5d44e0d0f88dfa785..a7b966c78a2f62075fb7804f6e96028564dda161 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -528,6 +528,13 @@ struct gpio_chip { */ int (*of_xlate)(struct gpio_chip *gc, const struct of_phandle_args *gpiospec, u32 *flags); + + /** + * @of_add_pin_range: + * + * Callback to add pin ranges from pinctrl + */ + int (*of_add_pin_range)(struct gpio_chip *chip); #endif /* CONFIG_OF_GPIO */ }; From patchwork Mon Feb 17 12:57:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yixun Lan X-Patchwork-Id: 13977750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15A0EC021AA for ; Mon, 17 Feb 2025 12:58:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:In-Reply-To:References:Message-Id: MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 17 Feb 2025 12:58:31 +0000 (UTC) From: Yixun Lan Date: Mon, 17 Feb 2025 20:57:45 +0800 Subject: [PATCH v5 2/5] dt-bindings: gpio: spacemit: add support for K1 SoC MIME-Version: 1.0 Message-Id: <20250217-03-k1-gpio-v5-2-2863ec3e7b67@gentoo.org> References: <20250217-03-k1-gpio-v5-0-2863ec3e7b67@gentoo.org> In-Reply-To: <20250217-03-k1-gpio-v5-0-2863ec3e7b67@gentoo.org> To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Conor Dooley , Paul Walmsley , Palmer Dabbelt X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2910; i=dlan@gentoo.org; h=from:subject:message-id; bh=J4LzejSQ5iFcYvYi6JNYyYrOhmebJg2E7is5cCBuyAo=; b=owEBzQIy/ZANAwAKATGq6kdZTbvtAcsmYgBnszJd8XdZlWM84TE7E4yfh3s3Y2ffGC9HCA9Rr W1ZkVUj3MqJApMEAAEKAH0WIQS1urjJwxtxFWcCI9wxqupHWU277QUCZ7MyXV8UgAAAAAAuAChp c3N1ZXItZnByQG5vdGF0aW9ucy5vcGVucGdwLmZpZnRoaG9yc2VtYW4ubmV0QjVCQUI4QzlDMzF CNzExNTY3MDIyM0RDMzFBQUVBNDc1OTREQkJFRAAKCRAxqupHWU277XkJD/9g1AnlmJcqBqTJUS FxmoX5jHQBALyWdYSfLNNcT1+UYG6v9ZOMGr93Kc2LHeaB7NDY6U1xxElCeUOE6gE3f1GfHJfHL XObxPeC4BUcIIgsBNi01juk5S4zZJYhureO96EV7Gn9C9ZJ6/UyXM3nCaEsZUY8zOdPqFCXqwlC Agz1Jqz+VvA0ICceCJh/DXdCZfupwsqP/VPB8a4Br6oQp0RO1ggbiVKVqHePviAoU+RFzYZ2/HG Qk+L//zr9cL7Uyp3lOuL/J8o10330fGpbUnDpYlYHZYMLnJ+IC5XizhJCmQ+eJUT0001n2PjKT0 9FiDgEqFMGslaHBz2L+1vs3Ajd+tP0w8NdwQc0m8aHhYGOx7eu/ITDjp3iOTKwSQBrlzvJo6f/S OA7FR/BvPqLeAUdRwUIWtyWppUb9CmZ6B/jhd8/5O35IdT/6GrImCQHnAqjkzw9Ip/mKezgR3A0 0UdlIk9/fmIuhoxXKeih8JSb4sARKhWK/PX3s8crwfI5N8DH3e0ligncwhQ7Ji4RWUyCEG+VnoA 7oLK3s7zBt3FZRgt1YxjzXqfd02jju4UO+lVZ499yshRuFW6xDxJfF3MOUQmvnSwvIcCVRMLikd kz3p4tiNuZVlp9xY+qsQIqyCScaDTGVKEjaSm/PfWZkwu+qgizJqVAyXRHafHPktpS7w== X-Developer-Key: i=dlan@gentoo.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250217_045838_027256_2A8D75B0 X-CRM114-Status: GOOD ( 12.47 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Meng Zhang , Yixun Lan , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Jesse Taube , Yangyu Chen , Inochi Amaoto , Jisheng Zhang , linux-riscv@lists.infradead.org, spacemit@lists.linux.dev Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The GPIO controller of K1 support basic functions as input/output, all pins can be used as interrupt which route to one IRQ line, trigger type can be select between rising edge, failing edge, or both. There are four GPIO banks, each consisting of 32 pins. Signed-off-by: Yixun Lan --- .../devicetree/bindings/gpio/spacemit,k1-gpio.yaml | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml new file mode 100644 index 0000000000000000000000000000000000000000..72a3ed2882782e5d22cf7d7a499c9084aefd961a --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/spacemit,k1-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 GPIO controller + +maintainers: + - Yixun Lan + +description: + The controller's registers are organized as sets of eight 32-bit + registers with each set of port controlling 32 pins. A single + interrupt line is shared for all of the pins by the controller. + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + const: spacemit,k1-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 3 + description: + The first two cells are the GPIO bank index and offset inside the bank, + the third cell should specify GPIO flag. + + gpio-ranges: true + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 3 + description: + The first two cells are the GPIO bank index and offset inside the bank, + the third cell should specify interrupt flag. The controller does not + support level interrupts, so flags of IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW + should not be used. Refer for valid flags. + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + - gpio-ranges + +additionalProperties: false + +dependencies: + interrupt-controller: [ interrupts ] + +examples: + - | + gpio: gpio@d4019000 { + compatible = "spacemit,k1-gpio"; + reg = <0xd4019000 0x800>; + gpio-controller; + #gpio-cells = <3>; + interrupts = <58>; + interrupt-controller; + interrupt-parent = <&plic>; + #interrupt-cells = <3>; + gpio-ranges = <&pinctrl 0 0 32>, + <&pinctrl 0 32 32>, + <&pinctrl 0 64 32>, + <&pinctrl 0 96 32>; + }; +... From patchwork Mon Feb 17 12:57:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yixun Lan X-Patchwork-Id: 13977751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CCE99C021AA for ; Mon, 17 Feb 2025 12:58:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:In-Reply-To:References:Message-Id: MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8a0sSV8762+Fpfq/mswbybqIpycE9I7me6Nb1lryocg=; b=HJOR05FS4tQGiK CGz8vVddMR2eLAhruEYqXmdnLrtWFxlWuarGxxelh+/CITKsDrvgV6jcQUnsE5cufA/jHgOaQunIU dAv4hDJHjqYQvm9CkxwG7lzbgqeHHlVEs/7Wmwwhmx2X8C5dMV3htfNb5Z62564VCARH0MCFbtYo7 2e+sH6bj8iHbEKH243qtJzBmXRyQkEYxPJ8GzCqR1nUjksf8kvT2PXGWWC8z9TNmMr9URQIBS/V3K aRgNNjx5LE4X1F4JCs82sZ+DvqWYf1MRixF6bk4Lk9izaDau18BhRXm2e0zTAHZ7VTL6is34QlCmy uuCL9BOWD+/a0Th6WQtA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tk0hy-00000004Y2g-2CTz; Mon, 17 Feb 2025 12:58:46 +0000 Received: from woodpecker.gentoo.org ([140.211.166.183] helo=smtp.gentoo.org) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tk0hw-00000004Y1P-1PDr for linux-riscv@lists.infradead.org; Mon, 17 Feb 2025 12:58:45 +0000 Received: from [127.0.0.1] (unknown [180.172.76.141]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dlan) by smtp.gentoo.org (Postfix) with ESMTPSA id EF959343069; Mon, 17 Feb 2025 12:58:37 +0000 (UTC) From: Yixun Lan Date: Mon, 17 Feb 2025 20:57:46 +0800 Subject: [PATCH v5 3/5] gpio: spacemit: add support for K1 SoC MIME-Version: 1.0 Message-Id: <20250217-03-k1-gpio-v5-3-2863ec3e7b67@gentoo.org> References: <20250217-03-k1-gpio-v5-0-2863ec3e7b67@gentoo.org> In-Reply-To: <20250217-03-k1-gpio-v5-0-2863ec3e7b67@gentoo.org> To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Conor Dooley , Paul Walmsley , Palmer Dabbelt X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=11875; i=dlan@gentoo.org; h=from:subject:message-id; bh=8T6UC22VB3ad82HdVuZr3S453BNjtMVkGO2b6JE3F/g=; b=owEBzQIy/ZANAwAKATGq6kdZTbvtAcsmYgBnszJgS8cCPLNR+NSkn5NXPwNblJQVGaeUf9m0g VRVNO0Bw8OJApMEAAEKAH0WIQS1urjJwxtxFWcCI9wxqupHWU277QUCZ7MyYF8UgAAAAAAuAChp c3N1ZXItZnByQG5vdGF0aW9ucy5vcGVucGdwLmZpZnRoaG9yc2VtYW4ubmV0QjVCQUI4QzlDMzF CNzExNTY3MDIyM0RDMzFBQUVBNDc1OTREQkJFRAAKCRAxqupHWU277f8hD/0U3VUrk7UsIZA983 /Do7FG3n3sDv3M78y48KlVRBr4x10xx5gJu1gYYJVferf3BRlrZWf5kOoQ6NU7m6nKSDRZf7CJD 9KtETCLnrVyzK6sqijyZPUfr5IyQquCi2nZ/nCfpBHAkkg9U38SuICCMfptWMxk9cbqWCZzXGKf VC0iqCqPTL+ZI62M37Y4ERVAZgH8cnMECO4xZodO7VcbQ9zeiy2iV/FcKHtwpnaI6l4OZQj1Brj 1abZSQaDq7H9/Uyic7Q4YER6LbdXHSyD9yTd/epyD3Flr8vFyhXYkZAKCgj5i0eMylDaqPottbi YmZS5Tfp3hcVeCwL1x5l7N2dFxg6TH7nUJjTPl0R3Os/oFVNcMthBrGY0s6eg1LhS48cl5PoHH2 cbJ8aQLmaBplo43DW/b0DoGWYbBxtB2AtJ8/KqRHdZxWHNDF/2jtcTH1fwS9bjWEnigd0y9tttb j8RSuG9cvQ33WOgnRqJxR7IN+yhROGnIx+We16iasLnGNzy4HcM9owu6DD5b2iB8QM+NKw+ClIp e3UEeQdL/J9g0IGSlfw1aQY4Wps1PDHroAgKPY4shZUziFHm20MHWh80f8AWjIqJqzIh0FXtkpY T4ofXnt0bwgNiwPEsS9xjD/kv+bY5FuBA6UKOIE3MicqV+mSFsPTPGqvEDYL/1fpovUA== X-Developer-Key: i=dlan@gentoo.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250217_045844_415665_B275D356 X-CRM114-Status: GOOD ( 23.79 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Meng Zhang , Yixun Lan , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Jesse Taube , Yangyu Chen , Inochi Amaoto , Jisheng Zhang , linux-riscv@lists.infradead.org, spacemit@lists.linux.dev Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Implement GPIO functionality which capable of setting pin as input, output. Also, each pin can be used as interrupt which support rising, failing, or both edge type trigger. Signed-off-by: Yixun Lan --- drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-spacemit-k1.c | 376 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 385 insertions(+) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index add5ad29a673c09082a913cb2404073b2034af48..eaae729eec00a3d6d2b83769aed3e2b0ca9927e5 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -655,6 +655,14 @@ config GPIO_SNPS_CREG where only several fields in register belong to GPIO lines and each GPIO line owns a field with different length and on/off value. +config GPIO_SPACEMIT_K1 + bool "SPACEMIT K1 GPIO support" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on OF_GPIO + select GPIOLIB_IRQCHIP + help + Say yes here to support the SpacemiT's K1 GPIO device. + config GPIO_SPEAR_SPICS bool "ST SPEAr13xx SPI Chip Select as GPIO support" depends on PLAT_SPEAR diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index af3ba4d81b583842893ea69e677fbe2abf31bc7b..6709ce511a0cf10310a94521c85a2d382dcfa696 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -156,6 +156,7 @@ obj-$(CONFIG_GPIO_SIOX) += gpio-siox.o obj-$(CONFIG_GPIO_SL28CPLD) += gpio-sl28cpld.o obj-$(CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER) += gpio-sloppy-logic-analyzer.o obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o +obj-$(CONFIG_GPIO_SPACEMIT_K1) += gpio-spacemit-k1.o obj-$(CONFIG_GPIO_SPEAR_SPICS) += gpio-spear-spics.o obj-$(CONFIG_GPIO_SPRD) += gpio-sprd.o obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c new file mode 100644 index 0000000000000000000000000000000000000000..f72511b5ab8f8f0b1d1c9e89d2f9ca07b623a866 --- /dev/null +++ b/drivers/gpio/gpio-spacemit-k1.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2023-2025 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (C) 2025 Yixun Lan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gpiolib.h" + +/* register offset */ +/* GPIO port level register */ +#define GPLR 0x00 +/* GPIO port direction register - R/W */ +#define GPDR 0x0c +/* GPIO port set register - W */ +#define GPSR 0x18 +/* GPIO port clear register - W */ +#define GPCR 0x24 +/* GPIO port rising edge register R/W */ +#define GRER 0x30 +/* GPIO port falling edge register R/W */ +#define GFER 0x3c +/* GPIO edge detect status register - R/W1C */ +#define GEDR 0x48 +/* GPIO (set) direction register - W */ +#define GSDR 0x54 +/* GPIO (clear) direction register - W */ +#define GCDR 0x60 +/* GPIO (set) rising edge detect enable register - W */ +#define GSRER 0x6c +/* GPIO (clear) rising edge detect enable register - W */ +#define GCRER 0x78 +/* GPIO (set) falling edge detect enable register - W */ +#define GSFER 0x84 +/* GPIO (clear) falling edge detect enable register - W */ +#define GCFER 0x90 +/* GPIO interrupt mask register, 0 disable, 1 enable - R/W */ +#define GAPMASK 0x9c + +#define NR_BANKS 4 +#define NR_GPIOS_PER_BANK 32 + +#define to_spacemit_gpio_bank(x) container_of((x), struct spacemit_gpio_bank, gc) + +struct spacemit_gpio; + +struct spacemit_gpio_bank { + struct gpio_chip gc; + struct spacemit_gpio *sg; + void __iomem *base; + u32 index; + u32 irq_mask; + u32 irq_rising_edge; + u32 irq_falling_edge; +}; + +struct spacemit_gpio { + struct device *dev; + struct spacemit_gpio_bank sgb[NR_BANKS]; +}; + +static irqreturn_t spacemit_gpio_irq_handler(int irq, void *dev_id) +{ + struct spacemit_gpio_bank *gb = dev_id; + unsigned long pending; + u32 n, gedr; + + gedr = readl(gb->base + GEDR); + if (!gedr) + return IRQ_NONE; + writel(gedr, gb->base + GEDR); + + gedr = gedr & gb->irq_mask; + if (!gedr) + return IRQ_NONE; + + pending = gedr; + for_each_set_bit(n, &pending, BITS_PER_LONG) + handle_nested_irq(irq_find_mapping(gb->gc.irq.domain, n)); + + return IRQ_HANDLED; +} + +static void spacemit_gpio_irq_ack(struct irq_data *d) +{ + struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d); + + writel(BIT(irqd_to_hwirq(d)), gb->base + GEDR); +} + +static void spacemit_gpio_irq_mask(struct irq_data *d) +{ + struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d); + u32 bit = BIT(irqd_to_hwirq(d)); + + gb->irq_mask &= ~bit; + + if (bit & gb->irq_rising_edge) + writel(bit, gb->base + GCRER); + + if (bit & gb->irq_falling_edge) + writel(bit, gb->base + GCFER); +} + +static void spacemit_gpio_irq_unmask(struct irq_data *d) +{ + struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d); + u32 bit = BIT(irqd_to_hwirq(d)); + + gb->irq_mask |= bit; + + if (bit & gb->irq_rising_edge) + writel(bit, gb->base + GSRER); + + if (bit & gb->irq_falling_edge) + writel(bit, gb->base + GSFER); +} + +static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d); + u32 bit = BIT(irqd_to_hwirq(d)); + + if (type & IRQ_TYPE_EDGE_RISING) { + gb->irq_rising_edge |= bit; + writel(bit, gb->base + GSRER); + } else { + gb->irq_rising_edge &= ~bit; + writel(bit, gb->base + GCRER); + } + + if (type & IRQ_TYPE_EDGE_FALLING) { + gb->irq_falling_edge |= bit; + writel(bit, gb->base + GSFER); + } else { + gb->irq_falling_edge &= ~bit; + writel(bit, gb->base + GCFER); + } + + return 0; +} + +static void spacemit_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) +{ + struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(data); + + seq_printf(p, "%s-%d", dev_name(gb->gc.parent), gb->index); +} + +static struct irq_chip spacemit_gpio_chip = { + .name = "k1-gpio-irqchip", + .irq_ack = spacemit_gpio_irq_ack, + .irq_mask = spacemit_gpio_irq_mask, + .irq_unmask = spacemit_gpio_irq_unmask, + .irq_set_type = spacemit_gpio_irq_set_type, + .irq_print_chip = spacemit_gpio_irq_print_chip, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int spacemit_gpio_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, u32 *flags) +{ + struct spacemit_gpio_bank *gb = gpiochip_get_data(gc); + struct spacemit_gpio *sg = gb->sg; + + int i; + + if (gc->of_gpio_n_cells != 3) + return -EINVAL; + + if (gpiospec->args_count < gc->of_gpio_n_cells) + return -EINVAL; + + i = gpiospec->args[0]; + if (i >= NR_BANKS) + return -EINVAL; + + if (gc != &sg->sgb[i].gc) + return -EINVAL; + + if (gpiospec->args[1] >= gc->ngpio) + return -EINVAL; + + if (flags) + *flags = gpiospec->args[2]; + + return gpiospec->args[1]; +} + +static int spacemit_add_pin_range(struct gpio_chip *gc) +{ + struct spacemit_gpio_bank *gb; + struct of_phandle_args pinspec; + struct pinctrl_dev *pctldev; + struct device_node *np; + int ret, trim; + + np = dev_of_node(&gc->gpiodev->dev); + if (!np) + return 0; + + gb = to_spacemit_gpio_bank(gc); + + ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, + gb->index, &pinspec); + if (ret) + return ret; + + pctldev = of_pinctrl_get(pinspec.np); + of_node_put(pinspec.np); + if (!pctldev) + return -EPROBE_DEFER; + + /* Ignore ranges outside of this GPIO chip */ + if (pinspec.args[0] >= (gc->offset + gc->ngpio)) + return -EINVAL; + + if (pinspec.args[0] + pinspec.args[2] <= gc->offset) + return -EINVAL; + + if (!pinspec.args[2]) + return -EINVAL; + + /* Trim the range to fit this GPIO chip */ + if (gc->offset > pinspec.args[0]) { + trim = gc->offset - pinspec.args[0]; + pinspec.args[2] -= trim; + pinspec.args[1] += trim; + pinspec.args[0] = 0; + } else { + pinspec.args[0] -= gc->offset; + } + if ((pinspec.args[0] + pinspec.args[2]) > gc->ngpio) + pinspec.args[2] = gc->ngpio - pinspec.args[0]; + + ret = gpiochip_add_pin_range(gc, + pinctrl_dev_get_devname(pctldev), + pinspec.args[0], + pinspec.args[1], + pinspec.args[2]); + if (ret) + return ret; + + return 0; +} + +static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + void __iomem *regs, + int index, int irq) +{ + struct spacemit_gpio_bank *gb = &sg->sgb[index]; + struct gpio_chip *gc = &gb->gc; + struct device *dev = sg->dev; + struct gpio_irq_chip *girq; + void __iomem *dat, *set, *clr, *dirin, *dirout; + int ret, bank_base[] = { 0x0, 0x4, 0x8, 0x100 }; + + gb->index = index; + gb->base = regs + bank_base[index]; + + dat = gb->base + GPLR; + set = gb->base + GPSR; + clr = gb->base + GPCR; + dirin = gb->base + GCDR; + dirout = gb->base + GSDR; + + /* This registers 32 GPIO lines per bank */ + ret = bgpio_init(gc, dev, 4, dat, set, clr, dirout, dirin, + BGPIOF_UNREADABLE_REG_SET | BGPIOF_UNREADABLE_REG_DIR); + if (ret) + return dev_err_probe(dev, ret, "failed to init gpio chip\n"); + + gb->sg = sg; + + gc->label = dev_name(dev); + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + gc->ngpio = NR_GPIOS_PER_BANK; + gc->base = -1; + +#ifdef CONFIG_OF_GPIO + gc->of_xlate = spacemit_gpio_xlate; + gc->of_add_pin_range = spacemit_add_pin_range; + gc->of_gpio_n_cells = 3; +#endif + + girq = &gc->irq; + girq->threaded = true; + girq->handler = handle_simple_irq; + + gpio_irq_chip_set_chip(girq, &spacemit_gpio_chip); + + /* Clear Edge Detection Settings */ + writel(0x0, gb->base + GRER); + writel(0x0, gb->base + GFER); + /* Clear and Disable Interrupt */ + writel(0xffffffff, gb->base + GCFER); + writel(0xffffffff, gb->base + GCRER); + writel(0, gb->base + GAPMASK); + + ret = devm_request_threaded_irq(dev, irq, NULL, + spacemit_gpio_irq_handler, + IRQF_ONESHOT | IRQF_SHARED, + gb->gc.label, gb); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to register IRQ\n"); + + ret = devm_gpiochip_add_data(dev, gc, gb); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to add gpio chip\n"); + + /* Eable Interrupt */ + writel(0xffffffff, gb->base + GAPMASK); + + return 0; +} + +static int spacemit_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct spacemit_gpio *sg; + struct resource *res; + void __iomem *regs; + int i, irq, ret; + + sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL); + if (!sg) + return -ENOMEM; + + regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + sg->dev = dev; + + for (i = 0; i < NR_BANKS; i++) { + ret = spacemit_gpio_add_bank(sg, regs, i, irq); + if (ret) + return ret; + } + + return 0; +} + +static const struct of_device_id spacemit_gpio_dt_ids[] = { + { .compatible = "spacemit,k1-gpio" }, + { /* sentinel */ } +}; + +static struct platform_driver spacemit_gpio_driver = { + .probe = spacemit_gpio_probe, + .driver = { + .name = "k1-gpio", + .of_match_table = spacemit_gpio_dt_ids, + }, +}; +module_platform_driver(spacemit_gpio_driver); + +MODULE_AUTHOR("Yixun Lan "); +MODULE_DESCRIPTION("GPIO driver for SpacemiT K1 SoC"); +MODULE_LICENSE("GPL"); From patchwork Mon Feb 17 12:57:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yixun Lan X-Patchwork-Id: 13977752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1FFE6C021A9 for ; Mon, 17 Feb 2025 12:58:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:In-Reply-To:References:Message-Id: MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 17 Feb 2025 12:58:44 +0000 (UTC) From: Yixun Lan Date: Mon, 17 Feb 2025 20:57:47 +0800 Subject: [PATCH v5 4/5] riscv: dts: spacemit: add gpio support for K1 SoC MIME-Version: 1.0 Message-Id: <20250217-03-k1-gpio-v5-4-2863ec3e7b67@gentoo.org> References: <20250217-03-k1-gpio-v5-0-2863ec3e7b67@gentoo.org> In-Reply-To: <20250217-03-k1-gpio-v5-0-2863ec3e7b67@gentoo.org> To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Conor Dooley , Paul Walmsley , Palmer Dabbelt X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1785; i=dlan@gentoo.org; h=from:subject:message-id; bh=WVBz+R9XhlQhdzku9JAMTki0K5OuMCV+ma1IEixq6JY=; b=owEBzQIy/ZANAwAKATGq6kdZTbvtAcsmYgBnszJjEkNRYJm+jpFpDKfHlEE5r9b/y639sXg/R rB574NORAWJApMEAAEKAH0WIQS1urjJwxtxFWcCI9wxqupHWU277QUCZ7MyY18UgAAAAAAuAChp c3N1ZXItZnByQG5vdGF0aW9ucy5vcGVucGdwLmZpZnRoaG9yc2VtYW4ubmV0QjVCQUI4QzlDMzF CNzExNTY3MDIyM0RDMzFBQUVBNDc1OTREQkJFRAAKCRAxqupHWU277eF5D/wL0sPxLR1LrXWnQ3 4myIo8WzuuteNyHsN7ZkVyzl74Bpe+3nFfUhPrHscL21GlIoj3g7PzUtKU60jBAI3tOrgtVETT3 D8o2SXsZuMJrUh94Cs6lirwR5QBlkGwwsGSDFr9XoGuMB6p13Kfjx9sm4NPP3BUHD39SIDWRMnG 4VxxLqKZXn4Fd54HWrl7Rddpm686YWmsnWu3/V8gtn848DSRMZokApH9GlGnMsFmYzFU/GfTSE/ a5jrfo3dxPTc2b1iYGQ8R0YB345qR0uV/m1mO3ykPwFAHG+g/VkVhIcoY6KttqK5VnXDC7dtvwr 2X0aYDHHUEUtl1D7nIMq4ALvksnVWilyRKpfsx5QHdZ9PgzOv/q+Psr951hkMhAQkpq/fTt63Pr LUj6J18JuW/d87JcBG3RBhnZmBwnEz5Y2fxVIBF7UkZnAJMfrc3iHX/yF/6IXofFI9QI5bmRau6 AsY0QMPRosDaID9/IGWpYFHCK6F1RFr2rueM+P8JINbrWo/R5ifRi1Q7BHA9eaGxAhl1wKcyJ/i yBh/pQhiCGfn9Ry4+yBhY8g9wth3zDSDXDqnM09glVHoF16kVo7PwFgUwCfueqJhB13qI9UQIoc ZshpzZwNNN4fxTDZ+vTR0e3bXjLPTqOVvksbGTXs3SQth6h/8itYMFEzpS90LRDTMdjw== X-Developer-Key: i=dlan@gentoo.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250217_045851_382355_31A606C5 X-CRM114-Status: UNSURE ( 8.12 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Meng Zhang , Yixun Lan , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Jesse Taube , Yangyu Chen , Inochi Amaoto , Jisheng Zhang , linux-riscv@lists.infradead.org, spacemit@lists.linux.dev Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Populate the GPIO node in the device tree for SpacemiT K1 SoC. Each of 32 pins will act as one bank and map pins to pinctrl controller. Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 3 +++ arch/riscv/boot/dts/spacemit/k1.dtsi | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi index a8eac5517f8578d60cb45214589ccb45ac376b9a..283663647a86ff137917ced8bfe79a129c86342a 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -7,6 +7,9 @@ #define K1_PADCONF(pin, func) (((pin) << 16) | (func)) +/* Map GPIO pin to each bank's */ +#define K1_GPIO(x) (x / 32) (x % 32) + &pinctrl { uart0_2_cfg: uart0-2-cfg { uart0-2-pins { diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index c670ebf8fa12917aa6493fcd89fdd1409529538b..d65ff76ead8cbe303412954c8abafbefecf8081e 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -404,6 +404,21 @@ uart9: serial@d4017800 { status = "disabled"; }; + gpio: gpio@d4019000 { + compatible = "spacemit,k1-gpio"; + reg = <0x0 0xd4019000 0x0 0x100>; + gpio-controller; + #gpio-cells = <3>; + interrupts = <58>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-ranges = <&pinctrl 0 0 32>, + <&pinctrl 0 32 32>, + <&pinctrl 0 64 32>, + <&pinctrl 0 96 32>; + }; + pinctrl: pinctrl@d401e000 { compatible = "spacemit,k1-pinctrl"; reg = <0x0 0xd401e000 0x0 0x400>; From patchwork Mon Feb 17 12:57:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yixun Lan X-Patchwork-Id: 13977753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C448CC021AA for ; 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Mon, 17 Feb 2025 12:59:00 +0000 Received: from woodpecker.gentoo.org ([140.211.166.183] helo=smtp.gentoo.org) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tk0iA-00000004Y8y-1BL1 for linux-riscv@lists.infradead.org; Mon, 17 Feb 2025 12:58:59 +0000 Received: from [127.0.0.1] (unknown [180.172.76.141]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dlan) by smtp.gentoo.org (Postfix) with ESMTPSA id 82E273430DE; Mon, 17 Feb 2025 12:58:51 +0000 (UTC) From: Yixun Lan Date: Mon, 17 Feb 2025 20:57:48 +0800 Subject: [PATCH v5 5/5] riscv: dts: spacemit: add gpio LED for system heartbeat MIME-Version: 1.0 Message-Id: <20250217-03-k1-gpio-v5-5-2863ec3e7b67@gentoo.org> References: <20250217-03-k1-gpio-v5-0-2863ec3e7b67@gentoo.org> In-Reply-To: <20250217-03-k1-gpio-v5-0-2863ec3e7b67@gentoo.org> To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Conor Dooley , Paul Walmsley , Palmer Dabbelt X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; 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a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250217_045858_354132_57E01C63 X-CRM114-Status: UNSURE ( 7.45 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Meng Zhang , Yixun Lan , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Jesse Taube , Yangyu Chen , Inochi Amaoto , Jisheng Zhang , linux-riscv@lists.infradead.org, spacemit@lists.linux.dev Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Leverage GPIO to support system LED to indicate activity of CPUs. Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 1d617b40a2d51ee464b57234d248798aeb218643..816ef1bc358ec490aff184d5915d680dbd9f00cb 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -17,6 +17,17 @@ aliases { chosen { stdout-path = "serial0"; }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "sys-led"; + gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; }; &uart0 {