From patchwork Tue Feb 18 14:26:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13980047 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DAFA26A0D7; Tue, 18 Feb 2025 14:27:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739888860; cv=none; b=n5GrDuALN0xVpN41MVZOzW681e40gqTgfW4sfL+xCbUsZXRjPwG8BT7luKL1GxIjG0YSqz2agL6WEqeAtCrkDWkiu8TxvmCOKYrhFU63ehkvlTk4OW7dE7Y8Mzu+ofrDqymIsOskGue+HcV3VXH1tq83y6VXDdIzOnGu7vx7FVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739888860; c=relaxed/simple; bh=kuYeVDvp8hjTH1IgHmrJLXlU+/zQ4sez4XzYxhySnak=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=GsdvebW7+TKuSJSMUnYT9f4nnfx0smqLv3AODAe13j7+f16kknowRXvsWsuyKpDKre3w7jPIiOIfd/NCCYgqWtJUJSa6wdPHvTwPoKEDNxFJT4vMeD8NjGNKjsNepXXNZyLVHWzWgo/R+d5rQjp/xk+sQr+lFTe6yCRI2OguZGg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Xncr/0tL; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Xncr/0tL" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51ICKq8h026146; Tue, 18 Feb 2025 14:27:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= A4Ugt8JGI4OW7ptZ0h9gm3LgnfhkSdadEhp94FwH8bg=; b=Xncr/0tLUz+DlwV7 vj9AZhjNaQWABt9Ac+StUG7jAhYFrJBaCwAKpulJPxF3z/XygU0uMM/z6ozLU3h8 +uRSyD8SiP50+6g5Z/UtsMx9zvZZ/Wx5An/6TlKjTmSbkyIh7EBlFkCh+kMWLzRl pyn8yHbY+icDCwzGZVq4MiqEECGLJJxJt7FxHPw818c09BrWNs2LoBaKHD5xg1vG 1zFrroKNnyLO9LWYDByxiyevhA1oICSHA2HmiYlQfrDuU2KUCkZb5fFsYt1pdswJ u4Q/8APgXz4nUR9PwA/ix47isSegv/Pw4ad5Pl+SSTHW573omaPWRWCMjZ4i/Mru Y/aBOQ== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44ut7sn54m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Feb 2025 14:27:35 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51IERIL7026418 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Feb 2025 14:27:18 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 18 Feb 2025 06:27:14 -0800 From: Jagadeesh Kona Date: Tue, 18 Feb 2025 19:56:46 +0530 Subject: [PATCH 1/5] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250218-videocc-pll-multi-pd-voting-v1-1-cfe6289ea29b@quicinc.com> References: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> In-Reply-To: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Jagadeesh Kona X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: MEEqWaH-x2NGqmWo_fbFXmNhgYZJR9b7 X-Proofpoint-ORIG-GUID: MEEqWaH-x2NGqmWo_fbFXmNhgYZJR9b7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-18_07,2025-02-18_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=832 clxscore=1015 priorityscore=1501 adultscore=0 spamscore=0 malwarescore=0 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502180109 To configure the video PLLs and enable the video GDSCs on SM8450, SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX. Therefore, update the videocc bindings to include the MXC power domain on these platforms. Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 62714fa54db82491a7a108f7f18a253d737f8d61..737efc4b46564c1e475b02873d2dc124329fb775 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -32,9 +32,11 @@ properties: - description: Video AHB clock from GCC power-domains: - maxItems: 1 description: - MMCX power domain. + Power domains required for the clock controller to operate + items: + - description: MMCX power domain + - description: MXC power domain required-opps: maxItems: 1 @@ -72,7 +74,8 @@ examples: reg = <0x0aaf0000 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; From patchwork Tue Feb 18 14:26:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13980046 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EC2526A0DA; Tue, 18 Feb 2025 14:27:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739888858; cv=none; b=p/GGzpSYOMbzGDoLMm1uaf2LmdGRtAor7p/Dqz1eIf+azz1NtZx+HOQCdOc22WzAmNY4cSChgemWOPtQRQBjs2RnwxY/TJa0C2VQahkWm/vyAsApmV3naG0ri/QmZA6F8hmEoGuP3siDhzEi+2dZaET5uUhslVw7H5o6eniqO+k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739888858; c=relaxed/simple; bh=PhB6OzwPDDrY1d9lL1JvH7rZoen6/sphN1KSoNVFKS0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=sojEZ+vYDqs18l/1VEqW3TsglYb+GMxpoYDI/NkgkS9eLU+tA+Pdl8Sq4OBlcy3Gjxhhl9WKbYoqHJWrTMi336FSeor3aI04H1ybuicjSohcOC9sBugHiA5o4+RAPhDGkp3qo7mvTKr+yrrbmLpmiU6ERo+vhaGSwtrKYJIMn/8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=EwBUuKzi; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="EwBUuKzi" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51IAmPmX020884; Tue, 18 Feb 2025 14:27:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= zvW4R9RdiZDuhArRhb8iPnmp3Z7MWWkpYGzDzEtr/YA=; b=EwBUuKzi276BXZad fPeQMpYoR+8m0xdDT9iKLS4tHSxULwGeMfPeMneotcVQMxINIaAg+4Kxo3edjJI4 FJLqCRN3OyAzW0PE4HEAsfbvHdWev3Yi0BH+UxFRCXZSExvYPhsmDeteUqiycdGj xRhfEFYG6/89lQKBzyaoZNcJH+DkmbNghw3pQflRznlchWT1IpIHIrRLfauLS/gv 43Z1chvAYKl9Iif37YPksYjsMtkSKEYwsS+u4+QsUN4QItW4btKe/zM2qnBbCBDa 8ZsGy/qCVFLNddI1UnRxqQNWREusgCqAmlk9KDtoT8RQCzCWlC0IwBUe7lU7g21R epmp5A== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44ut7sw53b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Feb 2025 14:27:33 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51IERN0O024307 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Feb 2025 14:27:23 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 18 Feb 2025 06:27:18 -0800 From: Jagadeesh Kona Date: Tue, 18 Feb 2025 19:56:47 +0530 Subject: [PATCH 2/5] clk: qcom: common: Add support to attach multiple power domains Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250218-videocc-pll-multi-pd-voting-v1-2-cfe6289ea29b@quicinc.com> References: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> In-Reply-To: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Jagadeesh Kona X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: sZOxJA6fYnQb5lBszC5ag8aH77-x2TCK X-Proofpoint-ORIG-GUID: sZOxJA6fYnQb5lBszC5ag8aH77-x2TCK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-18_07,2025-02-18_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=832 phishscore=0 spamscore=0 clxscore=1011 mlxscore=0 suspectscore=0 adultscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502180109 From: Taniya Das In the latest chipset clock controllers, multiple power domains can be required to access and configure the PLLs in probe. Therefore, add support for an API to attach to multiple power domains in the clock controller probe before configuring the PLLs. Signed-off-by: Taniya Das Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/common.c | 12 ++++++++++++ drivers/clk/qcom/common.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 9e3380fd718198c9fe63d7361615a91c3ecb3d60..ec27f70b24bdec24edd2f6b3df0d766fc1cdcbf0 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -391,5 +391,17 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index, } EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index); +int qcom_cc_attach_pds(struct device *dev, struct qcom_cc_desc *desc) +{ + int ret; + + ret = devm_pm_domain_attach_list(dev, NULL, &desc->pd_list); + if (ret < 0 && ret != -EEXIST) + return ret; + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_cc_attach_pds); + MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("QTI Common Clock module"); diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 7ace5d7f5836aa81431153ba92d8f14f2ffe8147..45f1f53fb407d4600f5059b792564b68cd8c244d 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -38,6 +38,7 @@ struct qcom_cc_desc { const struct qcom_icc_hws_data *icc_hws; size_t num_icc_hws; unsigned int icc_first_node_id; + struct dev_pm_domain_list *pd_list; }; /** @@ -76,5 +77,6 @@ extern int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc); extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index, const struct qcom_cc_desc *desc); +extern int qcom_cc_attach_pds(struct device *dev, struct qcom_cc_desc *desc); #endif From patchwork Tue Feb 18 14:26:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13980049 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35C3E26D5C9; Tue, 18 Feb 2025 14:27:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739888868; cv=none; b=PbbSBsBraB8QfjFWMRQTrlYhfg1rbew4/ZZoxD6lBPTzrHmL0301m3tJuGx6NS1ABQ650qnvoCH23iKER2K0tHn1AnY+Zweo/wSg6BrmvSEcPPZUKh8TY4+khSrCR/4IzjWq59/5/zbeRbrwNlZyyBnQP9KKCnPqRhvhR4Ucukg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739888868; c=relaxed/simple; bh=E1sLj3nSLKbyA5X3l1PNaCQPrVHOz5WY0J7BiPFStR0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=HBGAhf1UuXkfrfxqPUgJv6iFG0r+yII1btO6bWv51Ad8EL5ogNHX+M11b/zv0NR+WNTTDNLYK7fplqAVDkYSq1mSpcRLondezsU5fCyUHD4rUFLyRXs2nKa8NV5juUrFSyMkywmEnrbx3zrs7XSjLyOMp7g+QRm5h5A2S8FaXuc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=YylOXd4l; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="YylOXd4l" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51IBh34s026366; Tue, 18 Feb 2025 14:27:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Afrx0VHj98Va41ypMszwR6MhY3suuQ3MzWBXy/7D3/g=; b=YylOXd4lt0rRIBwA Oo0K9QpNBU56BlE1yO80NpDzFy1TP8AoHFQUy3ZXJ4Z74Wq1WEvutuEntW+nWeEu Ig2uvX90rYS/l7wPlr5yVYJo/af9Ar5pZj7lyUH1yGXF5UrKcpsT5ptfA4G854Z8 xQkGeTJwK+styU12L/SrLZe/oYgnr18cNJwwy+WgzsavzCB7cy00xJ41GM0OwYv9 smYilqeyaTZuW2hGKwnEcSAWy+ebeOewvDJCYx19JFhSkKC18nqfDddn2BgoUDD/ 40J1V8ZegDwL7T04viiITuW69rvNOWCx5tuWxhpkepMHnrerAJw5YAkkxmPM+fvz ZPQ9uA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44ut7vw3yx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Feb 2025 14:27:43 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51IERSOO024347 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Feb 2025 14:27:28 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 18 Feb 2025 06:27:23 -0800 From: Jagadeesh Kona Date: Tue, 18 Feb 2025 19:56:48 +0530 Subject: [PATCH 3/5] clk: qcom: common: Attach clock power domains conditionally Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250218-videocc-pll-multi-pd-voting-v1-3-cfe6289ea29b@quicinc.com> References: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> In-Reply-To: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Jagadeesh Kona X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: DycCh1apGGd1tqABucSum8qh3rxhdbis X-Proofpoint-ORIG-GUID: DycCh1apGGd1tqABucSum8qh3rxhdbis X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-18_07,2025-02-18_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 phishscore=0 spamscore=0 clxscore=1011 priorityscore=1501 impostorscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 mlxscore=0 mlxlogscore=614 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502180109 Attach clock power domains in qcom_cc_really_probe() only if the clock controller has not already attached to them. Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/common.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index ec27f70b24bdec24edd2f6b3df0d766fc1cdcbf0..eb7e2a56d1d135f839fd9bd470ba6231ce775a8c 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -300,9 +300,12 @@ int qcom_cc_really_probe(struct device *dev, if (!cc) return -ENOMEM; - ret = devm_pm_domain_attach_list(dev, NULL, &cc->pd_list); - if (ret < 0 && ret != -EEXIST) - return ret; + cc->pd_list = desc->pd_list; + if (!cc->pd_list) { + ret = devm_pm_domain_attach_list(dev, NULL, &cc->pd_list); + if (ret < 0 && ret != -EEXIST) + return ret; + } reset = &cc->reset; reset->rcdev.of_node = dev->of_node; From patchwork Tue Feb 18 14:26:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13980050 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D399226AAA4; Tue, 18 Feb 2025 14:27:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739888874; cv=none; b=Nft1HxaNKcDelIs3rbkM0UhqalVXftIPHfDv95ryV8Lr60myAVJk05JbgXlLDgagf8rsSc6QwdDTRW+E1FEhz8ajKkv9ybVczk25spPUV73B2ZSmFoNg8xWCKW3C9BgTAvxwfTd4N1474tzzrl+n2IdCg0KD6gdYT7dRH2wUX78= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739888874; c=relaxed/simple; bh=BV2VgzfcOo4EzLX7IZlkv3VsP0RMnY60MoLfDujX8BY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=IqjzpVb1giby8FRU9/naf4wpwuHuKSX6ztd5AUhI6yirzuyVRTVczVarR13s2Y5EzbZQu8A0RmECfpbESji5Axv/CFUeZOQo0XwkcOuEtaeNLSY0cKcY+YHI2gdgvVmTxB5gN/Ia1EtW0iJQumJzZIbMNB7RuBTjByLmyP2PSqo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=GdAuMFBB; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="GdAuMFBB" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51ICD348032460; Tue, 18 Feb 2025 14:27:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= J3mtRmAim5IvSoDPxMoM0Z1QEP1vYuBgxWn2KbVtPck=; b=GdAuMFBBRdtrCyCr KBM/gtumt6t4PR4r3s0by1mGiDGWGdNkxeVQawqI7nyckOyy7TURCTUcOchdZlMt Ff4KEJ/uuH7TIH/ZTiEeEpaE8n3UXXGrMCTTvhp5XUhuk6RIRW79ya4l4p5S6U1P oTzduusdbQ2H3J8liNuHYnAEpgHYuX+a6V6OvgLVk5tJ1qTDIEnviSIRJ0IAHMxP wiFMHsa9OOTfmNto5WyDT3urfqB0tQ4QAZ3I485e3I8b71J6WNp1utxLSA69FLr8 AsJ9po8nX3kNKtxgQUjHojQHVFM7H/mndtoTQNz7rn5hvN7pfv5S1kt52BhqOxex PxYh8Q== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44ut7ww3am-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Feb 2025 14:27:48 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51IERXL8026537 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Feb 2025 14:27:33 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 18 Feb 2025 06:27:28 -0800 From: Jagadeesh Kona Date: Tue, 18 Feb 2025 19:56:49 +0530 Subject: [PATCH 4/5] clk: qcom: videocc: Add support to attach multiple power domains Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250218-videocc-pll-multi-pd-voting-v1-4-cfe6289ea29b@quicinc.com> References: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> In-Reply-To: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Jagadeesh Kona X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: -3WHwkDTAykQ-gPqrCZuaTHkfrcKJBAN X-Proofpoint-ORIG-GUID: -3WHwkDTAykQ-gPqrCZuaTHkfrcKJBAN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-18_07,2025-02-18_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 bulkscore=0 mlxlogscore=896 spamscore=0 adultscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502180109 During boot-up, the PLL configuration might be missed even after calling pll_configure() from the clock controller probe. This can happen because the PLL is connected to one or more rails that are turned off, and the current clock controller code cannot enable multiple rails during probe. Consequently, the PLL may be activated with suboptimal settings, causing functional issues. To properly configure the video PLLs in the probe on SM8450, SM8475, SM8550, and SM8650 platforms, the MXC rail must be ON along with MMCX. Therefore, add support to attach multiple power domains to videocc on these platforms. Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/videocc-sm8450.c | 4 ++++ drivers/clk/qcom/videocc-sm8550.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c index f26c7eccb62e7eb8dbd022e2f01fa496eb570b3f..b50a14547336580de88a741f1d33b126e9daa848 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -437,6 +437,10 @@ static int video_cc_sm8450_probe(struct platform_device *pdev) struct regmap *regmap; int ret; + ret = qcom_cc_attach_pds(&pdev->dev, &video_cc_sm8450_desc); + if (ret) + return ret; + ret = devm_pm_runtime_enable(&pdev->dev); if (ret) return ret; diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index 7c25a50cfa970dff55d701cb24bc3aa5924ca12d..d4b223d1392f0721afd1b582ed35d5061294079e 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -542,6 +542,10 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) int ret; u32 sleep_clk_offset = 0x8140; + ret = qcom_cc_attach_pds(&pdev->dev, &video_cc_sm8550_desc); + if (ret) + return ret; + ret = devm_pm_runtime_enable(&pdev->dev); if (ret) return ret; From patchwork Tue Feb 18 14:26:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13980048 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50D4026AAAA; Tue, 18 Feb 2025 14:27:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739888865; cv=none; b=mEBerpG7jP1cmcvEkCBkUKFuPNwtGkTUo5ZUP+NXiYfWG4FoMaGXNYcbG5DFHdJCOJaajASF19WUs8aoneqLIG+l3khoEaGXpLjbfeIKvuDX0Oc4C5/VgYTqGEDOD643VSSmxK+gDPbDtTBg1pLGqi0q/anEW+cC1GhfV2kCnFA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739888865; c=relaxed/simple; bh=3rgyOH9/26VcayvUAl8fp+rwStdFKTqhMgSME8hwOF8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=nDXZbblcHKlNE5BEO7egH5PfZ/aiIVtMqbbX6SDLZXuNq9zyKtXUpuM8BjNQxlm4QMS7BuDwFWQoUPezdt1kDk0sBkdKTh6hzDtetBwhoC3T+kGo4JlRTjVKeL+c1DXAmJfUWWp1iNcedknMx0A21C5zTzmoxkJUpP27udV1ugI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Z45Xk+GA; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Z45Xk+GA" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51ICp3sp003065; Tue, 18 Feb 2025 14:27:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= n9StW93AuXkZCvTTk7MV8gn/vtGlMrxPbQD13sZg6xE=; b=Z45Xk+GAQNqay8hU 5vFIZsDPNjyqV1BQLfMXCzRRAMAtvqwhUWSU6DUtkPb4LF4Tav0C1Zrj2jWbHO2p YFOu6KuOuNgh7EqOfYx0brTd85UcMczUoBuPsqUNQeNMdgzu6Pu9q1N56iF/iAhX 59m8f9LAOn8aJCMhKllChlHm4u+2QvCCkmdKGur0m66aNImxN/q3MMUM3CWwydHD CKrg+l2cK96KCAHGMAva7yqUpWLghqQ3Nr0zmXZE0fGHYf/uYSoGnOQc5eBBye5h hEOjdH+zqbRHUhSqrHUcUNpW7Ra5LC683tx1VPfOhHxGeA6RuWbwM9wnR0Odr1UD +/iiuQ== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44ut7tw587-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Feb 2025 14:27:39 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51IERbJ0026562 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Feb 2025 14:27:37 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 18 Feb 2025 06:27:33 -0800 From: Jagadeesh Kona Date: Tue, 18 Feb 2025 19:56:50 +0530 Subject: [PATCH 5/5] arm64: dts: qcom: Add MXC power domain to videocc nodes Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250218-videocc-pll-multi-pd-voting-v1-5-cfe6289ea29b@quicinc.com> References: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> In-Reply-To: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Jagadeesh Kona X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Vn4iktO0PAaQ8dE0xNnSJHtCQY_ngKHR X-Proofpoint-ORIG-GUID: Vn4iktO0PAaQ8dE0xNnSJHtCQY_ngKHR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-18_07,2025-02-18_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 mlxscore=0 mlxlogscore=470 clxscore=1011 phishscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502180109 Videocc requires both MMCX and MXC rails to be powered ON to configure the video PLLs on SM8450, SM8550 and SM8650 platforms. Hence add MXC power domain to videocc node on these platforms. Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9c809fc5fa45a98ff5441a0b6809931588897243..4f8dca8fc64212191780067c5d8815e3a2bb137f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3136,7 +3136,8 @@ videocc: clock-controller@aaf0000 { reg = <0 0x0aaf0000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index eac8de4005d82f246bc50f64f09515631d895c99..a039ae71e1b7bba8124128d19de5e00c65217770 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2889,7 +2889,8 @@ videocc: clock-controller@aaf0000 { reg = <0 0x0aaf0000 0 0x10000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 86684cb9a9325618ddb74458621cf4bbdc1cc0d1..32af2a0f7a0030f155b7d8c93faeffa384a42768 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3524,7 +3524,8 @@ videocc: clock-controller@aaf0000 { reg = <0 0x0aaf0000 0 0x10000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;