From patchwork Tue Feb 18 20:58:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13980850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6ECF2C021AF for ; Tue, 18 Feb 2025 20:58:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 113B910E761; Tue, 18 Feb 2025 20:58:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="O5QlgjDr"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 43E9410E451; Tue, 18 Feb 2025 20:58:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739912336; x=1771448336; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bsabV6h92XmfSrKmJlod4fAfYVGlzS3AZqfxI4Z69Dc=; b=O5QlgjDrpJUdotZVVK7QZV7uxAHV7MC/+17eRaYrvz7dw1yb1ZBp6d8L QqwfBsBBD8Ols9f4uaiAPfCJo3HhMPjsk/m4mQ4ycgMz2GM9pQXYIaFXS 89KaKS2E1g7cwHWEFoLPu+5m+5WwCyfrz28eg6V5Nv2OKF3LgeJ0YD5kI jsMm1RhA1g9JGJYqu6SgNOJiE10UTu2WTU0W643o9J7cZNi3fVgkb4x/Y r6arVK/ryFLA9mcuf1YcimMdt3a9E5sK24ffapT3ZBtbjcaAXFSftjVQx /62ddxzSQV3WLyhWqRjfw2KyySvd2E3vZZiK8s//bFNq8Xedr7wPgwrTW A==; X-CSE-ConnectionGUID: bPpTdckJSxeBee35inofXA== X-CSE-MsgGUID: xebaRbpMTtKy7ljfqxmMRA== X-IronPort-AV: E=McAfee;i="6700,10204,11348"; a="28228333" X-IronPort-AV: E=Sophos;i="6.13,296,1732608000"; d="scan'208";a="28228333" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2025 12:58:56 -0800 X-CSE-ConnectionGUID: /E5tCJX/TbKXQV5JQhb1DQ== X-CSE-MsgGUID: Gp9iv7NGSAe2kV/YPJ32og== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,296,1732608000"; d="scan'208";a="114688974" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 18 Feb 2025 12:58:54 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 18 Feb 2025 22:58:53 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 1/4] drm/i915/dsb: Allow DSB based updates without planes Date: Tue, 18 Feb 2025 22:58:47 +0200 Message-ID: <20250218205850.1422-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250218205850.1422-1-ville.syrjala@linux.intel.com> References: <20250218205850.1422-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We don't actually need any planes to get updated in order to perform the commit on the DSB. Allow DSB based updates even when we don't touch planes. The main benefit here is that pure LUT updates will now go through the DSB path and therefore we don't have to do vblank evasion/etc. on the CPU. I think the reason I had this excluded was that I was originally contemplating using frame/flip timestamps as a way to complete the commits. But I had to scrap that idea when it turned out that those timestamp get corrupted when DSB is poking at random registers. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 065fdf6dbb88..8d46c092fa4d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7332,7 +7332,6 @@ static void intel_atomic_dsb_prepare(struct intel_atomic_state *state, /* FIXME deal with everything */ new_crtc_state->use_dsb = - new_crtc_state->update_planes && !new_crtc_state->do_async_flip && (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) && !new_crtc_state->scaler_state.scaler_users && From patchwork Tue Feb 18 20:58:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13980851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF0D7C021AA for ; Tue, 18 Feb 2025 20:59:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4118C10E766; Tue, 18 Feb 2025 20:59:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bgqREIsz"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 39C8D10E764; Tue, 18 Feb 2025 20:58:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739912339; x=1771448339; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AzhnFC4+g3ddaFUkjiC3UDtVgGOALeS/wyh/d1tC5qc=; b=bgqREIszySYKf/evUHIuBupY3igLIx0gHe/Hx3rS6rza0VJonJ2sk7C7 XZPRGZZVqFx4Erxzv19HPh+B9CNih5tb4+Tdggi/tl/FmyNH1fkufh2zb 5cptbO2U0oE7z3gUIFktEg459phbnp84bcRC/ScbGv3sUmqVt8c4OyuOa 4/8kahLwq/0X/3//fxtMafsm2U34TFl/6dhG+1HTWmDUZ5/3AeuRCijHl lYWa1xVPtF7QuHQ7Q39gxufiW7/HedsyKdD7vX32mHZLmu+4qKtz4HiqK rpDAP+Qfe7HEBqvzcWsemUJ0Kocpg/9/5OkKZQjUV47dYJtHsc6Rq4Tr/ w==; X-CSE-ConnectionGUID: ITp8N89kSzWL2PwRu/j0+w== X-CSE-MsgGUID: SWIpkTBbTNO9TDZG1/445w== X-IronPort-AV: E=McAfee;i="6700,10204,11348"; a="28228337" X-IronPort-AV: E=Sophos;i="6.13,296,1732608000"; d="scan'208";a="28228337" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2025 12:58:59 -0800 X-CSE-ConnectionGUID: IZMvmkZzRkSJyM9NvlpUuw== X-CSE-MsgGUID: AG43K6cbQDGibYVormp7tg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,296,1732608000"; d="scan'208";a="114688978" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 18 Feb 2025 12:58:57 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 18 Feb 2025 22:58:56 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 2/4] drm/i915/dsb: Plumb dsb into plane scaler functions Date: Tue, 18 Feb 2025 22:58:48 +0200 Message-ID: <20250218205850.1422-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250218205850.1422-1-ville.syrjala@linux.intel.com> References: <20250218205850.1422-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We want to start doing scaler programming (plane scalers only initially) on the DSB. To that end plumb the DSB into the relevant places in the scaler code. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/skl_scaler.c | 60 +++++++++++-------- drivers/gpu/drm/i915/display/skl_scaler.h | 7 ++- .../drm/i915/display/skl_universal_plane.c | 4 +- 4 files changed, 42 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 8d46c092fa4d..826b001a66fa 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6805,7 +6805,7 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, */ if (DISPLAY_VER(dev_priv) >= 9 && !intel_crtc_needs_modeset(new_crtc_state)) - skl_detach_scalers(new_crtc_state); + skl_detach_scalers(NULL, new_crtc_state); if (intel_crtc_vrr_enabling(state, crtc)) intel_vrr_enable(new_crtc_state); diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index 3d24fa773094..ee81220a7c88 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -666,12 +666,14 @@ static u16 glk_nearest_filter_coef(int t) */ static void glk_program_nearest_filter_coefs(struct intel_display *display, + struct intel_dsb *dsb, enum pipe pipe, int id, int set) { int i; - intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(pipe, id, set), - PS_COEF_INDEX_AUTO_INC); + intel_de_write_dsb(display, dsb, + GLK_PS_COEF_INDEX_SET(pipe, id, set), + PS_COEF_INDEX_AUTO_INC); for (i = 0; i < 17 * 7; i += 2) { u32 tmp; @@ -683,11 +685,12 @@ static void glk_program_nearest_filter_coefs(struct intel_display *display, t = glk_coef_tap(i + 1); tmp |= glk_nearest_filter_coef(t) << 16; - intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(pipe, id, set), - tmp); + intel_de_write_dsb(display, dsb, + GLK_PS_COEF_DATA_SET(pipe, id, set), tmp); } - intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); + intel_de_write_dsb(display, dsb, + GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); } static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set) @@ -703,14 +706,15 @@ static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set) return PS_FILTER_MEDIUM; } -static void skl_scaler_setup_filter(struct intel_display *display, enum pipe pipe, +static void skl_scaler_setup_filter(struct intel_display *display, + struct intel_dsb *dsb, enum pipe pipe, int id, int set, enum drm_scaling_filter filter) { switch (filter) { case DRM_SCALING_FILTER_DEFAULT: break; case DRM_SCALING_FILTER_NEAREST_NEIGHBOR: - glk_program_nearest_filter_coefs(display, pipe, id, set); + glk_program_nearest_filter_coefs(display, dsb, pipe, id, set); break; default: MISSING_CASE(filter); @@ -759,7 +763,7 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state) trace_intel_pipe_scaler_update_arm(crtc, id, x, y, width, height); - skl_scaler_setup_filter(display, pipe, id, 0, + skl_scaler_setup_filter(display, NULL, pipe, id, 0, crtc_state->hw.scaling_filter); intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl); @@ -775,7 +779,8 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state) } void -skl_program_plane_scaler(struct intel_plane *plane, +skl_program_plane_scaler(struct intel_dsb *dsb, + struct intel_plane *plane, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { @@ -825,35 +830,38 @@ skl_program_plane_scaler(struct intel_plane *plane, trace_intel_plane_scaler_update_arm(plane, scaler_id, crtc_x, crtc_y, crtc_w, crtc_h); - skl_scaler_setup_filter(display, pipe, scaler_id, 0, + skl_scaler_setup_filter(display, dsb, pipe, scaler_id, 0, plane_state->hw.scaling_filter); - intel_de_write_fw(display, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); - intel_de_write_fw(display, SKL_PS_VPHASE(pipe, scaler_id), - PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); - intel_de_write_fw(display, SKL_PS_HPHASE(pipe, scaler_id), - PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); - intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, scaler_id), - PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y)); - intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, scaler_id), - PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h)); + intel_de_write_dsb(display, dsb, SKL_PS_CTRL(pipe, scaler_id), + ps_ctrl); + intel_de_write_dsb(display, dsb, SKL_PS_VPHASE(pipe, scaler_id), + PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); + intel_de_write_dsb(display, dsb, SKL_PS_HPHASE(pipe, scaler_id), + PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); + intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(pipe, scaler_id), + PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y)); + intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(pipe, scaler_id), + PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h)); } -static void skl_detach_scaler(struct intel_crtc *crtc, int id) +static void skl_detach_scaler(struct intel_dsb *dsb, + struct intel_crtc *crtc, int id) { struct intel_display *display = to_intel_display(crtc); trace_intel_scaler_disable_arm(crtc, id); - intel_de_write_fw(display, SKL_PS_CTRL(crtc->pipe, id), 0); - intel_de_write_fw(display, SKL_PS_WIN_POS(crtc->pipe, id), 0); - intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, id), 0); + intel_de_write_dsb(display, dsb, SKL_PS_CTRL(crtc->pipe, id), 0); + intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(crtc->pipe, id), 0); + intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(crtc->pipe, id), 0); } /* * This function detaches (aka. unbinds) unused scalers in hardware */ -void skl_detach_scalers(const struct intel_crtc_state *crtc_state) +void skl_detach_scalers(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct intel_crtc_scaler_state *scaler_state = @@ -863,7 +871,7 @@ void skl_detach_scalers(const struct intel_crtc_state *crtc_state) /* loop through and disable scalers that aren't in use */ for (i = 0; i < crtc->num_scalers; i++) { if (!scaler_state->scalers[i].in_use) - skl_detach_scaler(crtc, i); + skl_detach_scaler(dsb, crtc, i); } } @@ -873,7 +881,7 @@ void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state) int i; for (i = 0; i < crtc->num_scalers; i++) - skl_detach_scaler(crtc, i); + skl_detach_scaler(NULL, crtc, i); } void skl_scaler_get_config(struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h index 4d2e2dbb1666..355ea15260ca 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.h +++ b/drivers/gpu/drm/i915/display/skl_scaler.h @@ -8,6 +8,7 @@ struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +struct intel_dsb; struct intel_plane; struct intel_plane_state; @@ -21,10 +22,12 @@ int intel_atomic_setup_scalers(struct intel_atomic_state *state, void skl_pfit_enable(const struct intel_crtc_state *crtc_state); -void skl_program_plane_scaler(struct intel_plane *plane, +void skl_program_plane_scaler(struct intel_dsb *dsb, + struct intel_plane *plane, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); -void skl_detach_scalers(const struct intel_crtc_state *crtc_state); +void skl_detach_scalers(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state); void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); void skl_scaler_get_config(struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index cd9762947f1d..3488c7ae6d8a 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1466,7 +1466,7 @@ skl_plane_update_arm(struct intel_dsb *dsb, * TODO: split into noarm+arm pair */ if (plane_state->scaler_id >= 0) - skl_program_plane_scaler(plane, crtc_state, plane_state); + skl_program_plane_scaler(dsb, plane, crtc_state, plane_state); /* * The control register self-arms if the plane was previously @@ -1646,7 +1646,7 @@ icl_plane_update_arm(struct intel_dsb *dsb, * TODO: split into noarm+arm pair */ if (plane_state->scaler_id >= 0) - skl_program_plane_scaler(plane, crtc_state, plane_state); + skl_program_plane_scaler(dsb, plane, crtc_state, plane_state); icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state); From patchwork Tue Feb 18 20:58:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13980852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 870BEC021AD for ; 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X-CSE-ConnectionGUID: yJ9QkooZTU22rj5AF9ytzQ== X-CSE-MsgGUID: dvhLUFDzS8uI/6486n6CFQ== X-IronPort-AV: E=McAfee;i="6700,10204,11348"; a="28228340" X-IronPort-AV: E=Sophos;i="6.13,296,1732608000"; d="scan'208";a="28228340" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2025 12:59:02 -0800 X-CSE-ConnectionGUID: MtYAHxbuT6+mE/ImI/+5Gw== X-CSE-MsgGUID: tDIIudfYRNiuMe0JNc9O+g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,296,1732608000"; d="scan'208";a="114688987" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 18 Feb 2025 12:59:00 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 18 Feb 2025 22:58:59 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 3/4] drm/i915/dsb: Allow DSB based commits when scalers are in use Date: Tue, 18 Feb 2025 22:58:49 +0200 Message-ID: <20250218205850.1422-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250218205850.1422-1-ville.syrjala@linux.intel.com> References: <20250218205850.1422-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Have DSB perform plane scaler programming as well. Changes to pfit/pipe scaler are not being done on the dsb since those take the fastset path. However we do now allow DSB based plane updates when the pfit/pipe scaler is currently enabled (the pfit/pipe scaler just won't be touched by the DSB). Fortunately the hardware issue where some scaler registers are latched at frame start and some at start of vblank has been fixed on icl+ (IIRC), and since DSB is tgl+ only we don't have to do any changes to the DSB vblank evasion. Not that we handle that hardware issue correctly in the CPU vblank evasion either... Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 826b001a66fa..7fd12abdf969 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7319,8 +7319,6 @@ static void intel_atomic_dsb_prepare(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - const struct intel_crtc_state *old_crtc_state = - intel_atomic_get_old_crtc_state(state, crtc); struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); @@ -7334,8 +7332,6 @@ static void intel_atomic_dsb_prepare(struct intel_atomic_state *state, new_crtc_state->use_dsb = !new_crtc_state->do_async_flip && (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) && - !new_crtc_state->scaler_state.scaler_users && - !old_crtc_state->scaler_state.scaler_users && !intel_crtc_needs_modeset(new_crtc_state) && !intel_crtc_needs_fastset(new_crtc_state); @@ -7345,6 +7341,7 @@ static void intel_atomic_dsb_prepare(struct intel_atomic_state *state, static void intel_atomic_dsb_finish(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); @@ -7391,6 +7388,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_crtc_planes_update_arm(new_crtc_state->dsb_commit, state, crtc); + if (DISPLAY_VER(display) >= 9) + skl_detach_scalers(new_crtc_state->dsb_commit, + new_crtc_state); + if (!new_crtc_state->dsb_color_vblank) { intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); From patchwork Tue Feb 18 20:58:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13980853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F9CDC021AD for ; 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X-CSE-ConnectionGUID: h35DToDySZKq7bs8UOwstw== X-CSE-MsgGUID: pYMrhuNyQUGqsKA8I0WKgg== X-IronPort-AV: E=McAfee;i="6700,10204,11348"; a="28228343" X-IronPort-AV: E=Sophos;i="6.13,296,1732608000"; d="scan'208";a="28228343" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2025 12:59:05 -0800 X-CSE-ConnectionGUID: 9J9GEOUzSNWZ9rkTZe9lxw== X-CSE-MsgGUID: oOOUnmtARoeAzo/u/aRzHg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,296,1732608000"; d="scan'208";a="114689002" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 18 Feb 2025 12:59:03 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 18 Feb 2025 22:59:02 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Uma Shankar Subject: [PATCH 4/4] drm/i915: Do state check for color management changes Date: Tue, 18 Feb 2025 22:58:50 +0200 Message-ID: <20250218205850.1422-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250218205850.1422-1-ville.syrjala@linux.intel.com> References: <20250218205850.1422-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä In order to validate LUT programming more thoroughly let's do a state check for all color management updates as well. Not sure we really want this outside CI. It is rather heavy and color management updates could become rather common with all the HDR/etc. stuff happening. Maybe we should have an extra knob for this that we could enable in CI? v2: Skip for initial_commit to avoid FDI dotclock sanity checks/etc. tripping up Reviewed-by: Uma Shankar Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_modeset_verify.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index bc70e72ccc2e..f61641d27c4a 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -239,6 +239,8 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); if (!intel_crtc_needs_modeset(new_crtc_state) && + (!intel_crtc_needs_color_update(new_crtc_state) || + new_crtc_state->inherited) && !intel_crtc_needs_fastset(new_crtc_state)) return;