From patchwork Wed Feb 19 17:20:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 13982558 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49C6A21423F; Wed, 19 Feb 2025 17:20:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739985618; cv=none; b=MqTmtvWMiEp1tPI2glVYiUVUOhokQla9J5pQeQNUrZj2hIY1T5+Ou8Plw9Ju67DQE+KHvKdwI+I6NByY37QOsWCBBuONjzO5FEcwFAz/o+eMjggN49JtvYozPK7LkZ3I/4XcgjKWjsOsfT5bJElREqy9oO4nEQ4nddccR7jOaXI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739985618; c=relaxed/simple; bh=bMSRWL9vhgEV0SWpFh+qnRL63hnQOGX+QjCyihjf6vE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uxQ8PWbo/fuglXQeygtCkVIJBGGxriw7w0SrjpeAvUK+455w++sosGldcWucfpx9awyvOKsrhR9i3rroaCg8hsU8kBz3mPaEuokcOnNefZj7NeRyE9/p6DFRTWDTj5Fn7xOXYIXNTWw+cjGc+ud86ypYFJoDBxrp/tbxN7+RRPc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HfGzKuRJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HfGzKuRJ" Received: by smtp.kernel.org (Postfix) with ESMTPS id C061CC4CEDD; Wed, 19 Feb 2025 17:20:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739985617; bh=bMSRWL9vhgEV0SWpFh+qnRL63hnQOGX+QjCyihjf6vE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HfGzKuRJqxFIQWlGy2hP9VwCCnYYjAUNsv0/v7RaHeLjU/srBm73VQTxDiFcoT5gy bUAem9iShteDeUDvmtZv9HkxfJTcpfSlwFUvDTesXYmPButyZZPQvdqkNGH7O+5/a5 9ADj31JzRjhqsHgTB5sJ7ahQlGocnpCrRCcbL8KIp3L4PIfHnOeIh1wTukWYPRkeWo PdBGadJIkpxUwSydhFnelNwVtXkznNDQV4cN/QU9vJqAfrk2IFA/i7BaSvhivecAip ClKWfFgmO9bJRNLNR7GOBYoqeHiDyLKNFzyV6p/7GnGi0xVlDKxMwiBkzGcy0L5z6p 4vcYfrVNByOYQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0A5FC021B0; Wed, 19 Feb 2025 17:20:17 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Wed, 19 Feb 2025 17:20:19 +0000 Subject: [PATCH 1/6] clk: clk-axi-clkgen: fix fpfd_max frequency for zynq Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250219-dev-axi-clkgen-limits-v1-1-26f7ef14cd9c@analog.com> References: <20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com> In-Reply-To: <20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739985620; l=999; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=3XWz9JBStnY9lwXNwvrymtRHf0DsK7mnM7TrKIE5Q88=; b=CagHeeQdIboKjyeU5BMWDU+YjMPK03N/b7ioxFvpB1lk3BgUHlZ3TLsHbsqZhRj+bAMcgIkBW MFypUeUwB2LCsv7Fhvc3zbcg1h5EJk18I7KXqEEZII+FEzfr0DLkZUP X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá The fpfd_max frequency should be set to 450 MHz instead of 300 MHz. Well, it actually depends on the platform speed grade but we are being conservative for ultrascale so let's be consistent. In a following change we will set these limits at runtime. Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver") Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 934e53a96dddac8ed61dd109cfc188f3a2a0539a..00bf799964c61a3efc042b0f3a9ec3bc8625c9da 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -118,7 +118,7 @@ static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = { static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = { .fpfd_min = 10000, - .fpfd_max = 300000, + .fpfd_max = 450000, .fvco_min = 600000, .fvco_max = 1200000, }; From patchwork Wed Feb 19 17:20:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 13982559 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49B9E214209; Wed, 19 Feb 2025 17:20:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739985618; cv=none; b=nlXigiDIEdWU2/vkRZNH2oO+tHL1vVYp+8EDF7VYn0y1/ZFe2W9347rYyo8rfZOfb+GYQyV/CW0Y9VzAnYOTN5XRea2+0BDZzm7z/XkzUv6L4jRPtG8rJkJfiYmIXTxyh04Kwr6F144dpyaQ3l2wiJuceV2kv8iKgXUf4DeAN+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739985618; c=relaxed/simple; bh=gyCOn420nu33ZZ8ZpTt+CB+QBZMb4ojXZKnLb7lc8r8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eWYbpNDWJDV1WVC7RqVAFBZXmhKY1xdOPr+f9AfqAZGZwOW+FjD7psSJ87XRehydbxWuscbAOA6QNyvccBmfMrD7yOpsUxxPgSM3kzwrPhlKavQAgwFcCD7Jk0okFNtKtBBVwjV3tBE7b0BRerYM84p78PwcluAtTcXDCcdzSzA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ps0flReu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ps0flReu" Received: by smtp.kernel.org (Postfix) with ESMTPS id CDA25C4CEE7; Wed, 19 Feb 2025 17:20:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739985617; bh=gyCOn420nu33ZZ8ZpTt+CB+QBZMb4ojXZKnLb7lc8r8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ps0flReuQt+HJF57c5kpt0ZAbDnkhlQ12FIZiD15d2c63v49uPHzIWiCjeB39lEfi SBdVjliO73Wh05K0uGYrQEG+RqxAvty+oqlUsmzi0EORAQBjVY3IuByYmrtHGg3mNS NC/vOAu8bi8yMKk/zh7ZCSRm3c89ZdfHgLKO2WagD/6sSf3g56nM1ivKWh3UC6O4Qr VHYEeV93ZQBjq9OPa8buMf3MO1r83wTKng3+RBGsCSjHBf0Zl9K8jqhKX8QqvEGvW4 +Im2YY3qpffmYf5kFjoMQAb0HLFeW1RHvf8jEjadCtPncreN0KF5bGrZkfOs9h+c4i rrGGcmGkrUe3A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEC0AC021B2; Wed, 19 Feb 2025 17:20:17 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Wed, 19 Feb 2025 17:20:20 +0000 Subject: [PATCH 2/6] clk: clk-axi-clkgen: make sure to include mod_devicetable.h Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250219-dev-axi-clkgen-limits-v1-2-26f7ef14cd9c@analog.com> References: <20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com> In-Reply-To: <20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739985620; l=659; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=BGGCp0B/QWIWTXslxwf7dXWZP54vUsku9BYioWyTJhQ=; b=VE6/nEVCYXRxFQEzYPWaJ3WVokWfafGzx7yQ8E2/PBZ0+mhT5vF+x3M+B7+7VgB0s27yB9EvS r3y7t+A+EKsA36YmAjkovnsFSYPmHwNBhHvEMW24UuW0kLf10LJtg5I X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá The mod_devicetable header is the one to be used for struct of_device_id. Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 00bf799964c61a3efc042b0f3a9ec3bc8625c9da..2a95f9b220234a1245024a821c50e1eb9c104ac9 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #define AXI_CLKGEN_V2_REG_RESET 0x40 From patchwork Wed Feb 19 17:20:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 13982556 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 133BE1FDA93; Wed, 19 Feb 2025 17:20:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739985618; cv=none; b=ojeXZC+uxCGKdJJCIvx/MqbHzdpmwGp1pXj2KafMz5y84yiNe4F1pg6RaljHmbIcoHOrObNIZ81j2H9DGm9Gwi8Bu+omTxGX1bXGtLXoFA0RGGpuqztUJkcN8n7xOu8rReBz4jdwPBldWL7Gxv38ZUOOwH6Im3eghZWzr5QVBtM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739985618; c=relaxed/simple; bh=e+m0k0M5Z5wNKexhhlUYDfbSJ1xgMvf3PJ1NPl7NcQ8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qBh1ji+m7bl3RXHbdoM4Toom7d2i4uN6tr+jPmyrzv1+DduZ9O/ECQN+86ARby1nkj0HV4nAjCt+PNlFG0W+xsodJNSaORL5kE5NJOgOgM4ONVC0Xq+UYH6YiVHL+NMf7f1eu2/GlgbjFSiEB9V8jgvAQw04Eb++H1RU9x3XjFc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Kd3HYP8E; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Kd3HYP8E" Received: by smtp.kernel.org (Postfix) with ESMTPS id E1F7FC4CEE9; Wed, 19 Feb 2025 17:20:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739985617; bh=e+m0k0M5Z5wNKexhhlUYDfbSJ1xgMvf3PJ1NPl7NcQ8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Kd3HYP8EtFlOBKJuOF4Uy2MsZEobizSikyRcMA38XP04cjCRSB/rQnK0LOsQxJuNZ IHvJN7MPmIRVF5vby2j5uuK9a2AZ54/eYq9CUIckfXwyrfrO3S43iequoR4/fonqSn 4erfQ9Z4r71sAGtdd/TRoTGWzBbO8+AAO8fGupU2kjxOAsvbagWH3Z56vSaR2denMz 1nbputL8z9bgakqS2DBFOWlFKqc5QAj4eQnm4YUIQlpddUY8tLXQkTcS6y37P0aQop QrPaNe0Hm8C8+ituxTXEInjNPPIPW/eVSrV3QYS2NoHIp9t9maxqRgIX/dSmuwjDEW sw9QbuNdOu3Bg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5727C021B1; Wed, 19 Feb 2025 17:20:17 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Wed, 19 Feb 2025 17:20:21 +0000 Subject: [PATCH 3/6] include: fpga: adi-axi-common: add new helper macros Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250219-dev-axi-clkgen-limits-v1-3-26f7ef14cd9c@analog.com> References: <20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com> In-Reply-To: <20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739985620; l=2067; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=yJg4OAu6RcRDDQlB5kvTHzyUpwrZS4HT9bCyy9oa3/U=; b=mMLTxcaS1tOVeHlljXiFRHkGMv3JTZDZLu+MQ6KMv/El0EQ+Qg9DiqHxQa9ZPOgfC88P1oLdh iCDZ7dr0JNuAKUM7GdEyeluoNx8v90P4oKDE6PpxTpvYKulfubyQBXW X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá Add new helper macros and enums to help identifying the platform and some characteristics of it at runtime. Signed-off-by: Nuno Sá --- include/linux/fpga/adi-axi-common.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/include/linux/fpga/adi-axi-common.h b/include/linux/fpga/adi-axi-common.h index 141ac3f251e6f256526812b9d55cd440a2a46e76..747a4ff586708a3dcf34c26ec5aec347cf617b15 100644 --- a/include/linux/fpga/adi-axi-common.h +++ b/include/linux/fpga/adi-axi-common.h @@ -12,6 +12,8 @@ #define ADI_AXI_COMMON_H_ #define ADI_AXI_REG_VERSION 0x0000 +#define ADI_AXI_REG_FPGA_INFO 0x001C +#define ADI_AXI_REG_FPGA_VOLTAGE 0x0140 #define ADI_AXI_PCORE_VER(major, minor, patch) \ (((major) << 16) | ((minor) << 8) | (patch)) @@ -20,4 +22,37 @@ #define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff) #define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff) +#define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff) +#define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff) +#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info) (((info) >> 8) & 0xff) +#define ADI_AXI_INFO_FPGA_VOLTAGE(val) ((val) & 0xffff) + +enum adi_axi_fgpa_technology { + ADI_AXI_FPGA_TECH_UNKNOWN = 0, + ADI_AXI_FPGA_TECH_SERIES7, + ADI_AXI_FPGA_TECH_ULTRASCALE, + ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS, +}; + +enum adi_axi_fpga_family { + ADI_AXI_FPGA_FAMILY_UNKNOWN = 0, + ADI_AXI_FPGA_FAMILY_ARTIX, + ADI_AXI_FPGA_FAMILY_KINTEX, + ADI_AXI_FPGA_FAMILY_VIRTEX, + ADI_AXI_FPGA_FAMILY_ZYNQ, +}; + +enum adi_axi_fpga_speed_grade { + ADI_AXI_FPGA_SPEED_UNKNOWN = 0, + ADI_AXI_FPGA_SPEED_1 = 10, + ADI_AXI_FPGA_SPEED_1L = 11, + ADI_AXI_FPGA_SPEED_1H = 12, + ADI_AXI_FPGA_SPEED_1HV = 13, + ADI_AXI_FPGA_SPEED_1LV = 14, + ADI_AXI_FPGA_SPEED_2 = 20, + ADI_AXI_FPGA_SPEED_2L = 21, + ADI_AXI_FPGA_SPEED_2LV = 22, + ADI_AXI_FPGA_SPEED_3 = 30, +}; + #endif /* ADI_AXI_COMMON_H_ */ From patchwork Wed Feb 19 17:20:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 13982560 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49C0921423C; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IXLlGSKk" Received: by smtp.kernel.org (Postfix) with ESMTPS id EE194C4CEEB; Wed, 19 Feb 2025 17:20:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739985618; bh=N0gDNeAdIYDJBypJgqWPXHM4B/7XjOy4fs/9xKEoAlc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=IXLlGSKkpHeHkxw0NpLXZvn+Gc7csYbpOlLr17+KYgbpEe3esDMQkenkB87JcZPxF uaokuFtflxT+PxyUoswVwdCEHyu6rN8napdlzgFdG+qhMkyzVtf/Saadk1YwklbIVP NRczJuHV4tpFB0It8mCFAynBurWO2wph4CrIpIPnjRwFa27SgSdYBQnkhn61ywj7f7 ENJSXwJc8Uvc4PBPBRXwcs9IpCgyfPE6G6jhEO4nYiDegfSbDnrRQe7bqqqX90BQpi GegKzs8ZsUaz+kF4dVem5R52ypR7MF+jzG1Mt81bmKd09Zvzs0YHgQpoYPceJryK2l RQ3gc6RIteO7A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6FBDC021B0; Wed, 19 Feb 2025 17:20:17 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Wed, 19 Feb 2025 17:20:22 +0000 Subject: [PATCH 4/6] clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250219-dev-axi-clkgen-limits-v1-4-26f7ef14cd9c@analog.com> References: <20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com> In-Reply-To: <20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739985620; l=3698; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=b0wTLM4W+6x7yEOO5vkPSqdl2eWJcNE+mU1J9N7CBFo=; b=87tigZmZ2VB30xP0XViRXKMgD06ggl+eHi4kOBy3IlxV2G1t2oNmZ11lBT1EgNEChGdpx2gia g6Pfm3SrdpAB828ch/iv/8EO8JrnkntpZykteczYrO6gl/K3tLuqwX1 X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá This patch adds support for setting the limits in struct axi_clkgen_limits in accordance with fpga speed grade, voltage, technology and family. This new information is extracted from two new registers implemented in the ip core that are only available for core versions higher or equal to 4. Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 62 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 2a95f9b220234a1245024a821c50e1eb9c104ac9..8c270ba7626bc24c4385615b7aa08ee95e198881 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -16,6 +16,8 @@ #include #include +#include + #define AXI_CLKGEN_V2_REG_RESET 0x40 #define AXI_CLKGEN_V2_REG_CLKSEL 0x44 #define AXI_CLKGEN_V2_REG_DRP_CNTRL 0x70 @@ -497,6 +499,54 @@ static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw) return parent; } +static int axi_clkgen_setup_limits(struct axi_clkgen *axi_clkgen, + struct device *dev) +{ + unsigned int tech, family, speed_grade, reg_value; + + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_FPGA_INFO, ®_value); + tech = ADI_AXI_INFO_FPGA_TECH(reg_value); + family = ADI_AXI_INFO_FPGA_FAMILY(reg_value); + speed_grade = ADI_AXI_INFO_FPGA_SPEED_GRADE(reg_value); + + axi_clkgen->limits.fpfd_min = 10000; + axi_clkgen->limits.fvco_min = 600000; + + switch (speed_grade) { + case ADI_AXI_FPGA_SPEED_1 ... ADI_AXI_FPGA_SPEED_1LV: + axi_clkgen->limits.fvco_max = 1200000; + axi_clkgen->limits.fpfd_max = 450000; + break; + case ADI_AXI_FPGA_SPEED_2 ... ADI_AXI_FPGA_SPEED_2LV: + axi_clkgen->limits.fvco_max = 1440000; + axi_clkgen->limits.fpfd_max = 500000; + if (family == ADI_AXI_FPGA_FAMILY_KINTEX || family == ADI_AXI_FPGA_FAMILY_ARTIX) { + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_FPGA_VOLTAGE, + ®_value); + if (ADI_AXI_INFO_FPGA_VOLTAGE(reg_value) < 950) { + axi_clkgen->limits.fvco_max = 1200000; + axi_clkgen->limits.fpfd_max = 450000; + } + } + break; + case ADI_AXI_FPGA_SPEED_3: + axi_clkgen->limits.fvco_max = 1600000; + axi_clkgen->limits.fpfd_max = 550000; + break; + default: + return dev_err_probe(dev, -ENODEV, "Unknown speed grade %d\n", + speed_grade); + }; + + /* Overwrite vco limits for ultrascale+ */ + if (tech == ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS) { + axi_clkgen->limits.fvco_max = 1600000; + axi_clkgen->limits.fvco_min = 800000; + } + + return 0; +} + static const struct clk_ops axi_clkgen_ops = { .recalc_rate = axi_clkgen_recalc_rate, .determine_rate = axi_clkgen_determine_rate, @@ -511,6 +561,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) { const struct axi_clkgen_limits *dflt_limits; struct axi_clkgen *axi_clkgen; + unsigned int pcore_version; struct clk_init_data init; const char *parent_names[2]; const char *clk_name; @@ -556,7 +607,16 @@ static int axi_clkgen_probe(struct platform_device *pdev) return -EINVAL; } - memcpy(&axi_clkgen->limits, dflt_limits, sizeof(axi_clkgen->limits)); + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_VERSION, &pcore_version); + + if (ADI_AXI_PCORE_VER_MAJOR(pcore_version) > 0x04) { + ret = axi_clkgen_setup_limits(axi_clkgen, &pdev->dev); + if (ret) + return ret; + } else { + memcpy(&axi_clkgen->limits, dflt_limits, + sizeof(axi_clkgen->limits)); + } clk_name = pdev->dev.of_node->name; of_property_read_string(pdev->dev.of_node, "clock-output-names", From patchwork Wed Feb 19 17:20:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 13982557 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F91320E6F9; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KDdCksLP" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0988CC4CEEE; Wed, 19 Feb 2025 17:20:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739985618; bh=4es1eyBKKpCqIekbjwlzdY5OhzypORpRYcmfkLXfn9k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=KDdCksLPzektJVATykRIL1+vlMXfJZGNMRfEIq6nBhoBbFOJRUXAWGYbTUaoEtTpG eX2nt4Iq9InjaKzvhnAM/wNEhxsgYYhht8aInT2J0fH13V2763qEdoc55hjFTLMBoc K+8sUcOAOT1WGrp3Pp2sfmC9gPEhq64bGQZb2ECJWjwAHeZqbDSn8kBtHrb6OdfZl9 1X6+tjNRTfMKqCZF6xneIipMRt5cfv6qL7Nfutb+5ZFK0AL02d6Lyk1AL9s+lmyCCs SC8wnAtCUld/dyx8VWn6RC+MnTH0QKuA/7iaVlqeF3lkOadXo8b7lrHqQeJ/nYjNWJ cwIXUUtYiRhKg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3DF6C021AA; Wed, 19 Feb 2025 17:20:17 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Wed, 19 Feb 2025 17:20:23 +0000 Subject: [PATCH 5/6] clk: clk-axi-clkgen move to min/max() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250219-dev-axi-clkgen-limits-v1-5-26f7ef14cd9c@analog.com> References: <20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com> In-Reply-To: <20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739985620; l=1495; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=dKtpJRfG8e67XLztq7w3SFpV7IL+cAAC4d8nwJYRezc=; b=79EDtsKwfsLPU2lzzPpm5kQnq6fd/Z0f5NE3HV/z0qdK756HI+5vSXWMH2J0HCDCLQ6sqWIzR QjXa4qYZWM2Aahnl9qQBSrEfaY1SFAAA0Rfpf6fCjkR3E4w8QBSuPKz X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá Instead of using the type versions of min/max(), use the plain ones as now they are perfectly capable of handling different types like unsigned and non negative integers that are compiletime constant. Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 8c270ba7626bc24c4385615b7aa08ee95e198881..82a99c3b9063cd2dd8a9dc7fdec81a38feee12b9 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -144,15 +144,15 @@ static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits, *best_m = 0; *best_dout = 0; - d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1); - d_max = min_t(unsigned long, fin / limits->fpfd_min, 80); + d_min = max(DIV_ROUND_UP(fin, limits->fpfd_max), 1); + d_max = min(fin / limits->fpfd_min, 80); again: fvco_min_fract = limits->fvco_min << fract_shift; fvco_max_fract = limits->fvco_max << fract_shift; - m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1); - m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift); + m_min = max(DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1); + m_max = min(fvco_max_fract * d_max / fin, 64 << fract_shift); for (m = m_min; m <= m_max; m++) { _d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract)); From patchwork Wed Feb 19 17:20:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 13982561 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C24F2144A1; Wed, 19 Feb 2025 17:20:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739985618; cv=none; b=vErP1s6CK8apB4kCAZ4ZX6FxjrIWV4wn160SEZkeMHS8lwq6/FbEYDN9bkMp+PP17eJICKp4ZxcfYWuNyVnuYS7DgSPsW0Y6uItvUacXt6VHUyYFH4jiB7X4JbXwa70/uCFtu7LZfpYUHTcJkfzsNf5lvvwYfoiE9JHL6NqESD4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739985618; c=relaxed/simple; bh=i1VGXudil3uO8mpDRLwILbAkxLcKhM1U565yRk8gfXg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AeWKi7Oqq4ZFhcHcKnRbm9m2XZhpep8kC5h0YU6Gy2gwNES6IZRBb+RvG4fnU9yLG/kTPwADeIeiHHzKqxOVMjVPrqddyj1eTOU6iSTjzgjYEsxchNcthSEfBtWys/HZPmm3rjht843FktUfnK881h/oj22ZNQj6QuE5Scrz7+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p2qCmyP5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p2qCmyP5" Received: by smtp.kernel.org (Postfix) with ESMTPS id 20FA0C4CEF0; Wed, 19 Feb 2025 17:20:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739985618; bh=i1VGXudil3uO8mpDRLwILbAkxLcKhM1U565yRk8gfXg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=p2qCmyP5hZUekRMQcJ0nHd0lh/uPFISWV9mb/QQF2+sx9ntZswasaLiNjO4YUy/gh hVlrpN75Cwv6gwepJBrBMF58flW+/yZbCXj97XAZRuoLlkWitl0tfVIbrkXEqya9G6 Iie4G5kfR5g+Q39uOxigSOoUE04Dm7PMx9L2ASTU3AJkl2e2Lq/uDh7l82h80AiDAa MPDoRKrk7HE42vdC9rLXvGqPFrZ54fx5ZZ4cIT6plvTyI+uqQUEYjaZM0LfiaehptK QGpae/Pubf5O3Qw03WUrd7RhKbr5+nOA9QhrgB1+lgQDviLgH+9/DWhtrEBYXNfOMW 0UXiBemb4+o7g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10973C021B2; Wed, 19 Feb 2025 17:20:18 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Wed, 19 Feb 2025 17:20:24 +0000 Subject: [PATCH 6/6] clk: clk-axi-clkgen: fix coding style issues Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250219-dev-axi-clkgen-limits-v1-6-26f7ef14cd9c@analog.com> References: <20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com> In-Reply-To: <20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739985620; l=8515; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=tI86xVg7YOftvhQhe4lqGIGeOGxdqHpIWGA5l8Te3T4=; b=hJnbc8/K+bhq/Lcif6ek1z9lnq9aCHnZLwwZ/JdW8wusoQtBwJt9aTrBw+WeGRWVxv73wYdLx Pme1b4X/TMqAZifURg8pjCdW9zVuNIV/97YtDXqutLYF8H8f8vj27k5 X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá This is just cosmetics and so no functional changes intended. Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 76 +++++++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 37 deletions(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 82a99c3b9063cd2dd8a9dc7fdec81a38feee12b9..c2b5c01698455075ad01d5fad356aa162c53b3bc 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -15,6 +15,7 @@ #include #include #include +#include #include @@ -93,7 +94,7 @@ static uint32_t axi_clkgen_lookup_filter(unsigned int m) } } -static const uint32_t axi_clkgen_lock_table[] = { +static const u32 axi_clkgen_lock_table[] = { 0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8, 0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8, 0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339, @@ -105,7 +106,7 @@ static const uint32_t axi_clkgen_lock_table[] = { 0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113, }; -static uint32_t axi_clkgen_lookup_lock(unsigned int m) +static u32 axi_clkgen_lookup_lock(unsigned int m) { if (m < ARRAY_SIZE(axi_clkgen_lock_table)) return axi_clkgen_lock_table[m]; @@ -127,8 +128,9 @@ static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = { }; static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits, - unsigned long fin, unsigned long fout, - unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout) + unsigned long fin, unsigned long fout, + unsigned int *best_d, unsigned int *best_m, + unsigned int *best_dout) { unsigned long d, d_min, d_max, _d_min, _d_max; unsigned long m, m_min, m_max; @@ -195,9 +197,9 @@ struct axi_clkgen_div_params { }; static void axi_clkgen_calc_clk_params(unsigned int divider, - unsigned int frac_divider, struct axi_clkgen_div_params *params) + unsigned int frac_divider, + struct axi_clkgen_div_params *params) { - memset(params, 0x0, sizeof(*params)); if (divider == 1) { @@ -224,8 +226,8 @@ static void axi_clkgen_calc_clk_params(unsigned int divider, if (params->edge == 0 || frac_divider == 1) params->low--; - if (((params->edge == 0) ^ (frac_divider == 1)) || - (divider == 2 && frac_divider == 1)) + if ((params->edge == 0 ^ frac_divider == 1) || + (divider == 2 && frac_divider == 1)) params->frac_wf_f = 1; params->frac_phase = params->edge * 4 + frac_divider / 2; @@ -233,13 +235,13 @@ static void axi_clkgen_calc_clk_params(unsigned int divider, } static void axi_clkgen_write(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int val) + unsigned int reg, unsigned int val) { writel(val, axi_clkgen->base + reg); } static void axi_clkgen_read(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int *val) + unsigned int reg, unsigned int *val) { *val = readl(axi_clkgen->base + reg); } @@ -260,7 +262,7 @@ static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen) } static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int *val) + unsigned int reg, unsigned int *val) { unsigned int reg_val; int ret; @@ -284,7 +286,8 @@ static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, } static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int val, unsigned int mask) + unsigned int reg, unsigned int val, + unsigned int mask) { unsigned int reg_val = 0; int ret; @@ -305,8 +308,7 @@ static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, return 0; } -static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, - bool enable) +static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, bool enable) { unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE; @@ -322,31 +324,31 @@ static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw) } static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen, - unsigned int reg1, unsigned int reg2, unsigned int reg3, - struct axi_clkgen_div_params *params) + unsigned int reg1, unsigned int reg2, + unsigned int reg3, + struct axi_clkgen_div_params *params) { axi_clkgen_mmcm_write(axi_clkgen, reg1, - (params->high << 6) | params->low, 0xefff); + (params->high << 6) | params->low, 0xefff); axi_clkgen_mmcm_write(axi_clkgen, reg2, - (params->frac << 12) | (params->frac_en << 11) | - (params->frac_wf_r << 10) | (params->edge << 7) | - (params->nocount << 6), 0x7fff); + (params->frac << 12) | (params->frac_en << 11) | + (params->frac_wf_r << 10) | (params->edge << 7) | + (params->nocount << 6), 0x7fff); if (reg3 != 0) { axi_clkgen_mmcm_write(axi_clkgen, reg3, - (params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00); + (params->frac_phase << 11) | (params->frac_wf_f << 10), + 0x3c00); } } -static int axi_clkgen_set_rate(struct clk_hw *clk_hw, - unsigned long rate, unsigned long parent_rate) +static int axi_clkgen_set_rate(struct clk_hw *clk_hw, unsigned long rate, + unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); const struct axi_clkgen_limits *limits = &axi_clkgen->limits; unsigned int d, m, dout; struct axi_clkgen_div_params params; - uint32_t power = 0; - uint32_t filter; - uint32_t lock; + u32 power = 0, filter, lock; if (parent_rate == 0 || rate == 0) return -EINVAL; @@ -366,22 +368,22 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, ¶ms); axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2, - MMCM_REG_CLKOUT5_2, ¶ms); + MMCM_REG_CLKOUT5_2, ¶ms); axi_clkgen_calc_clk_params(d, 0, ¶ms); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV, - (params.edge << 13) | (params.nocount << 12) | - (params.high << 6) | params.low, 0x3fff); + (params.edge << 13) | (params.nocount << 12) | + (params.high << 6) | params.low, 0x3fff); axi_clkgen_calc_clk_params(m >> 3, m & 0x7, ¶ms); axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2, - MMCM_REG_CLKOUT6_2, ¶ms); + MMCM_REG_CLKOUT6_2, ¶ms); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2, - (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff); + (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3, - (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff); + (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900); @@ -410,7 +412,7 @@ static int axi_clkgen_determine_rate(struct clk_hw *hw, } static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen, - unsigned int reg1, unsigned int reg2) + unsigned int reg1, unsigned int reg2) { unsigned int val1, val2; unsigned int div; @@ -437,7 +439,7 @@ static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen, } static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, - unsigned long parent_rate) + unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); unsigned int d, m, dout; @@ -445,9 +447,9 @@ static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, unsigned int val; dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1, - MMCM_REG_CLKOUT0_2); + MMCM_REG_CLKOUT0_2); m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1, - MMCM_REG_CLK_FB2); + MMCM_REG_CLK_FB2); axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val); if (val & MMCM_CLK_DIV_NOCOUNT) @@ -620,7 +622,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) clk_name = pdev->dev.of_node->name; of_property_read_string(pdev->dev.of_node, "clock-output-names", - &clk_name); + &clk_name); init.name = clk_name; init.ops = &axi_clkgen_ops;