From patchwork Thu Feb 20 03:59:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13983278 Received: from mail-lj1-f173.google.com (mail-lj1-f173.google.com [209.85.208.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F8A91D6199 for ; Thu, 20 Feb 2025 03:59:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740023974; cv=none; b=ZsNgn0yJo8n8sEzdlUCxvjJr8eUaMRXRcgM6Z0T1Fmwmz7H0kM5jU8s/3dBWIOK7bqC642awAp59wdKlLoqGKZ3xwa/ts9BUZTtkKh2doXW9m8VhYn5brnB0d2TgiAC9+feIGtMBXaL5OmXpbEW+o4PQNh1bQ+e5wNobSDu+wRY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740023974; c=relaxed/simple; bh=GNObJ2Uc82KNceelQcBkAhl4MJssNBmn9OFMj9GdoG8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bmlS2xFvdbAttZNlIV4pMGnIiliZlUPVzhFt0JMilTB1TE5wBKM1QVzTeq8JanEGpSk3chY6xdz+RfcyrDHVSGnefX40qbsNZtNZLu6mF/RmRmvNuLSmyfBt3JgsOP9CrCGSNDnRCGLek34NT5vfN6dNLw8JdC+FvjvLqPnmG3c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=EClrv0cJ; arc=none smtp.client-ip=209.85.208.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="EClrv0cJ" Received: by mail-lj1-f173.google.com with SMTP id 38308e7fff4ca-30930b0b420so3829491fa.2 for ; Wed, 19 Feb 2025 19:59:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740023970; x=1740628770; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1buqoTyS8LTS0FvAWXv9OjwwCEAG9Q8Buw04m6my9bk=; b=EClrv0cJTxj3hUIJHTBO+aLkZrUQeoLqsPuNC8lbnw7yvUXuKbe4LRIxNnSg/Mf1Aw P1HADAF09+X4S62kK0672giXBZYQwtVJgvFpSbzRulYv0SIYBZcN5EF1vTEGV5KL35HL +xUcr846Bw/voSdT4ESwaOl1tu86ORUff5DtZXTX1Pc21Cwp1+5C6oh6Rmnps3COphWd pHzdbW3vGe0Zo1kiNUxZnnWmjSimorkWzR5oppDecO09d3q/1lACBybOO4+zEF/vn6pn ojLnNMM74L7CyysJOSIIIR6xeEjbkyods79WQz2uJZQtLSlA38DjpUE7IuhjBo51mYFD 99Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740023970; x=1740628770; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1buqoTyS8LTS0FvAWXv9OjwwCEAG9Q8Buw04m6my9bk=; b=sh6AGHlKBPTE2t0pSfrrR8S4+c3E1ODrXDUVmRnS1N2MIN8L7PVzZnUzCzjETlpEJ6 8OrnzFe4QPCKNoLIen1a3BgPETlAk85F8i7B9eIVMvBFmHlBeUbwdlddMtQkj/ms2eFv OeGljNfqiEgBNLPjY8iFyEKLnzwsp29UJtCCpwhuMRJfZy+0N4u9PKp07ZQn4rN/DH6U y0MOgqsdRw93A2sgJVt9k2T61/ZqOmSh96Dy0ehppTPbH30GSFDP8UH6qJTNGuIdVQMl vtUaO9ZnzdjvU8lv5KIU0UfLOCoSBils7THBseNiZEp4iKWoym0yILxxPPZ5lsTCtDW2 Lu/A== X-Gm-Message-State: AOJu0YzwuF///ydaRYc1oAKeVG3zO4Zbvo8TyPTr1uGF0YkjrP4D/t89 Jd1Xk545Yn4Vv0b0r4Fz4pHCVSYcYalu9blkY4dobeUTe6+edbmm9IJ24ed56CE= X-Gm-Gg: ASbGncte7awVsmcDGxca1bhOu1ULu/2uVlmFRXBSy7O+DJ5SMKqa6sMYfEy+JZnOl2y W3C6OUh+91p/rdIeRvGuuODsdvv+2uhVvIoy5C93vbvyU/H++Kj2vQeAp9TZesrbXlTeAbp5z8r m39waILVR+4zK+PNJkYChDZ23FE64JR8mUJJCdVARAl6sCVeHwzHeNo9P8w6KsZKOYLc+00855x 0C98nHZ0Wzcbrq1GiePERsTC5qafgH+U613equXi3Nyn810IdRUykzLuMHbpPgDRQKekv7h9Tvy DtPXuOL4OedvZ+atjewBJD0= X-Google-Smtp-Source: AGHT+IFB5cN6OcdOISTIDzwCna44ZkJ5LDxYOgyNDXJJOJ+6bYILIa/mm9Rz5mRGFEMeDIU6b5l6uA== X-Received: by 2002:a05:6512:2356:b0:545:27dc:64ca with SMTP id 2adb3069b0e04-5462ef19818mr2697703e87.33.1740023969994; Wed, 19 Feb 2025 19:59:29 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-545225f22ebsm2143909e87.16.2025.02.19.19.59.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Feb 2025 19:59:29 -0800 (PST) From: Dmitry Baryshkov Date: Thu, 20 Feb 2025 05:59:22 +0200 Subject: [PATCH v2 1/5] drm/msm/dpu: rename CDM block definition Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250220-dpu-add-cdm-v2-1-77f5f0df3d9a@linaro.org> References: <20250220-dpu-add-cdm-v2-0-77f5f0df3d9a@linaro.org> In-Reply-To: <20250220-dpu-add-cdm-v2-0-77f5f0df3d9a@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3239; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=GNObJ2Uc82KNceelQcBkAhl4MJssNBmn9OFMj9GdoG8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBntqidUq2n2lRLNlCrtDv6lB+4ZMDtYRBGU5i2e K1aGLmhE3eJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ7aonQAKCRCLPIo+Aiko 1aAmB/9iC8sBodCCNsTdZwNmP+kdaeSGLaeeWPtf1IbiV7bMBzo5Pvz9DhNORb05OCZ5TyAf/WD ipEi11Wgp1+lZqs6F08BuwWfjNPutNErNaW1qHqPu5SxrBlDAzX/HXCfoagXqBq/TiJ9dkEJBKs z4zbozXCPJ5A20YQiHWXWV6BWeoYnK+CzNmrvck9HyTA0wzcX9wc/JKwUJn9PTqeHy7LlqniEoS XWzAqhEKZlH8GCn2MaYrm5MbrccNj9eN21HXm39zLPMwV641WGoQD+0tUHUz3y4VSdzA0gdLfx3 SGrfSGlASywMQKW4H75Znr0/8g44MCwYVit+wlP7/P0keeRX X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The CDM block is not limited to SC7280, but it is common to all platforms since DPU 5.x. Rename it from sc7280_cdm to dpu_cdm_5_x. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index e8916ae826a6daf30eb08de53521dae89c07636c..47e01c3c242f9a2ecb201b04be5effd7ff0d04b1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -386,7 +386,7 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = { .mdss_ver = &sm8250_mdss_ver, .caps = &sm8250_dpu_caps, .mdp = &sm8250_mdp, - .cdm = &sc7280_cdm, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sm8250_ctl), .ctl = sm8250_ctl, .sspp_count = ARRAY_SIZE(sm8250_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 2f153e0b5c6a9e319657b99aa0954d9b190fe724..e9625c48c5677ef221b8fc80e7f9df8957b847e2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -248,7 +248,7 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = { .mdss_ver = &sc7280_mdss_ver, .caps = &sc7280_dpu_caps, .mdp = &sc7280_mdp, - .cdm = &sc7280_cdm, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sc7280_ctl), .ctl = sc7280_ctl, .sspp_count = ARRAY_SIZE(sc7280_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 76ec72a323781363d37b62fec752ea1232bbd75b..4d96ce71746f2595427649d0fdb73dae0c18be60 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -458,7 +458,7 @@ const struct dpu_mdss_cfg dpu_sa8775p_cfg = { .mdss_ver = &sa8775p_mdss_ver, .caps = &sa8775p_dpu_caps, .mdp = &sa8775p_mdp, - .cdm = &sc7280_cdm, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sa8775p_ctl), .ctl = sa8775p_ctl, .sspp_count = ARRAY_SIZE(sa8775p_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 0b342c043875f3329a9f71c5e751b2244f9f5ef7..ec7f42a334fc688bec468df490c81a89dd3d396d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -507,7 +507,7 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = { /************************************************************* * CDM block config *************************************************************/ -static const struct dpu_cdm_cfg sc7280_cdm = { +static const struct dpu_cdm_cfg dpu_cdm_5_x = { .name = "cdm_0", .id = CDM_0, .len = 0x228, From patchwork Thu Feb 20 03:59:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13983279 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8677D1DFE3A for ; Thu, 20 Feb 2025 03:59:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740023976; cv=none; b=IoTBYAgM0O6Hhfvk3Q/kTeUo1knf7PYluumd2puZjTsARzS95qyhkP/DcVCba8Ir519DhvdVwASEeXW9Juw/p+37L0+CDX0RAKr7GAaBEdQJjER/dzuRwwe311/sB3GxvLZ+I+DcbwC6oDFU2wn8PxflWAJRxzsedKIlorWZbyo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740023976; c=relaxed/simple; bh=nf1990nbPRPUmWhyQS4UntyiUuMTRclKGAirmxmgwtE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aSucbP6KX52hEpV5iJsXrgpt3LsWBva5JknEfOCiR11+bgJuv3oiHfIqWyOoZmDsYVY1A3BycTKzo76UmcWu4S0OwIfmE6kue2QE0IFMQBnzHF26vgHVX+BUidfxoJnjd+RCf4CiktL+0Y8VGBUlE5m9Fkm6DF7ZQ1NH8/2sYcw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=q2jjsEh2; arc=none smtp.client-ip=209.85.167.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="q2jjsEh2" Received: by mail-lf1-f52.google.com with SMTP id 2adb3069b0e04-5461f2ca386so472170e87.1 for ; Wed, 19 Feb 2025 19:59:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740023972; x=1740628772; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=j2pZmceZvEXbNiDq1E7KLAfqLw7wNQqTqrfWu6Knqbo=; b=q2jjsEh2RLjZmMhzyKgXpqcKogo/7YGPPiJvqKNmzNxSYOP3FeOqrtK+512U5GFsHW EKKTcJxf32ih4SKbDcEzbEc8+M5sGcR6HXTKP7oaLTiNbPzgiV1b000xhJPAmOwNVpCG tVuT0FlScDNBxnh34JwTcrhbggvKnDQXxuXTZGDUPFQvIfFC+LiQn04S2BV4iLjZJWCY 7ww9rSSF76yftsw8jzinGI4HB4/O6IxcrNu5Ad7fPqg8zoh6ShIvJ/N2oIXHd8r+BjmO IUU/s1JHI3EQH9C7MCzUO6Y5w8EgmyfrUCLDKnoNL3No8QKqist1fMsD0oDO6dLIzRIJ ybXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740023972; x=1740628772; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j2pZmceZvEXbNiDq1E7KLAfqLw7wNQqTqrfWu6Knqbo=; b=AdLbDzl4VP8+UkLaR0crfXybhNcZz7S7TOtHQCS57IMs8Ex+qMT4thIPccClQH3RRQ Ta2qK/LcofOrsE8q3Vzemm0sBBBr5croC8tjL8lsRmuzQ9HVhCLQ+wQDkyyTkphN2U+D fuk4/iUthlwPdW/qsXzjqXdzXzR/jbxBV/VrOkpGLBnjfYcoelaCnXQnmwjJGLRNu8sn UAEN2y7fwl4mbs5xZK2I7rV10oHLXn2JWn/GUi3hZRjCpT1rzj2YRGF1TxQ89tuKpizK 4yRLjz+zUhUW7iyyOELf/DYCp7VvbTFOu7K8zyhZ6O3ERN3nEk3Ml23+BDPbw+nRhgTR WfjA== X-Gm-Message-State: AOJu0YyoO3VYDu8z6k336lG/sriJj495BiNouQpA/TMajaIUyfjXshOS mfZZx6BzHcVVtmaeOyS/vC1NBU/rucIGTycovDr/5RRCXhyn38uhV3qeOxvpC+s= X-Gm-Gg: ASbGncteoTOxyTkQ50P9Q/TCFENnbvUSAMggP+4JaiE5nqV8845Q8x51fNmVVYkAo2a /lC/lZUGtojEVapCqxaiF01f0fMb/9kvDBv91uC4umYvxvEqjhjIsGMvlVNFasmV0r5tYGhV4Eu QgCQB92pVzTOMv+lFcOlnZA1hLNGgG61GAyjADRBjysQ9gFFHmeCXyxeP4k/UD33FtsKuhEm3rv v3ZQGd74nCKQFcWCcaDTx77gEgUu3jObow7sSvznAMStYYzoo1ENepmC4j8q2TyKqq5fuu0sjEw saQAYbf+/Y+/J5HNSg7as18= X-Google-Smtp-Source: AGHT+IGk9aAQ5Qp3H6XQfrsAQd91nSzvDsbfoGQxixgjlM46VhY/y1A9U6xZYuAp9drjT2otPqTnxw== X-Received: by 2002:a05:6512:2398:b0:545:2c86:17e6 with SMTP id 2adb3069b0e04-5452fe2f270mr7487945e87.5.1740023972498; Wed, 19 Feb 2025 19:59:32 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-545225f22ebsm2143909e87.16.2025.02.19.19.59.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Feb 2025 19:59:31 -0800 (PST) From: Dmitry Baryshkov Date: Thu, 20 Feb 2025 05:59:23 +0200 Subject: [PATCH v2 2/5] drm/msm/dpu: enable CDM_0 for DPUs 5.x+ Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250220-dpu-add-cdm-v2-2-77f5f0df3d9a@linaro.org> References: <20250220-dpu-add-cdm-v2-0-77f5f0df3d9a@linaro.org> In-Reply-To: <20250220-dpu-add-cdm-v2-0-77f5f0df3d9a@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7830; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=nf1990nbPRPUmWhyQS4UntyiUuMTRclKGAirmxmgwtE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBntqidQBMNbpenHJCJuqAz5esVnj6GyGf2kOiU+ xAvlmkq+M6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ7aonQAKCRCLPIo+Aiko 1bThCACB9GoLVESwKD9dNmVVDT3uPQj6KJvTP4Ozi9KZXH9LDOLwQGNsI4QAaz/CbGemn7GETtD tdHfOaGQ5MZkLxQilqTrQ1AB8XHkbYQRgAhNHGFIO2leAZVJpkWH3z2QWFJIcL95die0FnEWv8L GfryW0QVTruxHuHf4damQhpkhzZ+9sbuKXz0nosWWnHFfhXEuITQAx0e2EGsSK1pQflY2cB86al 9nwhpz7DtELsAI7hSW82RdrxMI6PQK/UQnJ2uL4jrHyagyuQ382zdHg02CCRjIzONLKAshz5VJ3 m6xfruYZpIDSI2fFKXGSkGBpQHc6s4dTq3TLZ+HP1+y5c6OE X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Enable the CDM_0 block on DPU generations starting from 5.x as documented in the vendor dtsi file. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 + 11 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index bcb39807fe61e231d6e318d8729ed86f213fb06a..85fde7243dd4d011ed1e3a5719fd6c98cf7d6e77 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -452,6 +452,7 @@ const struct dpu_mdss_cfg dpu_sm8650_cfg = { .mdss_ver = &sm8650_mdss_ver, .caps = &sm8650_dpu_caps, .mdp = &sm8650_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sm8650_ctl), .ctl = sm8650_ctl, .sspp_count = ARRAY_SIZE(sm8650_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 36cc9dbc00b5c1219e1aa557dd4ee0e801b5c9e7..23188290001ffb45563a9953a9f710bacb4dac89 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -388,6 +388,7 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = { .mdss_ver = &sm8150_mdss_ver, .caps = &sm8150_dpu_caps, .mdp = &sm8150_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sm8150_ctl), .ctl = sm8150_ctl, .sspp_count = ARRAY_SIZE(sm8150_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index e8eacdb47967a227567a96a85a93a69befbb00d5..de8ccf589f1fe026ca0697d48f9533befda4659d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -414,6 +414,7 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = { .mdss_ver = &sc8180x_mdss_ver, .caps = &sc8180x_dpu_caps, .mdp = &sc8180x_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sc8180x_ctl), .ctl = sc8180x_ctl, .sspp_count = ARRAY_SIZE(sc8180x_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index 2fe674d1e05988f39f66a01fedee96113437ea65..b2ebf76e386718b95292e119d53e67f5d9f0743a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -309,6 +309,7 @@ const struct dpu_mdss_cfg dpu_sm7150_cfg = { .mdss_ver = &sm7150_mdss_ver, .caps = &sm7150_dpu_caps, .mdp = &sm7150_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sm7150_ctl), .ctl = sm7150_ctl, .sspp_count = ARRAY_SIZE(sm7150_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index d761ed705bac30d9ffef3c0c9140e5e8a5e930ad..9ac4086b69938799dfe861172f0aec25ee0186f3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -232,6 +232,7 @@ const struct dpu_mdss_cfg dpu_sm6150_cfg = { .mdss_ver = &sm6150_mdss_ver, .caps = &sm6150_dpu_caps, .mdp = &sm6150_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sm6150_ctl), .ctl = sm6150_ctl, .sspp_count = ARRAY_SIZE(sm6150_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index 76f60a2df7a890c5346fe248d67d646ade574fe4..cc2951112bdadca60fe51faeecb81e57280662c3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -216,6 +216,7 @@ const struct dpu_mdss_cfg dpu_sm6125_cfg = { .mdss_ver = &sm6125_mdss_ver, .caps = &sm6125_dpu_caps, .mdp = &sm6125_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sm6125_ctl), .ctl = sm6125_ctl, .sspp_count = ARRAY_SIZE(sm6125_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 7382ebb6e5b2a0c1190e914fb593da93879c0d9a..42a00550eefbc10e97515340d6d8b33d4ef5e3fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -204,6 +204,7 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = { .mdss_ver = &sc7180_mdss_ver, .caps = &sc7180_dpu_caps, .mdp = &sc7180_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sc7180_ctl), .ctl = sc7180_ctl, .sspp_count = ARRAY_SIZE(sc7180_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 0502cee2f116e8ce24a0daf995f46b1d693aacaa..828a02429405238807562dd0aa29575f8367fdc7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -222,6 +222,7 @@ const struct dpu_mdss_cfg dpu_sm6350_cfg = { .mdss_ver = &sm6350_mdss_ver, .caps = &sm6350_dpu_caps, .mdp = &sm6350_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sm6350_ctl), .ctl = sm6350_ctl, .sspp_count = ARRAY_SIZE(sm6350_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index f7c08e89c882038aa658955ca1202bda3d928e80..795e9ebf8c11dcc7d7cae7444fc3e386ced5792d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -396,6 +396,7 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = { .mdss_ver = &sm8350_mdss_ver, .caps = &sm8350_dpu_caps, .mdp = &sm8350_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sm8350_ctl), .ctl = sm8350_ctl, .sspp_count = ARRAY_SIZE(sm8350_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 08742472f9cc812fbaf8f842ff7bd78f597e2b8d..048dfb9dbb601bdbbf6a1326a7af8680f2777b5d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -412,6 +412,7 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = { .mdss_ver = &sm8450_mdss_ver, .caps = &sm8450_dpu_caps, .mdp = &sm8450_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sm8450_ctl), .ctl = sm8450_ctl, .sspp_count = ARRAY_SIZE(sm8450_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 4d3787fceb72fb3641057a7ea04ae6503b671042..a5b90e5e31202900c0bb5bc4a705a6b269005474 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -407,6 +407,7 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = { .mdss_ver = &sm8550_mdss_ver, .caps = &sm8550_dpu_caps, .mdp = &sm8550_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sm8550_ctl), .ctl = sm8550_ctl, .sspp_count = ARRAY_SIZE(sm8550_sspp), From patchwork Thu Feb 20 03:59:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13983280 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 271ED1DFE3A for ; Thu, 20 Feb 2025 03:59:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740023979; cv=none; b=RilznRrujhjIF/SKC4bgyyqLdzU7wMf32kEZjuuSrSCrkrEQOj2Rp3DRSYn3oP8x6yWd7AjmcimSvpHpFdZVNqDleopct2YkNMkpbwq/gx+sE4afKQpPhBeXG0vVImJwT0FPwIg5TT6gFxld9OGur7pVZaNqRRFWhZ135J3pOzA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740023979; c=relaxed/simple; bh=akDkekVVLzHGn2gQgxyT6iyr6q7HQnLI7MIRAAwIajA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KXAZqcTi8ZFM4gLI/khpMg95rW9nwTiS4GQfP7bF/Q0U0a7UrEwb5Dl1AaVAWspcQOoRPcLA04BTcrTIyRroD0zA7lxtGjwwM+KfJgFfg9K62jUMD3GrDNzL6BHkd9QVU02WCkXmoAKX5p1jGlwj5CE5zzGgo/u+PiT+ouJZmCQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=W3PX/RIs; arc=none smtp.client-ip=209.85.167.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="W3PX/RIs" Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-5452c29bacfso604914e87.3 for ; Wed, 19 Feb 2025 19:59:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740023975; x=1740628775; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+iQktoZgMXFUuH/VI1uCNDXJ1CPN0nauJB73520LxmY=; b=W3PX/RIsLmwC+q2Dq4QsVLJvNPJ6/NF0NFeIkv5SF6ulGtEFynZCoi/3AV9cSmfGq0 xmOxRta/yx2L1Zz4UIQUXwxDbVdpHdAfTDHQDpEn1CCOZJ0Izl1SLd+znMwUPU5iE+cP Jt2RI0Gh7os+0BuwZpBi/ENtzgyZs4U2lR+g0kX4GlJMnxAJvjJ+Tih3caXRxxVQvXQs fupABjH/HizB/5lGprlqD76e4SRnDZpRleA36s1v2av3y/4y5CCvyINqOk6zBSdqvSAy kZnUUGSS3Sq7pgjZWdzxMzkWlJgRinyh3TGojyjYgIr7L3cAfgrp4qfah1gkmzLp2LPL 4I0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740023975; x=1740628775; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+iQktoZgMXFUuH/VI1uCNDXJ1CPN0nauJB73520LxmY=; b=M0EOF5Jb2UolpLImFJ4425YafowosG4LzSTwucy8ylFp/GCfhZWcHJ1456Qu9rt5GS bYVu/vYy0pWhWgbmkIleNs83SVIpnykAQqC3vlh2bvWO0WnmJSmeHCNYv+JlwzqsW/Hx MEvgEVlrPbGI62Y/IimZrECQYWJoMVZNu1Oyq4X8ujCql982xzn+z0j66JW+KtENRs17 ruUEFDrXIEqzkc2NRWMj3gnk2ovSjRmhRqCaikCpkoRW6i1+09kfXz/OAA03KYdV2F5i TRIWY1fZwQeo1GKE9BQmen6ujc9FdX+zS5eouDMsX7PovtTeSCccZZ5eKyI8oyg60/Vd IUYw== X-Gm-Message-State: AOJu0YyXJVjW1/YKhAma8GdHlSfjgqSTBmw198gpsUZETXVA93H/mlol T5+eKimuV3aIj70JG58vzl3HEsr5jak08Ogb67IOmxl/UNyxs2zz7ebm0OtRhQc= X-Gm-Gg: ASbGncuJEK8ihldbYFBZASy9UoTl0+igUdh64yY8MOaLwYm/HoRZB3j1ZTgrED7zubH 3zKCcZ2ZNF5OQAU4LsMwGXYxiNIatvan9qCr6GBuHV/1tNPBfrDm8vZ7yQFktd8CfAwnv++3PUj Fy4nQ2QNSOMCHYRYVSy8Bgt6+Nw1pCMVJxOKaSeVyvzfwOHSpnNhOkCIyFzCiTFu+unAZBUZY8F 1NJbb7AXsHg7xIctDUOWNa+khqn6pIGY5dP2Mtt6UJLgMuPoYiwdE09BsDvPhg2mCn72oEkDKaZ NAvX5yl7PXCu7XXfqttxkGA= X-Google-Smtp-Source: AGHT+IHw7aa5o4uaJn+nouzG3FdTcLYjCCQsNGddd5XryyAd4X9xtVduXFEX5mFe+RqzhgSoX2paAw== X-Received: by 2002:a05:6512:238a:b0:545:2300:924d with SMTP id 2adb3069b0e04-5452fe3f69bmr8165563e87.22.1740023975060; Wed, 19 Feb 2025 19:59:35 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-545225f22ebsm2143909e87.16.2025.02.19.19.59.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Feb 2025 19:59:33 -0800 (PST) From: Dmitry Baryshkov Date: Thu, 20 Feb 2025 05:59:24 +0200 Subject: [PATCH v2 3/5] drm/msm/dpu: enable CDM_0 for DPUs 1.x - 4.x Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250220-dpu-add-cdm-v2-3-77f5f0df3d9a@linaro.org> References: <20250220-dpu-add-cdm-v2-0-77f5f0df3d9a@linaro.org> In-Reply-To: <20250220-dpu-add-cdm-v2-0-77f5f0df3d9a@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7366; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=akDkekVVLzHGn2gQgxyT6iyr6q7HQnLI7MIRAAwIajA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBntqidHdzz2cllGriTVveL83n6zPQSayzkPKmLT Gzym3Re3QiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ7aonQAKCRCLPIo+Aiko 1Zt+CAClEde4yYR1pO+IHb7Op+k5ZVM/BBRba55q7cD5ZwxbefaTOABnp+rGAF1etvxhqaIogmN B24Evol5ClsCbzvhG6ixQEVf0QnxrGtsqCSC2ZrPFmjv8590VLiVF1l6SBvsPTInLuWA3GRGg9z ohhf/V/jtT1Q6/NpDaLj75PUcIdO7NpSMDio0OctOxK3hydtj16OB1sVIf1RzF3D8tzFuoeK5lJ hGdcRmwe7B/Q3tNWDn1ft5axI2i0htG6d2amPNtRXWhRR9E5pcy9GdEw+Fd/1qnrMbatOjrfULp 6zzaLaIo2U9wMj6nMkHhHbAHKl1JOXtjs5qqGLtGepFzNqRV X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Enable the CDM_0 block on DPU versions 1.x - 4.x as documented in the vendor dtsi file. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 7 +++++++ 10 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h index ab3dfb0b374ead36c7f07b0a77c703fb2c09ff8a..1f32807bb5e5d49b696832c4eab54c05106bfd4b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -190,6 +190,7 @@ const struct dpu_mdss_cfg dpu_msm8937_cfg = { .mdss_ver = &msm8937_mdss_ver, .caps = &msm8937_dpu_caps, .mdp = msm8937_mdp, + .cdm = &dpu_cdm_1_x_4_x, .ctl_count = ARRAY_SIZE(msm8937_ctl), .ctl = msm8937_ctl, .sspp_count = ARRAY_SIZE(msm8937_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h index 6bdaecca676144f9162ab1839d99f3e2e3386dc7..42131959ff22020a83c0ea65d79a56fd57c800f9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -167,6 +167,7 @@ const struct dpu_mdss_cfg dpu_msm8917_cfg = { .mdss_ver = &msm8917_mdss_ver, .caps = &msm8917_dpu_caps, .mdp = msm8917_mdp, + .cdm = &dpu_cdm_1_x_4_x, .ctl_count = ARRAY_SIZE(msm8917_ctl), .ctl = msm8917_ctl, .sspp_count = ARRAY_SIZE(msm8917_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h index 14f36ea6ad0eb61e87f043437a8cd78bb1bde49c..2b4723a5c67606d68dea905d947cd691bb28eda0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -198,6 +198,7 @@ const struct dpu_mdss_cfg dpu_msm8953_cfg = { .mdss_ver = &msm8953_mdss_ver, .caps = &msm8953_dpu_caps, .mdp = msm8953_mdp, + .cdm = &dpu_cdm_1_x_4_x, .ctl_count = ARRAY_SIZE(msm8953_ctl), .ctl = msm8953_ctl, .sspp_count = ARRAY_SIZE(msm8953_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index 491f6f5827d151011dd3f74bef2a4b8bf69591ab..5cf19de71f060818d257f95aa781b91ec201d4e4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -316,6 +316,7 @@ const struct dpu_mdss_cfg dpu_msm8996_cfg = { .mdss_ver = &msm8996_mdss_ver, .caps = &msm8996_dpu_caps, .mdp = msm8996_mdp, + .cdm = &dpu_cdm_1_x_4_x, .ctl_count = ARRAY_SIZE(msm8996_ctl), .ctl = msm8996_ctl, .sspp_count = ARRAY_SIZE(msm8996_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 64c94e919a69804599916404dff59fa4a6ac6cff..746474679ef5b9ce7ef351e2d5434706d6109d33 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -302,6 +302,7 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = { .mdss_ver = &msm8998_mdss_ver, .caps = &msm8998_dpu_caps, .mdp = &msm8998_mdp, + .cdm = &dpu_cdm_1_x_4_x, .ctl_count = ARRAY_SIZE(msm8998_ctl), .ctl = msm8998_ctl, .sspp_count = ARRAY_SIZE(msm8998_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 424815e7fb7dd858448bd41b5368b729373035f8..4f2f68b07f203a11529f7a680fb87b448305d80a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -269,6 +269,7 @@ const struct dpu_mdss_cfg dpu_sdm660_cfg = { .mdss_ver = &sdm660_mdss_ver, .caps = &sdm660_dpu_caps, .mdp = &sdm660_mdp, + .cdm = &dpu_cdm_1_x_4_x, .ctl_count = ARRAY_SIZE(sdm660_ctl), .ctl = sdm660_ctl, .sspp_count = ARRAY_SIZE(sdm660_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index df01227fc36468f4945c03e767e1409ea4fc0896..c70bef025ac4190347f81d75caf4777786fbeaf7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -205,6 +205,7 @@ const struct dpu_mdss_cfg dpu_sdm630_cfg = { .mdss_ver = &sdm630_mdss_ver, .caps = &sdm630_dpu_caps, .mdp = &sdm630_mdp, + .cdm = &dpu_cdm_1_x_4_x, .ctl_count = ARRAY_SIZE(sdm630_ctl), .ctl = sdm630_ctl, .sspp_count = ARRAY_SIZE(sdm630_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 72bd4f7e9e504c771d999dcf6277fceb169cffca..ab7b4822ca630f8258bc9eb52c0b967e9bc34d18 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -319,6 +319,7 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = { .mdss_ver = &sdm845_mdss_ver, .caps = &sdm845_dpu_caps, .mdp = &sdm845_mdp, + .cdm = &dpu_cdm_1_x_4_x, .ctl_count = ARRAY_SIZE(sdm845_ctl), .ctl = sdm845_ctl, .sspp_count = ARRAY_SIZE(sdm845_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h index daef07924886a529ee30349ae80375a324bbc245..c2fde980fb521d9259a9f1e3bf88cc81f46fdfe8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h @@ -132,6 +132,7 @@ const struct dpu_mdss_cfg dpu_sdm670_cfg = { .mdss_ver = &sdm670_mdss_ver, .caps = &sdm845_dpu_caps, .mdp = &sdm670_mdp, + .cdm = &dpu_cdm_1_x_4_x, .ctl_count = ARRAY_SIZE(sdm845_ctl), .ctl = sdm845_ctl, .sspp_count = ARRAY_SIZE(sdm670_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index ec7f42a334fc688bec468df490c81a89dd3d396d..a6bb46b201e907566e88abce945507d1bab51b3b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -507,6 +507,13 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = { /************************************************************* * CDM block config *************************************************************/ +static const struct dpu_cdm_cfg dpu_cdm_1_x_4_x = { + .name = "cdm_0", + .id = CDM_0, + .len = 0x224, + .base = 0x79200, +}; + static const struct dpu_cdm_cfg dpu_cdm_5_x = { .name = "cdm_0", .id = CDM_0, From patchwork Thu Feb 20 03:59:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13983281 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBB121DEFD9 for ; Thu, 20 Feb 2025 03:59:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740023980; cv=none; b=p25nK7cdgZdYuwB8Jx7eqadLgW/88yH5edABQ5v0aKhO1LIdS5bW2RAssbuWxXNSFTpeI21PuRNa1zul1B5Ja26dLHJ5lxgjTuaznhO3UMoKwMWeBW3N94dGOC8yJ8Q6mg/k7ev+k1erfdn9QBjbDVCTZpbMKm58iwroQ+IXJ/A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740023980; c=relaxed/simple; bh=ksuGoNCpiLiyemIz0C1goT90Bi/HXDBK3gu4zkBcFe4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qMESgVc6DtoOBnQk/kkCywnCNU/hmTbyTKgM8MCX5pCDSO1DqbWMtZowrCJoguInmC7YZcUastKyN8fzxSreDUjCgKRIUmJa8E2gNuN4+1cxkUOUdiYfC9V5mLHqzX+azrlPG9CI+GtnwDRkuaNqa0hXabqECyU15GntLWdnnLk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=oLqw7DWa; arc=none smtp.client-ip=209.85.167.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="oLqw7DWa" Received: by mail-lf1-f49.google.com with SMTP id 2adb3069b0e04-543e47e93a3so605495e87.2 for ; Wed, 19 Feb 2025 19:59:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740023977; x=1740628777; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=EqbHNmz099kigX0TqynbTHurbS64qX/w1xCegrKBwT4=; b=oLqw7DWaSa683TPRLrmJpyENM2uQ/VBBhpBhACltg+gSOBw47kFNR56zttxX/6ab9j gZnxwkUC0rZ2o2CdZdUbas5w2YPu5J81xP4c9x8YoWhG77JLuVsQgeYh2gYVNP/oSwF4 BipGe1Orh01joqUMBoVTx3RMMEGBzhJviRe/WH2oWjbDlLmNYdg8POvlb6HzAt3JhOes UCbPDk9opEVfGOQXV7Bx4DanyVQsRCLDD2GHOizL0u1rlTW8ijVpwFVMTVQioH2hVJfp DDNsgTwJRPnnjheBNuEvQnjgw0ei89vlMEU2RuFq3j7IKC/yndYQMoHP+HqmPif8mQ10 USJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740023977; x=1740628777; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EqbHNmz099kigX0TqynbTHurbS64qX/w1xCegrKBwT4=; b=oVlsCGv5UEbzmLocPlrOjTfGyE79zoO6TXVRwtqqGwB7W5oLFttX0dj72Fauzii8N5 brRs/kNoE2nwj+Mve1kEv9/ZJwtINXNTiQFFsl42dAL5RNnWoTg7CF/MDCw9Hw23H+0w xG3CU65sGTUmEzH5MQguCV7+KEYeJUKFK1wZvUk5rlsacoE/NuVqyK3vIV+sRwxJvMai 8YKBlZXlMkkDxC4k/5qtD9RT7fT6HUGRKW9yLOqQAAf3CYGkGohsUcZUoJtAfd0J9y/p tlvitiLoSUfNbBrX2hkX0jcoAXiLuhA/buVvnYi5rbyRmORhNoR25KYtCZl3dFxydP9u Bf1g== X-Gm-Message-State: AOJu0Yz6GfudYDCk5RUgMPaJ74iN1AxmWdhCo4fsLP0nM6ZLFNTGsMqo aYIyf1AaP3eFt/B6rjJpm+nJe+QFe7xx4UpgDEy6dbTUSm0xR/Oe2vs+uM2s6PA= X-Gm-Gg: ASbGncsAgoU/z5erVzNGM8UG0GeW0Vmj1ef0/BkLszuASiAI/Ud3qSOJ5MOwVjCWuqN v1kkhP+jRtQjESFOgbt6Bnrfpv+yKCnmcdd4/c1kGJymmC0cLKFGhc6pV6zHLrIGqzH5PgepYYf POhrgJXAJSrYpouJjq1e+CBFI5JUMadSi9Vqr6Icjd/G+lKhffI7be2serv+Ecz2FbL5cO226hT VcqhM2hIzdQKGTMer62FrKlzwvRu/xaskza5e0PmzdWV+Hcgn3S9A4Mic2Abvy/BA99KScoJZ8V YJQ+6pxC3bxL9dQErLIkENY= X-Google-Smtp-Source: AGHT+IHNLX1q/p1F1rq4DyZnm4yuozfzfNUpta652kVpbxvogd3CMY4f1V3qt5Csx5Qszd0Ja2VUvw== X-Received: by 2002:a05:6512:110b:b0:545:aaf:13fd with SMTP id 2adb3069b0e04-5452fe76fccmr6884137e87.51.1740023976695; Wed, 19 Feb 2025 19:59:36 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-545225f22ebsm2143909e87.16.2025.02.19.19.59.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Feb 2025 19:59:36 -0800 (PST) From: Dmitry Baryshkov Date: Thu, 20 Feb 2025 05:59:25 +0200 Subject: [PATCH v2 4/5] drm/msm/dpu: enable CDM_0 for SC8280XP platform Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250220-dpu-add-cdm-v2-4-77f5f0df3d9a@linaro.org> References: <20250220-dpu-add-cdm-v2-0-77f5f0df3d9a@linaro.org> In-Reply-To: <20250220-dpu-add-cdm-v2-0-77f5f0df3d9a@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=975; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ksuGoNCpiLiyemIz0C1goT90Bi/HXDBK3gu4zkBcFe4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBntqidVLBOqKTIOpBvG4db7VXVScNmMMC80vm5o Ax1Q2LayhuJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ7aonQAKCRCLPIo+Aiko 1Wt6B/4l0tedtz00rD6xE5Nk2oCfAEA9rif90maR94yeStThnNmOlaypC8JzqTsQwzyfYIDLppP 8Ad965InPWg8vKtWToJBb50m5vxxaubDgD/FQgmQqnFfuFsIzC06Uo2Qy9oTcoyXXPuZbw8YKvi K3VE8dPcvKt/74eD8HOTPHK/u4N5szfXBzG6SvzmYwok1e8rvwd+YVfgta0o9RZGN/sjj8SiXku X8/0zk0CE4KwOPA2Y+s0dzLlE5RBhDGuxMZU3ulsUMoOc/eGdn205hFslC6jxR/QIbBfiY34qJo 9K55rA2S3tsK3K2xjDvxlegOvFKTXSdkAnGCv/toxdPo0Ipm X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Enable CDM on the SC8280XP platform, allowing RGB to YUV conversion for the output. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 0d143e390eca964b1c81f835d0904a2079b0b941..fcee1c3665f88a9defca4fec38dd76d56c97297e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -435,6 +435,7 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = { .mdss_ver = &sc8280xp_mdss_ver, .caps = &sc8280xp_dpu_caps, .mdp = &sc8280xp_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(sc8280xp_ctl), .ctl = sc8280xp_ctl, .sspp_count = ARRAY_SIZE(sc8280xp_sspp), From patchwork Thu Feb 20 03:59:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13983282 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67F031E3DF2 for ; Thu, 20 Feb 2025 03:59:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740023983; cv=none; b=l8f+1ZeR8G2EGR3wtNJUyUvYYSJ5xBaJn+gHSJ5chIAty3ya+FsIznLlTxFu6S+DdQ19UlMDmLjsk7VQVq84sjl1/z8kY3F5i6sULjCnPsCCvuBgTRplJqn4SX53d5WFIAmThjq2IXyrmSV8x+dHhPsYrEzB8/nROSTw82z97LI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740023983; c=relaxed/simple; bh=Q0AAoFwflM5C/JzoUWd/DlT7FRIKp6S0uiQ3bl9uOHU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HVmlrqTuxj4IVuflYGxnpvAP03NWxxdR2+0FDPvZYf6rqxDn3Tx4w8Pfgm3iTFhTKEg84lOIRuCQ5C7Sy0qkcfAfaoiLoV549wjojsUCB6QuAAMN3GtUkMGado1nV7oz247ghPAFNdpkiQi00X5u2r0bnWVcEuj0wI0vrwZZ1xE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=PzmL/MpS; arc=none smtp.client-ip=209.85.167.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PzmL/MpS" Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-5452e6f2999so522972e87.3 for ; Wed, 19 Feb 2025 19:59:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740023979; x=1740628779; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9GONTdbG86yZro8yaESxJ4TpZYRnEloO1TeuZMx3gBM=; b=PzmL/MpSQKiEybsVotJ24UVN9eY5gHIXTpwPCW8w5CLptDKz1HkHB4zLK7BL5XcTdm 1baIHyWZS1Ew6RAogMz0WkOif5+ASIJ26ftGgsOmYDDURQNZwLounOA7YxscnvsPAG2o yrFes0BGtOHoaWWsD8hgdusqoKNhRnBjaWrtxn4rJy9nyp9F/ZZ3MIhsqLy3qL0ed0Ca tD6DI7oimm2H4Vf9/aCZcN5y7ukdo9n8iZ3QWVdWFLjWasV+apTq15TocYI+zfYpnAOF FSLIYFBWKo/qfB9Ia3y7/yp/Xg8w/e2PL2nz1BoaSS0K9Ns77V+kJpsfTrReKypRbxuP 08AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740023979; x=1740628779; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9GONTdbG86yZro8yaESxJ4TpZYRnEloO1TeuZMx3gBM=; b=b3iQLk6hbZtexfx9C3Y+tnwOElwZdyRmkvkb+r2HgpxjjihHRLDvZGh+Ze6aUle4Hi Dxd486fRSBu40jaOUTsmK9md3ZfVybjvefmyUpAcuAqsqYKcBXHH1rM5GXPb0JcDFJjJ IhhKOT9+2le2f8CbQ4Iveic8DtnerXPbNzAyD1hZvkdfs29AnCmWCOqM/Yn2qV9NhDTc fOI1Dl8MW+Tw0Ax8rIXdBho4jf50/3jSMG8J9Q534AXZeK9cz/g5Gji2YpTjrvp39jh1 2VGL6f2UOBMoubAjC0yH1d1BiVzIBzFAf7HZwiH7zpPJyKOrVGIuDv2ZE4qRF4/Lqxwa WDTg== X-Gm-Message-State: AOJu0Yxz8HJS0sW1Uswsc6PSpz35LTSxodakzoT6zdoU/MduuTTzNOSx 4PXwvtciEyL3d9VshAo/CWGdH/KO2EZH8A/MnCBotwdt+OBzBIoefAXK08gaLNQ= X-Gm-Gg: ASbGncv3MhpzYRcqQqQo/bMYfEnh5ntnl5ax9pxL6iqYRVlQeWhFN27k5F0q4YfEGrv nyUizdjOqYd46CoD+uVhUmAWXPNpXBFP9+Oe+6NY2BZxxDjRHwJokzr+q7pUJllp38bPijWMlkH SlJGpisg/wOMWKVhsmbM0EyQ/52K7rHdjwA/g3WxwmSYTo1npDTTgm0Gj2oUSwjPVsxxw/a5yxQ mEfINJvmxcSAhGhfxe2COrqSsAXYHaJgA/3em+y/IEIP0xsdEvF6kEj/Y2gy1rNC8gG9BRtROLH DfZuppSD2mEeIZ3qASBFemo= X-Google-Smtp-Source: AGHT+IEhhy/z8VtOIqW4qjL7UAytFR0EnzQu+f+Os3W5yJxEdSUFdt89d6o9y72QFALZRA2LauuJNw== X-Received: by 2002:ac2:430b:0:b0:545:3032:91fd with SMTP id 2adb3069b0e04-54530329210mr6349493e87.16.1740023979295; Wed, 19 Feb 2025 19:59:39 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-545225f22ebsm2143909e87.16.2025.02.19.19.59.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Feb 2025 19:59:37 -0800 (PST) From: Dmitry Baryshkov Date: Thu, 20 Feb 2025 05:59:26 +0200 Subject: [PATCH v2 5/5] drm/msm/dpu: enable CDM_0 for X Elite platform Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250220-dpu-add-cdm-v2-5-77f5f0df3d9a@linaro.org> References: <20250220-dpu-add-cdm-v2-0-77f5f0df3d9a@linaro.org> In-Reply-To: <20250220-dpu-add-cdm-v2-0-77f5f0df3d9a@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=974; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Q0AAoFwflM5C/JzoUWd/DlT7FRIKp6S0uiQ3bl9uOHU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBntqiduKMlpqumEmY5OPFLoCuQXyc2gb70SXzyJ mywbLuvK72JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ7aonQAKCRCLPIo+Aiko 1b3MB/wPJEdUn5qcCCIEys0QHQbx0quVb/3EjLjFhCH3MdRYOPBQH1q31C0F4p7f+e+OVF7/QZH xS9SxWgd+TAv9ruf2lZt6fOkC1V+laRCZUz0pQsU0dZPi0DArTjuC8YfZxoWN1oSpHfqwriv5Xg tBS4RgB5isOHZnrA0R6xjA7DTCyKsAqSJPsj7+5I10eTetG/ZJ4EJ+K2gBmxZ2oKshysEgPCunS NQOiT7IognnfI77uzPrw3cTJah8MCWi9ngQp86N3Pm9bBxS19eetcS4UWbDb+hboVDZncBa7rQR aM92Cs9GyUESrpBUh37NHHYmUIJpkiONB88BNUMij4JM4ucZ X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Enable CDM on the X Elite platform, allowing RGB to YUV conversion for the output. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 6b112e3d17da6a4423851525262b66aa6c8622e3..8977fa48926b40d486110424f70344c4d29abe80 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -453,6 +453,7 @@ const struct dpu_mdss_cfg dpu_x1e80100_cfg = { .mdss_ver = &x1e80100_mdss_ver, .caps = &x1e80100_dpu_caps, .mdp = &x1e80100_mdp, + .cdm = &dpu_cdm_5_x, .ctl_count = ARRAY_SIZE(x1e80100_ctl), .ctl = x1e80100_ctl, .sspp_count = ARRAY_SIZE(x1e80100_sspp),