From patchwork Thu Feb 20 11:09:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13983807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F048C021B1 for ; Thu, 20 Feb 2025 11:13:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=uPQxzxqy0e5q08kJwlJxX/86t5KQ4xT8+cVHpZb9XXs=; b=uvg0UlzghseFzJLU4stZvZujaM mRVezWWr/HOgLEdHyiQonHeyhnGKe2O6u60uXUMuptgrB2Hx63MswtR8SheRBUFNeUSyuJZiyRpyZ BBQvaz8gPmlLn/gVIuAcPaQ6tkjsE3HtKE+ACYuN/vXnrTZWOPc8PvQxV/ada5COMPqYu2rfrr2L/ u1FU86Ou5osovE3PQ5VzmDD9eITqCfKygpOWcmPiisWic+SdeBxa9kIeYxGtNXpWai/IR9YLvCs9M +5WuatGqw9v241AsrzSqBJN5XxNFj8VhjYidPe4XLlkp4uWs/0aa6AXVG+JyT9MbJjBJqYuTYNxGT tr+QG5ww==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tl4UK-00000000Thi-2EOb; Thu, 20 Feb 2025 11:13:04 +0000 Received: from bali.collaboradmins.com ([148.251.105.195]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tl4RM-00000000Sw0-2tE4; Thu, 20 Feb 2025 11:10:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1740049799; bh=8LNTiqSD2cUqBlyQLegc+6Iq0xpmH5Hud+BUPCQFmjE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ifwgbz7KWQ+c256kIkLH5zet6OyfL3vCqXsjY7VC1a+CmOZhqZHBoUZhgRSlYbmxZ mDyvvboR/QIgVfAUZcJvypv1eHuHcqXlKPH7giEPp5jq+//9Srhituev8GHiOxDS69 mjErXX7ke0fn44r10ggwas3KZeKjN5U9cBGUHa7rclGp08iktVNtnC6lUGCUGMUjRR CKkKl474My2esQqnXZioKjD3aqL/DjsTX3NYt/sIoJlUqOO/R9oUYEdJcP65vPhZ/m R3rVxF5ODGxCU2zlwT4hpvAh599e9Ox5KL/fKjmfdZGHGrBDqOsTXTKTeGkjLFJcLa /3MWoz9EdCyPA== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9EAC017E1560; Thu, 20 Feb 2025 12:09:58 +0100 (CET) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, pablo.sun@mediatek.com Subject: [PATCH v1 1/4] arm64: dts: mediatek: mt8188: Add base display controller graph Date: Thu, 20 Feb 2025 12:09:45 +0100 Message-ID: <20250220110948.45596-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250220110948.45596-1-angelogioacchino.delregno@collabora.com> References: <20250220110948.45596-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250220_031000_876674_A8466B24 X-CRM114-Status: UNSURE ( 9.32 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The display related IPs in MT8188 are flexible and support being interconnected with different instances of DDP IPs and/or with different DDP IPs, forming a full Display Data Path that ends with an actual display output, which is board specific. Add a common graph in the main mt8188.dtsi devicetree, which is shared between all of the currently supported boards. All boards featuring any display functionality will extend this common graph to hook the display controller of the SoC to their specific output port(s). Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 140 +++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index c226998b7e47..4437b1820f26 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2868,6 +2868,23 @@ ovl0: ovl@1c000000 { iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; }; rdma0: rdma@1c002000 { @@ -2878,6 +2895,25 @@ rdma0: rdma@1c002000 { iommus = <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&color0_in>; + }; + }; + }; }; color0: color@1c003000 { @@ -2887,6 +2923,25 @@ color0: color@1c003000 { interrupts = ; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color0_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + color0_out: endpoint { + remote-endpoint = <&ccorr0_in>; + }; + }; + }; }; ccorr0: ccorr@1c004000 { @@ -2896,6 +2951,25 @@ ccorr0: ccorr@1c004000 { interrupts = ; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr0_in: endpoint { + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr0_out: endpoint { + remote-endpoint = <&aal0_in>; + }; + }; + }; }; aal0: aal@1c005000 { @@ -2905,6 +2979,25 @@ aal0: aal@1c005000 { interrupts = ; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal0_in: endpoint { + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + reg = <1>; + aal0_out: endpoint { + remote-endpoint = <&gamma0_in>; + }; + }; + }; }; gamma0: gamma@1c006000 { @@ -2914,6 +3007,23 @@ gamma0: gamma@1c006000 { interrupts = ; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma0_in: endpoint { + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + reg = <1>; + gamma0_out: endpoint { }; + }; + }; }; dither0: dither@1c007000 { @@ -2923,6 +3033,21 @@ dither0: dither@1c007000 { interrupts = ; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + dither0_out: endpoint { }; + }; + }; }; disp_dsi0: dsi@1c008000 { @@ -3005,6 +3130,21 @@ postmask0: postmask@1c01a000 { interrupts = ; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + postmask0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + postmask0_out: endpoint { }; + }; + }; }; vdosys0: syscon@1c01d000 { From patchwork Thu Feb 20 11:09:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13983808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47B5EC021B1 for ; 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Thu, 20 Feb 2025 12:09:59 +0100 (CET) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, pablo.sun@mediatek.com Subject: [PATCH v1 2/4] arm64: dts: mediatek: mt8390-genio-common: Add Display on DSI0 Date: Thu, 20 Feb 2025 12:09:46 +0100 Message-ID: <20250220110948.45596-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250220110948.45596-1-angelogioacchino.delregno@collabora.com> References: <20250220110948.45596-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250220_031002_333614_7A4AD2C8 X-CRM114-Status: GOOD ( 10.84 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Configure the DSI0 display pipeline and add regulator, pinctrl and display node to enable the Startek KD070FHFID078 panel found on the MediaTek Genio 510 and Genio 700 EVKs. Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8390-genio-common.dtsi | 145 +++++++++++++++++- 1 file changed, 137 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index 83828baa887b..0191776e037c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -21,6 +21,7 @@ / { aliases { + dsi0 = &disp_dsi0; ethernet0 = ð i2c0 = &i2c0; i2c1 = &i2c1; @@ -34,6 +35,15 @@ aliases { serial0 = &uart0; }; + backlight_lcm1: backlight-lcm1 { + compatible = "pwm-backlight"; + brightness-levels = <0 1023>; + default-brightness-level = <576>; + num-interpolated-steps = <1023>; + power-supply = <®_vsys>; + pwms = <&disp_pwm1 0 500000>; + }; + chosen { stdout-path = "serial0:921600n8"; }; @@ -218,6 +228,28 @@ usb_p2_vbus: regulator-9 { regulator-max-microvolt = <5000000>; enable-active-high; }; + + lcm1_iovcc: regulator-vio18-lcm1 { + compatible = "regulator-fixed"; + regulator-name = "vio18_lcm1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&pio 111 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_vreg_en_pins>; + vin-supply = <®_vsys>; + }; + + lcm1_vddp: regulator-vsys-lcm1 { + compatible = "regulator-fixed"; + regulator-name = "vsys_lcm1"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_vsys>; + }; }; &adsp { @@ -230,6 +262,67 @@ &afe { status = "okay"; }; +&disp_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "startek,kd070fhfid078", "himax,hx8279"; + reg = <0>; + backlight = <&backlight_lcm1>; + enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 25 GPIO_ACTIVE_HIGH>; + iovcc-supply = <&lcm1_iovcc>; + vdd-supply = <&lcm1_vddp>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_pins>; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; +}; + +&disp_pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm1_pins>; + status = "okay"; +}; + +&dither0_in { + remote-endpoint = <&postmask0_out>; +}; + +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +&gamma0_out { + remote-endpoint = <&postmask0_in>; +}; + &gpu { mali-supply = <&mt6359_vproc2_buck_reg>; status = "okay"; @@ -381,6 +474,10 @@ &mfg1 { domain-supply = <&mt6359_vsram_others_ldo_reg>; }; +&mipi_tx_config0 { + status = "okay"; +}; + &mmc0 { status = "okay"; pinctrl-names = "default", "state_uhs"; @@ -490,6 +587,10 @@ &mt6359codec { mediatek,mic-type-1 = <3>; /* DCC */ }; +&ovl0_in { + remote-endpoint = <&vdosys0_ep_main>; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins_default>; @@ -528,6 +629,12 @@ pins-cmd-dat { }; }; + disp_pwm1_pins: disp-pwm1-pins { + pins-pwm { + pinmux = ; + }; + }; + dptx_pins: dptx-pins { pins-cmd-dat { pinmux = ; @@ -848,20 +955,22 @@ pins-dat1 { }; }; - panel_default_pins: panel-default-pins { - pins-dcdc { - pinmux = ; - output-low; - }; - - pins-en { + dsi0_vreg_en_pins: dsi0-vreg-en-pins { + pins-pwr-en { pinmux = ; output-low; }; + }; + panel_default_pins: panel-default-pins { pins-rst { pinmux = ; - output-high; + output-low; + }; + + pins-en { + pinmux = ; + output-low; }; }; @@ -1039,6 +1148,14 @@ power-key { }; }; +&postmask0_in { + remote-endpoint = <&gamma0_out>; +}; + +&postmask0_out { + remote-endpoint = <&dither0_in>; +}; + &scp { memory-region = <&scp_mem>; status = "okay"; @@ -1091,6 +1208,18 @@ &uart2 { status = "okay"; }; +&vdosys0 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys0_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + }; +}; + &u3phy0 { status = "okay"; }; From patchwork Thu Feb 20 11:09:47 2025 Content-Type: text/plain; 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Thu, 20 Feb 2025 12:10:00 +0100 (CET) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, pablo.sun@mediatek.com Subject: [PATCH v1 3/4] arm64: dts: mediatek: mt8188-geralt: Add graph for DSI and DP displays Date: Thu, 20 Feb 2025 12:09:47 +0100 Message-ID: <20250220110948.45596-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250220110948.45596-1-angelogioacchino.delregno@collabora.com> References: <20250220110948.45596-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250220_031002_898363_7D82648F X-CRM114-Status: GOOD ( 10.64 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The base SoC devicetree now defines a display controller graph: connect the board specific outputs (eDP internal display, DP external display) to fully migrate Cherry and make it finally possible to make Chromebooks and other board types to coexist without per-board driver modifications. Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8188-geralt.dtsi | 155 +++++++++++++++++- 1 file changed, 148 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index faed5c8bc721..c5254ae0bb99 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -9,6 +9,7 @@ / { aliases { + dsi0 = &disp_dsi0; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -273,14 +274,27 @@ dsi_panel: panel@0 { port { dsi_panel_in: endpoint { - remote-endpoint = <&dsi_out>; + remote-endpoint = <&dsi0_out>; }; }; }; - port { - dsi_out: endpoint { - remote-endpoint = <&dsi_panel_in>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; }; }; }; @@ -296,12 +310,74 @@ &disp_pwm1 { pinctrl-0 = <&disp_pwm1_pins>; }; +&dither0_in { + remote-endpoint = <&postmask0_out>; +}; + +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + +&gamma0_out { + remote-endpoint = <&postmask0_in>; +}; + &dp_intf1 { status = "okay"; - port { - dp_intf1_out: endpoint { - remote-endpoint = <&dptx_in>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dp_intf1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dp_intf1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dptx_in>; + }; }; }; }; @@ -394,6 +470,35 @@ &i2c6 { status = "okay"; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_intf1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6359_vproc2_buck_reg>; }; @@ -513,6 +618,10 @@ flash@0 { }; }; +&ovl0_in { + remote-endpoint = <&vdosys0_ep_main>; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; @@ -1029,6 +1138,14 @@ &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; +&postmask0_in { + remote-endpoint = <&gamma0_out>; +}; + +&postmask0_out { + remote-endpoint = <&dither0_in>; +}; + &sound { pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off", "aud_etdm_spk_on", "aud_etdm_spk_off", @@ -1135,6 +1252,30 @@ &ssusb2 { status = "okay"; }; +&vdosys0 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys0_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + }; +}; + +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci2 { /* no power supply since MT7921's power is controlled by PCIe */ /* MT7921's USB BT has issues with USB2 LPM */ From patchwork Thu Feb 20 11:09:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13983832 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5BC8C021B2 for ; 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Thu, 20 Feb 2025 12:10:01 +0100 (CET) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, pablo.sun@mediatek.com Subject: [PATCH v1 4/4] arm64: dts: mediatek: mt8390-genio-common: Configure touch vreg pins Date: Thu, 20 Feb 2025 12:09:48 +0100 Message-ID: <20250220110948.45596-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250220110948.45596-1-angelogioacchino.delregno@collabora.com> References: <20250220110948.45596-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250220_031003_535471_72E9DC5B X-CRM114-Status: UNSURE ( 8.61 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add a pinctrl configuration for the Touchscreen IC's power line to make sure that the pin is configured as GPIO and to stop relying on correct pin configuration from bootloader. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index 0191776e037c..55564d91423f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -187,6 +187,8 @@ touch0_fixed_3v3: regulator-5 { gpio = <&pio 119 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <®_vsys>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_vreg_pins>; }; usb_hub_fixed_3v3: regulator-6 { @@ -1021,6 +1023,13 @@ pins-spi { }; }; + touch_vreg_pins: touch-avdd-pins { + pins-power { + pinmux = ; + output-high; + }; + }; + touch_pins: touch-pins { pins-irq { pinmux = ;