From patchwork Fri Feb 21 00:38:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 13984669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B713C021B2 for ; Fri, 21 Feb 2025 00:39:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6718F10E9FB; Fri, 21 Feb 2025 00:39:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WiTkdodm"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id E091610E1D2; Fri, 21 Feb 2025 00:38:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740098339; x=1771634339; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0zmEJK9xNDGTa3cTtVBOqoV+fxSXnNMjfwBF/uWhVqE=; b=WiTkdodmG/XZtf2eUCHbnLFbvr0VJk0TRWtTxjUUPafGTfFr7qlqN4FJ FvKyToRqc3jECOkck4ay7hT1cATUh+7ngtpmYQckgdT68+3xdsPX0WFi+ xCBZPsZaxAWEsn/w1ni18wNC1K+akLoI6GiECsnv4bCYQdlHE/tTE8dxx NNmMSrJK82LrrNp303Uj3OqlA1toC5BxpyX53Lla5MG6EGo3x+/lx/8Eq jIocotpGYmMXmQFfxO38dNMywVOMkMNSp7jAvS2SAPC8KRWLP1h4M0gnh 24xWkxvGVT+EesWJwEj50hNC4zS3xIqIqvy7i3BPBIswpIXKMY1eIppKR A==; X-CSE-ConnectionGUID: X3X3siM1T02E0KveRPGogQ== X-CSE-MsgGUID: NRCVcLsiSg2mPCysydygMA== X-IronPort-AV: E=McAfee;i="6700,10204,11351"; a="44688687" X-IronPort-AV: E=Sophos;i="6.13,303,1732608000"; d="scan'208";a="44688687" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2025 16:38:59 -0800 X-CSE-ConnectionGUID: +hMh3CYXSM22atx2SJQG4g== X-CSE-MsgGUID: Fg+svk8HQh+vZc7WMxUqKg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="120446840" Received: from mdroper-desk1.fm.intel.com ([10.1.39.133]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2025 16:38:57 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: matthew.d.roper@intel.com Subject: [PATCH 1/4] drm/i915/display: Make refclk fetching logic reusable Date: Thu, 20 Feb 2025 16:38:45 -0800 Message-ID: <20250221003843.443559-7-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250221003843.443559-6-matthew.d.roper@intel.com> References: <20250221003843.443559-6-matthew.d.roper@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" There's cdclk-specific code to obtain the display reference clock, either by reading a strap register, or by using a platform-specific hardcoded value. There's at least one other place in our drivers that potentially needs this clock frequency, so refactor the logic to make it more generally usable. While we're at it, change the fallback frequency we assume if the strap readout gives us something unrecognizable to 38.4MHz for platforms with display version 14 and above. 38.4MHz seems to be the sole frequency that's actually been used in recent history (since MTL), so this is probably the safest guess to make going forward. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cdclk.c | 44 +++++++++++++--------- drivers/gpu/drm/i915/display/intel_cdclk.h | 1 + 2 files changed, 28 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index c6cfc57a0346..57b01f8a7be8 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1636,38 +1636,48 @@ static u8 xe3lpd_calc_voltage_level(int cdclk) return 0; } -static void icl_readout_refclk(struct intel_display *display, - struct intel_cdclk_config *cdclk_config) +static u32 icl_readout_refclk(struct intel_display *display) { u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; switch (dssm) { - default: - MISSING_CASE(dssm); - fallthrough; case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: - cdclk_config->ref = 24000; - break; + return 24000; case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: - cdclk_config->ref = 19200; - break; + return 19200; case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: - cdclk_config->ref = 38400; - break; + return 38400; + default: + MISSING_CASE(dssm); + return DISPLAY_VER(display) >= 14 ? 38400 : 24000; } } +/** + * intel_display_get_refclk - Returns the display reference clock + * @display: display instance + * + * Returns the display reference clock in KHz. The display reference clock + * is defined by the SoC; on some platforms the proper value should be read + * from a hardware strap register, while on others there's only a single + * possible value. + */ +u32 intel_display_get_refclk(struct intel_display *display) +{ + if (display->platform.dg2) + return 38400; + else if (DISPLAY_VER(display) >= 11) + return icl_readout_refclk(display); + else + return 19200; +} + static void bxt_de_pll_readout(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { u32 val, ratio; - if (display->platform.dg2) - cdclk_config->ref = 38400; - else if (DISPLAY_VER(display) >= 11) - icl_readout_refclk(display, cdclk_config); - else - cdclk_config->ref = 19200; + cdclk_config->ref = intel_display_get_refclk(display); val = intel_de_read(display, BXT_DE_PLL_ENABLE); if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index 6b0e7a41eba3..3cfbe1f2b6b5 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -65,6 +65,7 @@ void intel_init_cdclk_hooks(struct intel_display *display); void intel_update_max_cdclk(struct intel_display *display); void intel_update_cdclk(struct intel_display *display); u32 intel_read_rawclk(struct intel_display *display); +u32 intel_display_get_refclk(struct intel_display *display); bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b); int intel_mdclk_cdclk_ratio(struct intel_display *display, From patchwork Fri Feb 21 00:38:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 13984670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26359C021B3 for ; Fri, 21 Feb 2025 00:39:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7349110E9FC; Fri, 21 Feb 2025 00:39:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ezF24ATQ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 277C810E1D2; Fri, 21 Feb 2025 00:38:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740098339; x=1771634339; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BkFRu1D+mgWUo4LkjEQ5E8iuEbI8wBKJsdAHnm8GI3M=; b=ezF24ATQE70xuq5l9nkLWAuN5fq+HZWPLapyHxxCpWhje3KUdiugl5VR SoNT4w5IG/5Ev+cEioWGlR7w7sx5Yyq3Z/p76I304URDoiIj8CQvyKp/Y USBJZAoPTssm0lXPZYgOi63+ARU1xPx+Qrr41cZSTrRJFwo1UoYwgRp77 l4AP/Xt8CzI6qp6H7aVdcmpD5mxL1AlpSQnVC2MAyOBMuOlUVJhu1bF34 1s5lz0J4SuHqtPzhgVMu6yX5dNBTOXG8VSwpq2Mi6GzHo6pzT9jXiS8Ln Z9lgk4ARi1JQXE8DxMQqNlbkonUYIHVbxkoF/5sutnmji5gzgZ1JPqt6f Q==; X-CSE-ConnectionGUID: ku779RPGTc6gk24/gjw0HA== X-CSE-MsgGUID: MmPeKKf2RaSv2h1QeM/xkw== X-IronPort-AV: E=McAfee;i="6700,10204,11351"; a="44688688" X-IronPort-AV: E=Sophos;i="6.13,303,1732608000"; d="scan'208";a="44688688" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2025 16:38:59 -0800 X-CSE-ConnectionGUID: VXO9NkPXTHmEea3+hY+FHA== X-CSE-MsgGUID: tpldQxaZQF+P7iqIw0Ih4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="120446843" Received: from mdroper-desk1.fm.intel.com ([10.1.39.133]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2025 16:38:58 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: matthew.d.roper@intel.com Subject: [PATCH 2/4] drm/i915/gt: Replace TIMESTAMP_OVERRIDE readout Date: Thu, 20 Feb 2025 16:38:46 -0800 Message-ID: <20250221003843.443559-8-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250221003843.443559-6-matthew.d.roper@intel.com> References: <20250221003843.443559-6-matthew.d.roper@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The whole GT CS clock initialization area is poorly documented in the specs and a lot of this code seems to have been inherited from the Windows driver team long ago. There's nothing in the specs that specifically explains using the display reference frequency, as taken from TIMESTAMP_OVERRIDE register, to determine the GT command streamer clock. But if the goal is just to get the display reference clock, we already have existing display code that takes care of that in a more straightforward manner (i.e., by either reading the strap register or using a per-platform constant). Let's drop the usage of TIMESTAMP_OVERRIDE (which is a bit questionable to begin with since this is a display debug register) and replace it with a call to our existing display function. Signed-off-by: Matt Roper --- .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 31 ++++++------------- 1 file changed, 9 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c index 6e63505fe478..adc21c3322da 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c @@ -11,23 +11,6 @@ #include "intel_gt_regs.h" #include "soc/intel_dram.h" -static u32 read_reference_ts_freq(struct intel_uncore *uncore) -{ - u32 ts_override = intel_uncore_read(uncore, GEN9_TIMESTAMP_OVERRIDE); - u32 base_freq, frac_freq; - - base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; - base_freq *= 1000000; - - frac_freq = ((ts_override & - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); - frac_freq = 1000000 / (frac_freq + 1); - - return base_freq + frac_freq; -} - static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore, u32 rpm_config_reg) { @@ -64,12 +47,14 @@ static u32 gen11_read_clock_frequency(struct intel_uncore *uncore) * We do not, and we assume nobody else does. * * First figure out the reference frequency. There are 2 ways - * we can compute the frequency, either through the - * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE - * tells us which one we should use. + * we can compute the frequency, either from the display reference + * clock or through RPM_CONFIG. CTC_MODE tells us which one we should + * use. */ if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { - freq = read_reference_ts_freq(uncore); + struct intel_display *display = &uncore->i915->display; + + freq = intel_display_get_refclk(display) * 1000; } else { u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0); @@ -93,7 +78,9 @@ static u32 gen9_read_clock_frequency(struct intel_uncore *uncore) u32 freq = 0; if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { - freq = read_reference_ts_freq(uncore); + struct intel_display *display = &uncore->i915->display; + + freq = intel_display_get_refclk(display) * 1000; } else { freq = IS_GEN9_LP(uncore->i915) ? 19200000 : 24000000; From patchwork Fri Feb 21 00:38:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 13984668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1864BC021B5 for ; Fri, 21 Feb 2025 00:39:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6642510E9F9; Fri, 21 Feb 2025 00:39:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="U9/DLuEo"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 663CC10E1D2; Fri, 21 Feb 2025 00:38:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740098340; x=1771634340; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mG4nzyPFSZQYSuTaQlsfgFmUg68zNqckZ/XGFwVIReQ=; b=U9/DLuEooPa/6L6JM6tDcdjWtOLzcrOKW1z4+j5VC/+A1me0QmJHMB/5 J2WK2vVVCbxgopCTNGdheAwVlmSYXXzCk0MzNTF9iY4dC2rQA3tsruQ05 LPZYfTMdCsDOwEKnn3pXRT107tpNFILQq5jSnDzI7UlK/QXI8PttaNBWq o/tBIVUpeibtvrZF6WUBfzzXdJXcScSmUmmPpBElAnTM+wIkbYlKNCsxc kTlzXQcG/rFOtu2dPDWu3XAbq/QlxNd/wQiAOZg49jWLeBtcK7fbPdxan M9gd65KcegcKK2JAQmtqy7eu8Ljmz+2unEYNRVeV+8v6tx03EBrhye2aU A==; X-CSE-ConnectionGUID: Q+r0Lu56SMCOOhRWf5Pw+A== X-CSE-MsgGUID: mD1lHQGhT6SKQLRtuc5PYg== X-IronPort-AV: E=McAfee;i="6700,10204,11351"; a="44688689" X-IronPort-AV: E=Sophos;i="6.13,303,1732608000"; d="scan'208";a="44688689" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2025 16:39:00 -0800 X-CSE-ConnectionGUID: FklTV5skTGuuztDNHxgQUQ== X-CSE-MsgGUID: Fm0rukoMR4qd3kzaqdMG0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="120446846" Received: from mdroper-desk1.fm.intel.com ([10.1.39.133]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2025 16:38:58 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: matthew.d.roper@intel.com Subject: [PATCH 3/4] drm/xe: Drop usage of TIMESTAMP_OVERRIDE Date: Thu, 20 Feb 2025 16:38:47 -0800 Message-ID: <20250221003843.443559-9-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250221003843.443559-6-matthew.d.roper@intel.com> References: <20250221003843.443559-6-matthew.d.roper@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On pre-Xe2 platforms, one of the approaches to initialize the GT command streamer frequency is to use the display reference clock. That's no longer relevant from Xe2 onward (i.e., all of the platforms where Xe is officially supported). Furthermore, use of TIMESTAMP_OVERRIDE to obtain the display reference clock is unnecessarily roundabout; the display driver already has a more reliable approach to obtain this value. Let's use the display driver's existing logic to determine the proper display reference clock in the rare cases where the hardware indicates we should do this. The one problem that arises here is if the Xe driver is run on an unsupported platform (i.e., pre-Xe2), CONFIG_DRM_XE_DISPLAY disabled (meaning we're not expecting to touch display hardware at all), and the platform has the rare CTC_MODE[1] setting indicating that display reference clock should be used as the GT CS refclk. If all of these conditions are true, the hardcoded 38.4 MHz value will still be correct for DG2 and MTL platforms, but there's a chance that we might not have the right value on the older Xe_LP platforms if we're trying not to touch the display hardware at all. Bspec: 62395 Signed-off-by: Matt Roper --- drivers/gpu/drm/xe/display/xe_display.c | 6 ++++++ drivers/gpu/drm/xe/display/xe_display.h | 4 ++++ drivers/gpu/drm/xe/xe_gt_clock.c | 28 ++++++++----------------- 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c index 02a413a07382..e35d58079f0d 100644 --- a/drivers/gpu/drm/xe/display/xe_display.c +++ b/drivers/gpu/drm/xe/display/xe_display.c @@ -17,6 +17,7 @@ #include "intel_acpi.h" #include "intel_audio.h" #include "intel_bw.h" +#include "intel_cdclk.h" #include "intel_display.h" #include "intel_display_driver.h" #include "intel_display_irq.h" @@ -548,3 +549,8 @@ int xe_display_probe(struct xe_device *xe) unset_display_features(xe); return 0; } + +u32 xe_display_get_refclk(struct xe_device *xe) +{ + return intel_display_get_refclk(&xe->display); +} diff --git a/drivers/gpu/drm/xe/display/xe_display.h b/drivers/gpu/drm/xe/display/xe_display.h index 685dc74402fb..b918f5d6b53a 100644 --- a/drivers/gpu/drm/xe/display/xe_display.h +++ b/drivers/gpu/drm/xe/display/xe_display.h @@ -41,6 +41,8 @@ void xe_display_pm_runtime_suspend(struct xe_device *xe); void xe_display_pm_runtime_suspend_late(struct xe_device *xe); void xe_display_pm_runtime_resume(struct xe_device *xe); +u32 xe_display_get_refclk(struct xe_device *xe); + #else static inline int xe_display_driver_probe_defer(struct pci_dev *pdev) { return 0; } @@ -72,5 +74,7 @@ static inline void xe_display_pm_runtime_suspend(struct xe_device *xe) {} static inline void xe_display_pm_runtime_suspend_late(struct xe_device *xe) {} static inline void xe_display_pm_runtime_resume(struct xe_device *xe) {} +static u32 xe_display_get_refclk(struct xe_device *xe) { return 38400; } + #endif /* CONFIG_DRM_XE_DISPLAY */ #endif /* _XE_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c index cc2ae159298e..b61f944a7b03 100644 --- a/drivers/gpu/drm/xe/xe_gt_clock.c +++ b/drivers/gpu/drm/xe/xe_gt_clock.c @@ -7,6 +7,7 @@ #include "xe_gt_clock.h" +#include "display/xe_display.h" #include "regs/xe_gt_regs.h" #include "regs/xe_regs.h" #include "xe_assert.h" @@ -15,22 +16,6 @@ #include "xe_macros.h" #include "xe_mmio.h" -static u32 read_reference_ts_freq(struct xe_gt *gt) -{ - u32 ts_override = xe_mmio_read32(>->mmio, TIMESTAMP_OVERRIDE); - u32 base_freq, frac_freq; - - base_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK, - ts_override) + 1; - base_freq *= 1000000; - - frac_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK, - ts_override); - frac_freq = 1000000 / (frac_freq + 1); - - return base_freq + frac_freq; -} - static u32 get_crystal_clock_freq(u32 rpm_config_reg) { const u32 f19_2_mhz = 19200000; @@ -57,14 +42,19 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg) int xe_gt_clock_init(struct xe_gt *gt) { + struct xe_device *xe = gt_to_xe(gt); u32 ctc_reg = xe_mmio_read32(>->mmio, CTC_MODE); u32 freq = 0; /* Assuming gen11+ so assert this assumption is correct */ - xe_gt_assert(gt, GRAPHICS_VER(gt_to_xe(gt)) >= 11); + xe_gt_assert(gt, GRAPHICS_VER(xe) >= 11); - if (ctc_reg & CTC_SOURCE_DIVIDE_LOGIC) { - freq = read_reference_ts_freq(gt); + /* + * Use of the display reference clock to determine GT CS frequency + * is only relevant to pre-Xe2 platforms. + */ + if (GRAPHICS_VER(xe) < 20 && ctc_reg & CTC_SOURCE_DIVIDE_LOGIC) { + freq = xe_display_get_refclk(xe); } else { u32 c0 = xe_mmio_read32(>->mmio, RPM_CONFIG0); From patchwork Fri Feb 21 00:38:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 13984671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2CBA3C021B2 for ; Fri, 21 Feb 2025 00:39:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B25310EA03; Fri, 21 Feb 2025 00:39:09 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="B45NHh5d"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA34610E1D2; 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20 Feb 2025 16:39:00 -0800 X-CSE-ConnectionGUID: KlAiUkQ2Tuyg+txxfi45ow== X-CSE-MsgGUID: M0GB8PZzQyeQxrnUlLqwPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="120446849" Received: from mdroper-desk1.fm.intel.com ([10.1.39.133]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2025 16:38:58 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: matthew.d.roper@intel.com, Michal Wajdeczko , Jakub Kolakowski , Lucas De Marchi Subject: [PATCH 4/4] drm/xe/sriov: Drop TIMESTAMP_OVERRIDE from Xe2 runtime regs Date: Thu, 20 Feb 2025 16:38:48 -0800 Message-ID: <20250221003843.443559-10-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250221003843.443559-6-matthew.d.roper@intel.com> References: <20250221003843.443559-6-matthew.d.roper@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" TIMESTAMP_OVERRIDE is never used to initialize the GT clock frequency on Xe2 platforms (and the register itself no longer exists on LNL) so drop it from the list of runtime registers. Cc: Michal Wajdeczko Cc: Jakub Kolakowski Acked-by: Michal Wajdeczko Reviewed-by: Lucas De Marchi Signed-off-by: Matt Roper --- drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c index 6b5f849a0722..f54061dec3c8 100644 --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c @@ -173,7 +173,6 @@ static const struct xe_reg ver_2000_runtime_regs[] = { XE2_GT_GEOMETRY_DSS_2, /* _MMIO(0x9154) */ CTC_MODE, /* _MMIO(0xa26c) */ HUC_KERNEL_LOAD_INFO, /* _MMIO(0xc1dc) */ - TIMESTAMP_OVERRIDE, /* _MMIO(0x44074) */ }; static const struct xe_reg ver_3000_runtime_regs[] = {