From patchwork Fri Feb 21 18:03:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincenzo Frascino X-Patchwork-Id: 13986134 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F21DC021B3 for ; Fri, 21 Feb 2025 18:07:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=84Pcn76Z63L/Hn2mjBRY1USicoufGMqrE0pe5JmE7uQ=; b=Lobogt0gCTRJqkyiHMplEEAc3v L4WZ9jWPRFW8rei34nOyGRi/ljWaAJm6Qq0Yffzj+CbnjUP93uu4cyZwu+2DP3pSM/neF4B6lXQ31 ZOuJ9Jtu+hFBjGKm0WGDDRVv9AAvlvBnJhk4t/gvYVdtisLCqgs+m+/c/Jlkxd+VrEQs0vcZLYua+ kPg8XlFAXiRq/4hGr+MZgc5XJuz2eBo1yLybbvKIixo/661TAD5NPc+7JaidXNpJ/moDln0gDdCRF JydBY3wqPs0SuZLeuN+1OdNBU9uLT6c1JYcwAW21u3V5LtpLvVwo8fkywCDX9dnoBLph4RggL1TBI BN7VcgkQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXQi-00000006Suj-2cmc; Fri, 21 Feb 2025 18:07:16 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXNX-00000006SCs-0KFg for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 18:04:00 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6567B1CC4; Fri, 21 Feb 2025 10:04:16 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 90B463F59E; Fri, 21 Feb 2025 10:03:56 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 01/10] arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESS Date: Fri, 21 Feb 2025 18:03:40 +0000 Message-ID: <20250221180349.1413089-2-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_100359_170725_1AFD98F1 X-CRM114-Status: GOOD ( 10.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Update the description and contextually the help text of CONFIG_ARCH_VEXPRESS to reflect the inclusion of all ARM Ltd Platforms. Signed-off-by: Vincenzo Frascino --- arch/arm64/Kconfig.platforms | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 02f9248f7c84..c468c23b2bba 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -374,13 +374,12 @@ config ARCH_UNIPHIER This enables support for Socionext UniPhier SoC family. config ARCH_VEXPRESS - bool "ARMv8 software model (Versatile Express)" + bool "ARM Ltd Platforms" select GPIOLIB select PM select PM_GENERIC_DOMAINS help - This enables support for the ARMv8 software model (Versatile - Express). + This enables support for the ARM Ltd Platforms. config ARCH_VISCONTI bool "Toshiba Visconti SoC Family" From patchwork Fri Feb 21 18:03:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincenzo Frascino X-Patchwork-Id: 13986135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B978BC021B5 for ; Fri, 21 Feb 2025 18:08:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=H93iyX4QsIjRvuarMUU+zmaDywtAgxNZUW5MXDIbqH0=; b=WyRk6Z6Lbk8ctTDbkDkI3/etQf iqJb0BNWIdEuLFBElEOKptPgfKYs9K0SV4mYxRhGOLAwrFcbtJ9ncQj7/k784uuxfARqAWWAtD1zb n2RkP1IU2WOXxbWu9Qr6iBdWnfpsvtwIXYnHE+aj4QlrtqFM+6P91lM5SFaaS/PEceyy46FJl5DZx vgpvsgR6JhgVxhdS9DphDjLkF32Og1UUdqOZBct2lqdqdCZkEs8ccOSNnRLcxm/gwxqfCg4nIeHhi H+oT46FoIy0G396qAM+RB9PI3bMKAP4SK0ODcjVR6mDoKzgniUo+dD6HSFBHu9mTQtOZX1Vi/xrat UyLb+MNw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXSA-00000006TF7-0zrR; Fri, 21 Feb 2025 18:08:46 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXNZ-00000006SDE-2VJb for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 18:04:02 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ECBD2169C; Fri, 21 Feb 2025 10:04:18 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 052803F59E; Fri, 21 Feb 2025 10:03:58 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke , Krzysztof Kozlowski Subject: [PATCH v7 02/10] dt-bindings: arm: Add Morello compatibility Date: Fri, 21 Feb 2025 18:03:41 +0000 Message-ID: <20250221180349.1413089-3-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_100401_669162_3A6CBA8C X-CRM114-Status: GOOD ( 13.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add compatibility to Arm Morello System Development Platform. Note: Morello is at the same time the name of an Architecture [1], an SoC [2] and a Board [2]. To distinguish in between Architecture/SoC and Board we refer to the first as arm,morello and to the second as arm,morello-sdp. [1] https://developer.arm.com/Architectures/Morello [2] https://www.morello-project.org/ Acked-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino --- .../devicetree/bindings/arm/arm,morello.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,morello.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,morello.yaml b/Documentation/devicetree/bindings/arm/arm,morello.yaml new file mode 100644 index 000000000000..b4cfa8d048c4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,morello.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,morello.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Morello Platforms + +maintainers: + - Vincenzo Frascino + +description: |+ + The Morello architecture is an experimental extension to Armv8.2-A, + which extends the AArch64 state with the principles proposed in + version 7 of the Capability Hardware Enhanced RISC Instructions + (CHERI) ISA. + + ARM's Morello Platforms are built as a research project to explore + capability architectures based on arm. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Arm Morello System Development Platform + items: + - const: arm,morello-sdp + - const: arm,morello + +additionalProperties: true + +... From patchwork Fri Feb 21 18:03:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincenzo Frascino X-Patchwork-Id: 13986136 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3D11C021B5 for ; Fri, 21 Feb 2025 18:10:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+PVIbNkaQDavQEgjBDli++CwOPMV7IlcwfOvzQNao20=; b=tCfwO6GAYIJk+8afQwNEhHA0c8 ZPKokbVwS1gHXxdYG69okWoRxU6AykmevIrdmYFY8lu3HODT5bu8S2TmXGWD4r08bDtPRD8Mkgizr Tpk+eTaDkg9fJigwcXwI6U4Iz+p18Sk/C42LEEFzUnAfMBZcv89+31QUHKEOO1hrR5Xm+cTE9eAbW VSLVHiOVnZsSEy8FMuYRHC2bSr1v+ObQJVnomF1tgGpH4dZ9PsuEDp2rxqJI937MB2/2rhYODQZ4l JawDT3ekwbvKiO5e97YT3umfWtxD5mJzFVJouzdU3x80xii610PVkimjZYjuzR988Gl5Se5SN5dG1 DEGZdWBQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXTb-00000006TbF-3wee; Fri, 21 Feb 2025 18:10:15 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXNc-00000006SDp-1Inw for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 18:04:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 607D61CC4; Fri, 21 Feb 2025 10:04:21 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8CB503F59E; Fri, 21 Feb 2025 10:04:01 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 03/10] dt-bindings: arm: Add Morello fvp compatibility Date: Fri, 21 Feb 2025 18:03:42 +0000 Message-ID: <20250221180349.1413089-4-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_100404_388626_4521CDA5 X-CRM114-Status: UNSURE ( 8.21 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add compatibility to Arm Morello Fixed Virtual Platform. Signed-off-by: Vincenzo Frascino --- Documentation/devicetree/bindings/arm/arm,morello.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/arm,morello.yaml b/Documentation/devicetree/bindings/arm/arm,morello.yaml index b4cfa8d048c4..e843b97fa485 100644 --- a/Documentation/devicetree/bindings/arm/arm,morello.yaml +++ b/Documentation/devicetree/bindings/arm/arm,morello.yaml @@ -23,9 +23,11 @@ properties: const: '/' compatible: oneOf: - - description: Arm Morello System Development Platform + - description: Arm Morello System Platforms items: - - const: arm,morello-sdp + - enum: + - arm,morello-sdp + - arm,morello-fvp - const: arm,morello additionalProperties: true From patchwork Fri Feb 21 18:03:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincenzo Frascino X-Patchwork-Id: 13986137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 220E1C021B3 for ; Fri, 21 Feb 2025 18:11:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=A7x6pXw5SnTSriLo3V1nB/w4JouDq5CticQaXUaH3P0=; b=gnsokiguzkoJOtJsN0kT5YxZlj mXAooHt4fv/7upiPRhuQ8hfrkwSGy+EtAiBhhf005OouYkRkcdbl+qb7nLGwCgpBjI/pL5EIiKdHp 20yL49292kgUOZ3xjPKUUp6gpp1ag7+2836/DHMhu/zYH6OC6Q6m83QrU3fSCJp0idO0ac7dAIJA6 5CnKiS3C65yC5GzWVx/R/uAMDV2kxdYTmEL6/TYkaLuHY9HBdViNdubtYc/wWxAHChXFBB7UFVbHQ tWI3Bj/lobOpB5Q2GygaqSiA3cIkKJQTsq7NDLC4AQ6XDQyOSCq4LCtXp1CdMdt94OiDslNMpJJ/3 0knA0azg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXV4-00000006TzS-2PdL; Fri, 21 Feb 2025 18:11:46 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXNe-00000006SED-2LLL for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 18:04:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E80B7169C; Fri, 21 Feb 2025 10:04:23 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F41C23F59E; Fri, 21 Feb 2025 10:04:03 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke , Krzysztof Kozlowski Subject: [PATCH v7 04/10] dt-bindings: arm: Add Rainier compatibility Date: Fri, 21 Feb 2025 18:03:43 +0000 Message-ID: <20250221180349.1413089-5-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_100406_630906_7A87EB57 X-CRM114-Status: UNSURE ( 7.91 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Arm Morello System Development Platform uses Rainier CPUs. Add compatibility to Rainier. Acked-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 73dd73d2d4fa..2e666b2a4dcd 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -177,6 +177,7 @@ properties: - arm,neoverse-v2 - arm,neoverse-v3 - arm,neoverse-v3ae + - arm,rainier - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan From patchwork Fri Feb 21 18:03:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincenzo Frascino X-Patchwork-Id: 13986138 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F00EC021B3 for ; Fri, 21 Feb 2025 18:13:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=NwOnW5qs6gscsRlBsH4OtJZW+V6EMyK8yYs+Hq3CEsQ=; b=HvgL8ro4byzHSWjLoVpUarKwM9 N3vWknoUEsJ5QZbU0sylAqYSKbdkbzQAKCl3ELL9asCo7QSZnxIRJhiHmzHDY4puOUEiISLSvhe83 oETMtLvxm8CMvkydO10w+/SFPVwF+m++wZupb5/aM3V0RFnwSXhAIPM7AFD0WsDaelkI8cB5pc2Kz we4c1T+yRZZ/M7vOMVrzN2LvzCfZBBSNCjPUKQshYVpp/7Y3x+eTMUPrafPhzQXYwsOFWAUfpmESc rc4Df+L+oIREu4R5rbdjM4O7dCNcTJGRt+s01hXtN031cFnvViAkrRgP2J2U3fzj8W3lZ4qENtDnm 7ANR6HLw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXWV-00000006UJP-0tv7; Fri, 21 Feb 2025 18:13:15 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXNh-00000006SEp-0U1b for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 18:04:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 817811CC4; Fri, 21 Feb 2025 10:04:26 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 87C3D3F59E; Fri, 21 Feb 2025 10:04:06 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke , Krzysztof Kozlowski Subject: [PATCH v7 05/10] dt-bindings: arm-pmu: Add support for ARM Rainier PMU Date: Fri, 21 Feb 2025 18:03:44 +0000 Message-ID: <20250221180349.1413089-6-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_100409_191485_9ED2B9E8 X-CRM114-Status: UNSURE ( 8.59 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for the ARM Rainier CPU core PMU. Acked-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino --- Documentation/devicetree/bindings/arm/pmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index a148ff54f2b8..295963a3cae7 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -67,6 +67,7 @@ properties: - arm,neoverse-v2-pmu - arm,neoverse-v3-pmu - arm,neoverse-v3ae-pmu + - arm,rainier-pmu - brcm,vulcan-pmu - cavium,thunder-pmu - nvidia,denver-pmu From patchwork Fri Feb 21 18:03:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincenzo Frascino X-Patchwork-Id: 13986139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E61B7C021B5 for ; Fri, 21 Feb 2025 18:14:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=5m1RuY+RQqkMNIBFAigrCxI4TYa5mNvA2VrOSqkPxXM=; b=OiKWqYD+zV+J7v0BDuZ8GMx64w H7K7gx0+bB6fIHQKdbfC+zdljzwR8Nm037eE4pS9FZ8p3Ika0xvaCPXwC8WRpOWzN6EubR736hgyP Cobg8vSS0i8LZ2UjaPiO53uxADOqFT68CHuFSWKvdhw66dnBtEP/S5aoDKrjSQ128Dmswkzug7SjN Ey6XSDtCBhiJjUN6FNkSwyUPDdAEEQDmpQzXuLc/Rb1Xh9Ntv8W3JQwEQjDvPFlKopkim1vRMzCt1 hmiNiIo0+M93zYC0cIzwVyk5jhWHEtPKa4DWF5sVFp0tML7hV9D9CIQTDUGW8U8EUEuhkWf7aafz8 ZlZHErRA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXXw-00000006UaG-3YwX; Fri, 21 Feb 2025 18:14:44 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXNj-00000006SFS-49ED for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 18:04:13 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E37EC169C; Fri, 21 Feb 2025 10:04:28 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A6A63F59E; Fri, 21 Feb 2025 10:04:08 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 06/10] perf: arm_pmuv3: Add support for ARM Rainier PMU Date: Fri, 21 Feb 2025 18:03:45 +0000 Message-ID: <20250221180349.1413089-7-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_100412_096939_67D007B3 X-CRM114-Status: UNSURE ( 9.66 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for the ARM Rainier CPU core PMU. Signed-off-by: Vincenzo Frascino --- drivers/perf/arm_pmuv3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 0e360feb3432..3785522a08e7 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -1369,6 +1369,7 @@ PMUV3_INIT_SIMPLE(armv8_neoverse_v1) PMUV3_INIT_SIMPLE(armv8_neoverse_v2) PMUV3_INIT_SIMPLE(armv8_neoverse_v3) PMUV3_INIT_SIMPLE(armv8_neoverse_v3ae) +PMUV3_INIT_SIMPLE(armv8_rainier) PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) PMUV3_INIT_SIMPLE(armv8_nvidia_denver) @@ -1416,6 +1417,7 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible = "arm,neoverse-v2-pmu", .data = armv8_neoverse_v2_pmu_init}, {.compatible = "arm,neoverse-v3-pmu", .data = armv8_neoverse_v3_pmu_init}, {.compatible = "arm,neoverse-v3ae-pmu", .data = armv8_neoverse_v3ae_pmu_init}, + {.compatible = "arm,rainier-pmu", .data = armv8_rainier_pmu_init}, {.compatible = "cavium,thunder-pmu", .data = armv8_cavium_thunder_pmu_init}, {.compatible = "brcm,vulcan-pmu", .data = armv8_brcm_vulcan_pmu_init}, {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init}, From patchwork Fri Feb 21 18:03:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincenzo Frascino X-Patchwork-Id: 13986141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7562AC021B3 for ; Fri, 21 Feb 2025 18:16:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=D5nSxae3xoqtY2iUn5V2O6+pbBfVh+LtbC0RBPkTHT4=; b=o+skonLOKy1cUkV0xtqX5HJisV eD2KTlPl6GYXSi44+4rW5sArtwoPR8DhqtRcxVaVC/d35YclZxJXInoIOOoO92+Z3ca+UP1y3yd2Z cOiqc0cUhcXxig8s0lnznGL5PCPTE9WZsTxPre+QocsF8ZAiA9F62UHzJBBpJZ/GyhbhnaCzthkSy 5Vi7d3IOVAcgNsBB9arlyLRJQ/rZDoP9/WKBICFtItzZGzL/l21ALw3rLkGBj2wOwkITCDBPnZozD GhMeAApIQugzpFz7W/YDqIFMtN5C00pVtHpyCi3IMm40SqH3KcjsRQvXUd4vtdxkxS2BQyodhbUlv REkid0gg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXZO-00000006UoV-2JAp; Fri, 21 Feb 2025 18:16:14 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXNm-00000006SGI-162X for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 18:04:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 59231169C; Fri, 21 Feb 2025 10:04:31 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 839023F59E; Fri, 21 Feb 2025 10:04:11 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 07/10] arm64: dts: morello: Add support for common functionalities Date: Fri, 21 Feb 2025 18:03:46 +0000 Message-ID: <20250221180349.1413089-8-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_100414_378251_B3813520 X-CRM114-Status: GOOD ( 12.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share some functionalities that have conveniently been included in morello.dtsi to avoid duplication. Introduce morello.dtsi. Note: Morello fvp will be introduced with a future patch series. Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/morello.dtsi | 323 +++++++++++++++++++++++++++ 1 file changed, 323 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi new file mode 100644 index 000000000000..e35e5e482720 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + */ + +#include + +/ { + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + + soc_refclk50mhz: clock-50000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "apb_pclk"; + }; + + soc_refclk85mhz: clock-85000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <85000000>; + clock-output-names = "iofpga:aclk"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,rainier"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_0>; + clocks = <&scmi_dvfs 0>; + + l2_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-size = <0x100000>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + compatible = "arm,rainier"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_1>; + clocks = <&scmi_dvfs 0>; + + l2_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu2: cpu@10000 { + compatible = "arm,rainier"; + reg = <0x0 0x10000>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_2>; + clocks = <&scmi_dvfs 1>; + + l2_2: l2-cache-2 { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu3: cpu@10100 { + compatible = "arm,rainier"; + reg = <0x0 0x10100>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_3>; + clocks = <&scmi_dvfs 1>; + + l2_3: l2-cache-3 { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + }; + + firmware { + interrupt-parent = <&gic>; + + scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 1 0>, <&mailbox 1 1>; + shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + device_type = "memory"; + /* [0x80000000-0xffffffff] */ + reg = <0x00000000 0x80000000 0x0 0x7f000000>; + }; + + memory@8080000000 { + device_type = "memory"; + /* [0x8080000000-0x83f7ffffff] */ + reg = <0x00000080 0x80000000 0x3 0x78000000>; + }; + + pmu { + compatible = "arm,rainier-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-firmware@ff000000 { + reg = <0x0 0xff000000 0x0 0x01000000>; + no-map; + }; + }; + + spe-pmu { + compatible = "arm,statistical-profiling-extension-v1"; + interrupts = ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + ranges; + + uart0: serial@2a400000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2a400000 0x0 0x1000>; + interrupts = ; + clocks = <&soc_refclk50mhz>, <&soc_refclk50mhz>; + clock-names = "uartclk", "apb_pclk"; + + status = "disabled"; + }; + + gic: interrupt-controller@2c010000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x30000000 0x0 0x10000>, /* GICD */ + <0x0 0x300c0000 0x0 0x80000>; /* GICR */ + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its1: msi-controller@30040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30040000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + + its2: msi-controller@30060000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30060000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + + its_ccix: msi-controller@30080000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30080000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + + its_pcie: msi-controller@300a0000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x300a0000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + smmu_dp: iommu@2ce00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x2ce00000 0x0 0x40000>; + + interrupts = , + , + ; + interrupt-names = "eventq", "gerror", "cmdq-sync"; + #iommu-cells = <1>; + }; + + mailbox: mhu@45000000 { + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0x0 0x45000000 0x0 0x1000>; + + interrupts = , + ; + #mbox-cells = <2>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + }; + + sram: sram@45200000 { + compatible = "mmio-sram"; + reg = <0x0 0x06000000 0x0 0x8000>; + ranges = <0 0x0 0x06000000 0x8000>; + + #address-cells = <1>; + #size-cells = <1>; + + cpu_scp_hpri0: scp-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + cpu_scp_hpri1: scp-sram@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From patchwork Fri Feb 21 18:03:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincenzo Frascino X-Patchwork-Id: 13986142 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55BBEC021B5 for ; Fri, 21 Feb 2025 18:17:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Fri, 21 Feb 2025 10:04:13 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 08/10] arm64: dts: morello: Add support for soc dts Date: Fri, 21 Feb 2025 18:03:47 +0000 Message-ID: <20250221180349.1413089-9-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_100416_485064_BDF67265 X-CRM114-Status: GOOD ( 15.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello SoC dts. Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/morello-sdp.dts | 157 ++++++++++++++++++++++++ 2 files changed, 158 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello-sdp.dts diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index d908e96d7ddc..869667bef7c0 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/arm/morello-sdp.dts new file mode 100644 index 000000000000..cee49dee7571 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-sdp.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model = "Arm Morello System Development Platform"; + compatible = "arm,morello-sdp", "arm,morello"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dpu_aclk: clock-350000000 { + /* 77.1 MHz derived from 24 MHz reference clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <350000000>; + clock-output-names = "aclk"; + }; + + dpu_pixel_clk: clock-148500000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + clock-output-names = "pxclk"; + }; + + i2c0: i2c@1c0f0000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x1c0f0000 0x0 0x1000>; + interrupts = ; + clocks = <&dpu_aclk>; + + #address-cells = <1>; + #size-cells = <0>; + + clock-frequency = <100000>; + + hdmi_tx: hdmi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + video-ports = <0x234501>; + port { + tda998x_0_input: endpoint { + remote-endpoint = <&dp_pl0_out0>; + }; + }; + }; + }; + + dp0: display@2cc00000 { + compatible = "arm,mali-d32", "arm,mali-d71"; + reg = <0x0 0x2cc00000 0x0 0x20000>; + interrupts = <0 69 4>; + clocks = <&dpu_aclk>; + clock-names = "aclk"; + iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, + <&smmu_dp 8>; + + #address-cells = <1>; + #size-cells = <0>; + + pl0: pipeline@0 { + reg = <0>; + clocks = <&dpu_pixel_clk>; + clock-names = "pxclk"; + port { + dp_pl0_out0: endpoint { + remote-endpoint = <&tda998x_0_input>; + }; + }; + }; + }; + + smmu_ccix: iommu@4f000000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x4f000000 0x0 0x40000>; + + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent = <&its1 0>; + #iommu-cells = <1>; + dma-coherent; + }; + + smmu_pcie: iommu@4f400000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x4f400000 0x0 0x40000>; + + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent = <&its2 0>; + #iommu-cells = <1>; + dma-coherent; + }; + + pcie_ctlr: pcie@28c0000000 { + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + reg = <0x28 0xC0000000 0 0x10000000>; + ranges = <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>, + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>, + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>; + bus-range = <0 255>; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; + msi-map = <0 &its_pcie 0 0x10000>; + iommu-map = <0 &smmu_pcie 0 0x10000>; + }; + + ccix_pcie_ctlr: pcie@4fc0000000 { + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + reg = <0x4f 0xC0000000 0 0x10000000>; + ranges = <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>, + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>, + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; + msi-map = <0 &its_ccix 0 0x10000>; + iommu-map = <0 &smmu_ccix 0 0x10000>; + }; +}; + +&uart0 { + status = "okay"; +}; From patchwork Fri Feb 21 18:03:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincenzo Frascino X-Patchwork-Id: 13986143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF578C021B5 for ; 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Fri, 21 Feb 2025 18:19:13 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXNq-00000006SHK-3W4Q for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 18:04:19 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 371F2169C; Fri, 21 Feb 2025 10:04:36 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6147C3F59E; Fri, 21 Feb 2025 10:04:16 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke Subject: [PATCH v7 09/10] arm64: dts: morello: Add support for fvp dts Date: Fri, 21 Feb 2025 18:03:48 +0000 Message-ID: <20250221180349.1413089-10-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_100418_956572_92C03204 X-CRM114-Status: GOOD ( 14.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello fvp dts. Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/Makefile | 2 +- arch/arm64/boot/dts/arm/morello-fvp.dts | 77 +++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/arm/morello-fvp.dts diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 869667bef7c0..f30ee045dc95 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,4 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/arm/morello-fvp.dts new file mode 100644 index 000000000000..2072c0b72325 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-fvp.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model = "Arm Morello Fixed Virtual Platform"; + compatible = "arm,morello-fvp", "arm,morello"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + bp_refclock24mhz: clock-24000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "bp:clock24mhz"; + }; + + block_0: virtio_block@1c170000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c170000 0x0 0x200>; + interrupts = ; + }; + + net_0: virtio_net@1c180000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c180000 0x0 0x200>; + interrupts = ; + }; + + rng_0: virtio_rng@1c190000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c190000 0x0 0x200>; + interrupts = ; + }; + + p9_0: virtio_p9@1c1a0000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c1a0000 0x0 0x200>; + interrupts = ; + }; + + kmi_0: kmi@1c150000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c150000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi_1: kmi@1c160000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c160000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + eth_0: ethernet@1d100000 { + compatible = "smsc,lan91c111"; + reg = <0x0 0x1d100000 0x0 0x10000>; + interrupts = ; + }; +}; + +&uart0 { + status = "okay"; +}; From patchwork Fri Feb 21 18:03:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincenzo Frascino X-Patchwork-Id: 13986144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1F5BC021B5 for ; Fri, 21 Feb 2025 18:20:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=0s1kvNRUu/hh2eqpKf7+3TQzwwwN4GvUxCCvW+yaCFU=; b=NaOFAm2ApeGFdkyPrfVZPRiDvX RBW1reTQaePg7cCgtbvxO6suIaz74Ep6sK6vGCohR3SE4ZugmnPcOeaXI9fPbuojpMHO+fefmmrhm Gubd1BMocLh6Xz8PCTxhKzlmRlbb7snwMetOWjragi/6h+uuJ0ubPQ2ubncMa+k1XX/yDabGY1v27 RrYWvyJKP35t5V6Cy3KwRsEWwyhhGo25BC5RJPqFqA87PaKSiTX+CtQ6+ud8ZFoFA+zqRePJJs7rK zYpAFKum3stu6iG/NF31kaFScVhvod3CCV7tGEjtRI36AqtMiro2tDoIZ7ehiNPY/h1TJRFqcnAZ7 /v71lr8w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXdj-00000006VNl-243q; Fri, 21 Feb 2025 18:20:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlXNt-00000006SIJ-1YHO for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 18:04:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BDEB41CC4; Fri, 21 Feb 2025 10:04:38 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CA64E3F59E; Fri, 21 Feb 2025 10:04:18 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Jessica Clarke , Krzysztof Kozlowski Subject: [PATCH v7 10/10] MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer Date: Fri, 21 Feb 2025 18:03:49 +0000 Message-ID: <20250221180349.1413089-11-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250221180349.1413089-1-vincenzo.frascino@arm.com> References: <20250221180349.1413089-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_100421_451837_B65FC4B8 X-CRM114-Status: UNSURE ( 8.06 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add Vincenzo Frascino as Arm Morello Software Development Platform Maintainer. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3864d473f52f..6aaef2286de8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2750,6 +2750,13 @@ F: arch/arm/boot/dts/socionext/milbeaut* F: arch/arm/mach-milbeaut/ N: milbeaut +ARM/MORELLO PLATFORM +M: Vincenzo Frascino +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/arm/arm,morello.yaml +F: arch/arm64/boot/dts/arm/morello* + ARM/MOXA ART SOC M: Krzysztof Kozlowski L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)