From patchwork Sat Feb 22 10:43:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13986586 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D31B1FBE9B; Sat, 22 Feb 2025 10:44:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740221058; cv=none; b=lRMwWp7Ht16UZhhFde4ejtUhs1AvgoM31lkGGKTrVIZB6GLFD9cKByWiTPOyRuCnwq6/WyrIw1bz6K+yXwgr6gAZbovoryozc6AnDwvM6/7b1AlPm/vuE3FPOs5vJUfjMnEjK2ObLI4k7Ij55Z/b8AIGq/dZiuR/LSyCrwasGQI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740221058; c=relaxed/simple; bh=1bxj/vC/QXDveDO1JYH8sC0FYLsbB1P5VxpEt6u4zPo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XUb1zr0oN8OhS3wGGFgWB3pSMEcgbWsP+/ytjMk+wh9/GhorAYkPah6gPZzlJ2fSqfSt1Wk/1UTuObB1uZw4crRP41b10ay7QYUrq0CyCw/R0k9PzQWWlhr53wPtde10o6Qju4zohp/lfjYJmGg5UWS0MPlYzV9oSTK7fUa/fgU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p5QP8NYF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p5QP8NYF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 49DF6C4CED1; Sat, 22 Feb 2025 10:44:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740221057; bh=1bxj/vC/QXDveDO1JYH8sC0FYLsbB1P5VxpEt6u4zPo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=p5QP8NYFIakX0saiNsA2sXR2CLO+44f61vUls0TBRjZ5wAFYtr6F/ztSg9l7h3y2X +YSt+U71JsgDZ+OZAbNm4derxPT/wpDfxh6TlYKHfzmFa9n/eX5qG56JApMqBRFmky 1BKmflSIOuOnBdH2gZz4leohx4KsZ90rd2MAgTCRY+ZPx/SGG5nasQi47kV5jxbyhe WgKwq8GEkOqVjxDhohV9bWxd+9xszKRiIEHl4kzQW4GMo7S6aAwQEwnaxoC145awui 3Ven1ekPNBpmIlVfAOTmrvU6PFxav7YCW3O/tLs87d0C0Ocb72LiyAwG4CIE5lqraL RLdDYUsEX87/g== From: Lorenzo Bianconi Date: Sat, 22 Feb 2025 11:43:44 +0100 Subject: [PATCH v3 1/2] dt-bindings: PCI: mediatek-gen3: Add mediatek,pbus-csr phandle array property Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250222-en7581-pcie-pbus-csr-v3-1-e0cca1f4d394@kernel.org> References: <20250222-en7581-pcie-pbus-csr-v3-0-e0cca1f4d394@kernel.org> In-Reply-To: <20250222-en7581-pcie-pbus-csr-v3-0-e0cca1f4d394@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Lorenzo Bianconi Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= X-Mailer: b4 0.14.2 Introduce the mediatek,pbus-csr property for the pbus-csr syscon node available on EN7581 SoC. The airoha pbus-csr block provides a configuration interface for the PBUS controller used to detect if a given address is accessible on PCIe controller. Signed-off-by: Lorenzo Bianconi --- .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index f05aab2b1addcac91d4685d7d94f421814822b92..162406e0691a81044406aa8f9e60605d0d917811 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -109,6 +109,17 @@ properties: power-domains: maxItems: 1 + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + '#interrupt-cells': const: 1 @@ -168,6 +179,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: @@ -197,6 +210,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: @@ -224,6 +239,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: From patchwork Sat Feb 22 10:43:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13986587 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D182D1FBE9B; Sat, 22 Feb 2025 10:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740221060; cv=none; b=HJz9cifn1xrzKr3QgCqs0M/jMiF4Sgz62nikBBo2PfxwQBMEQ3/GRPrVk6k5kNSnhjm+5hIu6bhBjGpAE95l0kyUrbH2y4zoXXOtPqXCOB268WlkdidSb4IjKx/htzUQEtu5g8jj5TM4+T9eIPxykf7XCRjH4EaG7lO+rLFEzGc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740221060; c=relaxed/simple; bh=KklBsnKcVFSuYBzhg3x4RUn9m/fVl0ZPRbgJvxFW3Kg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eLddnZnaWIjnQkbrBxB8iMdnc08VvaEjKxzWcCGUZPT4QctTpOLg/LUSQ+KGfznDTSn8vT476kQEV4jp50yIJUGddhsAsJ5tmOcyo9tU+dJ3JNHUf43EAwzfl/WKwG/zUCpQFL7YsuenRijvqfXmwmTZtvbupzH1nC95V2e8aBQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TAWwjkpd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TAWwjkpd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EF059C4CEE6; Sat, 22 Feb 2025 10:44:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740221060; bh=KklBsnKcVFSuYBzhg3x4RUn9m/fVl0ZPRbgJvxFW3Kg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TAWwjkpd+5cFg6+zzP9oLs1xn1rF2z5+dbD0nvnQlS8YjnyJWHp+/gQ+4ueZrNcX+ V0O8iEW/VgTO8jrhysPvVMFU7IRTf8vApyrqogJRYxD04B55UpF/q1OQbTYv4Uzeyr Y+46wNkZA8wPM+Df41iCJz/K6YVexwN3W47XLGYlC8ufvCexlmHXozu9VGPZsixfq6 tcvJNg2ATFeFuDPq/AU2abj3/aSJqLFBZYdO32ryolKyfrUqJjCF1bRvSlmKcxK3mR wllzj44pFCV6bMynfX6RT5XkQgByYhYo1surtZDfu7wWaqxxm9HCGRaHu2cAThwwy1 OL9xpO93NtnOg== From: Lorenzo Bianconi Date: Sat, 22 Feb 2025 11:43:45 +0100 Subject: [PATCH v3 2/2] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581 SoC Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250222-en7581-pcie-pbus-csr-v3-2-e0cca1f4d394@kernel.org> References: <20250222-en7581-pcie-pbus-csr-v3-0-e0cca1f4d394@kernel.org> In-Reply-To: <20250222-en7581-pcie-pbus-csr-v3-0-e0cca1f4d394@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Lorenzo Bianconi Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= X-Mailer: b4 0.14.2 Configure PBus base address and address mask to allow the hw to detect if a given address is accessible on PCIe controller. Fixes: f6ab898356dd ("PCI: mediatek-gen3: Add Airoha EN7581 support") Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 34 ++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 0f64e76e2111468e6a453889ead7fbc75804faf7..51103b7624c09ca957c22a25536dc9da25428e48 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -930,9 +932,13 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) { + struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); struct device *dev = pcie->dev; + struct resource_entry *entry; + u32 val, args[2], size, mask; + struct regmap *pbus_regmap; + resource_size_t addr; int err; - u32 val; /* * The controller may have been left out of reset by the bootloader @@ -944,6 +950,32 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) /* Wait for the time needed to complete the reset lines assert. */ msleep(PCIE_EN7581_RESET_TIME_MS); + /* + * Configure PBus base address and base address mask to allow the + * hw to detect if a given address is accessible on PCIe controller. + */ + pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, + "mediatek,pbus-csr", + ARRAY_SIZE(args), + args); + if (IS_ERR(pbus_regmap)) + return PTR_ERR(pbus_regmap); + + entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (!entry) + return -EINVAL; + + addr = entry->res->start - entry->offset; + err = regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); + if (err) + return err; + + size = lower_32_bits(resource_size(entry->res)); + mask = size ? GENMASK(31, __fls(size)) : 0; + err = regmap_write(pbus_regmap, args[1], mask); + if (err) + return err; + /* * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 * requires PHY initialization and power-on before PHY reset deassert.