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cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250221132021epsmtip27b96bcc645abda7a5dbb604b12c1bd58~mO8SYgc580769307693epsmtip2I; Fri, 21 Feb 2025 13:20:21 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, Jonathan.Cameron@Huawei.com, fan.ni@samsung.com, nifan.cxl@gmail.com, a.manzanares@samsung.com, pankaj.dubey@samsung.com, cassel@kernel.org, 18255117159@163.com, xueshuai@linux.alibaba.com, renyu.zj@linux.alibaba.com, will@kernel.org, mark.rutland@arm.com, Shradha Todi Subject: [PATCH v7 1/5] perf/dwc_pcie: Move common DWC struct definitions to 'pcie-dwc.h' Date: Fri, 21 Feb 2025 18:45:44 +0530 Message-Id: <20250221131548.59616-2-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 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(BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250222_025857_811927_256D6CB0 X-CRM114-Status: GOOD ( 24.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Manivannan Sadhasivam Since these are common to all Desginware PCIe IPs, move them to a new header 'pcie-dwc.h', so that other drivers like debugfs, perf and sysfs could make use of them. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Shradha Todi --- MAINTAINERS | 1 + drivers/perf/dwc_pcie_pmu.c | 25 +++---------------------- include/linux/pcie-dwc.h | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+), 22 deletions(-) create mode 100644 include/linux/pcie-dwc.h diff --git a/MAINTAINERS b/MAINTAINERS index 3864d473f52f..6474a2d83de4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18167,6 +18167,7 @@ S: Maintained F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml F: drivers/pci/controller/dwc/*designware* +F: include/linux/pcie-dwc.h PCI DRIVER FOR TI DRA7XX/J721E M: Vignesh Raghavendra diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c index cccecae9823f..da30f2c2d674 100644 --- a/drivers/perf/dwc_pcie_pmu.c +++ b/drivers/perf/dwc_pcie_pmu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -99,26 +100,6 @@ struct dwc_pcie_dev_info { struct list_head dev_node; }; -struct dwc_pcie_pmu_vsec_id { - u16 vendor_id; - u16 vsec_id; - u8 vsec_rev; -}; - -/* - * VSEC IDs are allocated by the vendor, so a given ID may mean different - * things to different vendors. See PCIe r6.0, sec 7.9.5.2. - */ -static const struct dwc_pcie_pmu_vsec_id dwc_pcie_pmu_vsec_ids[] = { - { .vendor_id = PCI_VENDOR_ID_ALIBABA, - .vsec_id = 0x02, .vsec_rev = 0x4 }, - { .vendor_id = PCI_VENDOR_ID_AMPERE, - .vsec_id = 0x02, .vsec_rev = 0x4 }, - { .vendor_id = PCI_VENDOR_ID_QCOM, - .vsec_id = 0x02, .vsec_rev = 0x4 }, - {} /* terminator */ -}; - static ssize_t cpumask_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -529,14 +510,14 @@ static void dwc_pcie_unregister_pmu(void *data) static u16 dwc_pcie_des_cap(struct pci_dev *pdev) { - const struct dwc_pcie_pmu_vsec_id *vid; + const struct dwc_pcie_vsec_id *vid; u16 vsec; u32 val; if (!pci_is_pcie(pdev) || !(pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)) return 0; - for (vid = dwc_pcie_pmu_vsec_ids; vid->vendor_id; vid++) { + for (vid = dwc_pcie_rasdes_vsec_ids; vid->vendor_id; vid++) { vsec = pci_find_vsec_capability(pdev, vid->vendor_id, vid->vsec_id); if (vsec) { diff --git a/include/linux/pcie-dwc.h b/include/linux/pcie-dwc.h new file mode 100644 index 000000000000..40f3545731c8 --- /dev/null +++ b/include/linux/pcie-dwc.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021-2023 Alibaba Inc. + * + * Copyright 2025 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#ifndef LINUX_PCIE_DWC_H +#define LINUX_PCIE_DWC_H + +#include + +struct dwc_pcie_vsec_id { + u16 vendor_id; + u16 vsec_id; + u8 vsec_rev; +}; + +/* + * VSEC IDs are allocated by the vendor, so a given ID may mean different + * things to different vendors. See PCIe r6.0, sec 7.9.5.2. + */ +static const struct dwc_pcie_vsec_id dwc_pcie_rasdes_vsec_ids[] = { + { .vendor_id = PCI_VENDOR_ID_ALIBABA, + .vsec_id = 0x02, .vsec_rev = 0x4 }, + { .vendor_id = PCI_VENDOR_ID_AMPERE, + .vsec_id = 0x02, .vsec_rev = 0x4 }, + { .vendor_id = PCI_VENDOR_ID_QCOM, + .vsec_id = 0x02, .vsec_rev = 0x4 }, + {} /* terminator */ +}; + +#endif /* LINUX_PCIE_DWC_H */ From patchwork Fri Feb 21 13:15:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13986602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05349C021B2 for ; Sat, 22 Feb 2025 11:05:38 +0000 (UTC) DKIM-Signature: v=1; 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Fri, 21 Feb 2025 13:20:25 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, Jonathan.Cameron@Huawei.com, fan.ni@samsung.com, nifan.cxl@gmail.com, a.manzanares@samsung.com, pankaj.dubey@samsung.com, cassel@kernel.org, 18255117159@163.com, xueshuai@linux.alibaba.com, renyu.zj@linux.alibaba.com, will@kernel.org, mark.rutland@arm.com, Shradha Todi Subject: [PATCH v7 2/5] PCI: dwc: Add helper to find the Vendor Specific Extended Capability (VSEC) Date: Fri, 21 Feb 2025 18:45:45 +0530 Message-Id: <20250221131548.59616-3-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250221131548.59616-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTf0xbVRTHc/v62kKAvHSMXWrY4BGj1MAolHrLQImS7WWQjYjRhM2wZ3kW 1tLWtjglMeNHYYPJDxmMOVk3GJNSOjAtIGWMVSCbAcFNGnQIywaIIkHmVhYXYFraov997jnf k+85597Lw/jfcQS8PJWe0apoJcnxZ/cOR70U/ec1uzy28nkccp5a56LG4QjUWpKLbtWaMFTS MYsjk+sLLjI3T3FQ0WfrOLLOT+Fosr+Jg8aNtznI2dPJRoYNAxvNGipwdPWnuyy02XsDoJYe Fxc1ly4B9M9AHxdVDX+KDDMJaPWZjZMSQl0x1eOUxWgBlP3CLJe6bC2gDCMrOGU1V3ComakB DmV/KKUWnI0sytZ6kqruNgPqiXV3RkCWIimXoXMYbTijkqlz8lTyZDItM/vN7ARJrChaJEWv kuEqOp9JJlPTM6L35ynd05LhH9HKAncog9bpyL2vJWnVBXomPFet0yeTjCZHqRFrYnR0vq5A JY9RMfpEUWxsXIJbeEyRO1v+O65ZJj7+dWgTFIHioErgx4OEGP447sQrgT+PT1wH8M5kB8t7 eAygpajdl3kK4M8bE9h2yfTNcz7VDQCXztaBrQSfcAFouJ+6xRxCCIvXKj0FwUQZgCOLIVsF GNGLQYfJ5EnsIBg4M3edvcVs4kX4zf1RDwcSifDcsy6W120P7Pja4dH7EfugeaLR4wyJBzzo MjfhXlEqrKv6G3h5B/zjdjfXywK4VFPuYzlst533jaCET22tPoPXocPZ5DbmubuLgl39e73h MNgw2umRYEQQrFpf8MkDYZ9xmyOha3OA7eVQaLw16WuHgqvOasy7oWoAZ+ubsFqw+8L/FpcB MINQRqPLlzO6BE2cijnx37XJ1PlW4HnSwoN94OGDRzFDgMUDQwDyMDI4MFrfJ+cH5tCfFDJa dba2QMnohkCCe4GfY4KdMrX7T6j02SKxNFYskUjE0niJiNwVWGo3yPmEnNYzCobRMNrtOhbP T1DE8l/5wCQ8VLxngXvgr/RdS8vxwn6uZfpe2vTxaqUx0fKWhrZNBQgDghQRLVd/kIycWH6f g7uS6mqlgm/bjgz2nDGeFzYKsk5r9Iv9zMtR3dqwI/PjvPIrha7I0/cWhlJGBayytcR9l+Lm HJmvYHPHG9q/r886uUEojn3VQpkb09O0VsfERMtgWbc1uGHww/4zj0efvJfWPPbuO4eyyLdL VKfCpsfkl5QKaWTLyM21zBLoOFobUruIdh7lX/uSKXxjf1xN09gLlrOOyZrnlZNC2WFDjFl4 5+Iv811tbZ3k4dvFUWmlKTLxowMV9oyS3yIulstWrfiKoy/LbsuIDo2vu0uydbm0SIhpdfS/ P6S5kFsEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeLIzCtJLcpLzFFi42LZdlhJXndu7Y50g4brTBZX2n+zW0w/rGix pCnD4tiEFcwWTavvslqs+DKT3WLVwmtsFg09v1ktNj2+xmpxedccNouz846zWVzZuo7FouVP C4vF3ZZOVoul1y8yWfzdtpfRYtHWL+wWC5tfMlr837OD3aL3cK1Fyx1Ti/c/N7M5iHksXjGF 1WPNvDWMHjtn3WX3WLCp1KPlyFtWj02rOtk87lzbw+ax86Glx5Mr05k8Ni+p9+jbsorR4/Mm uQCeKC6blNSczLLUIn27BK6Mu20vWAteC1Q8PfSXsYGxka+LkZNDQsBE4tb+aUxdjFwcQgK7 GSW6ms6zQyQkJT5fXMcEYQtLrPz3nB2i6BOjxJbTr1lBEmwCWhKNX7uYQRIiAp2MEnuPvAOr YhY4xywx83MLI0iVsECyRPf0CWA2i4CqxPZ7p1hAbF4BK4lpP9dDrZCXWL3hADOIzSlgLbHq 3HSwuBBQzZ4t91knMPItYGRYxSiZWlCcm55bbFhgmJdarlecmFtcmpeul5yfu4kRHElamjsY t6/6oHeIkYmD8RCjBAezkgivbsmOdCHelMTKqtSi/Pii0pzU4kOM0hwsSuK84i96U4QE0hNL UrNTUwtSi2CyTBycUg1Mqp8bH0k/ZrlvFRWulzuPjelfnltjmPTv/Lyrrt2XbOaWiPP0h9+b 41fnZMfpvWz6D56EdP/CGUbrPFM+Hn3g9r3woOCSzPWNP6t/9Exw1Pv+rfnNh321vefZRS5K zRVbGrVp5VHXT4rKZRnHj79606xzflfD/261h0/kt3Id6pM9+iJ50xeL27HnVjSwpXUpZafJ aEq9yNY9UbHReDebVEnFo8N9NS5fxV6/3fl4SbqdoreCUfWc2heB/6M3FE95cjNL7PhCwYjU U2euqAgE6d/rZ5Z0M7tZW5nh5nM90/u3buA7Vl37khXV84JUtEJPL92yyTu+o2nZrwkKgZ/e HpuZcbTPfdN2qwOnn/QosRRnJBpqMRcVJwIAqOTWsBMDAAA= X-CMS-MailID: 20250221132029epcas5p1e56dd355e7ac912ceb25325595de0d24 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250221132029epcas5p1e56dd355e7ac912ceb25325595de0d24 References: <20250221131548.59616-1-shradha.t@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250222_025901_978711_9699AAFD X-CRM114-Status: GOOD ( 15.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org dw_pcie_find_vsec_capability() is used by upcoming DWC APIs to find the VSEC capabilities like PTM, RAS etc. Co-developed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pcie-designware.c | 40 ++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 145e7f579072..a7c0671c6715 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -283,6 +284,45 @@ u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) } EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); +static u16 __dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, + u16 vsec_id) +{ + u16 vsec = 0; + u32 header; + + if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) + return 0; + + while ((vsec = dw_pcie_find_next_ext_capability(pci, vsec, + PCI_EXT_CAP_ID_VNDR))) { + header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); + if (PCI_VNDR_HEADER_ID(header) == vsec_id) + return vsec; + } + + return 0; +} + +static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, + const struct dwc_pcie_vsec_id *vsec_ids) +{ + const struct dwc_pcie_vsec_id *vid; + u16 vsec; + u32 header; + + for (vid = vsec_ids; vid->vendor_id; vid++) { + vsec = __dw_pcie_find_vsec_capability(pci, vid->vendor_id, + vid->vsec_id); + if (vsec) { + header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); + if (PCI_VNDR_HEADER_REV(header) == vid->vsec_rev) + return vsec; + } + } + + return 0; +} + int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if (!IS_ALIGNED((uintptr_t)addr, size)) { From patchwork Fri Feb 21 13:15:46 2025 Content-Type: text/plain; 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Fri, 21 Feb 2025 13:20:35 +0000 (GMT) Received: from epsmgms1p2new.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250221132035epsmtrp1068507ee0e753fde911714b6ad54e3ad~mO8fVGF833121131211epsmtrp1k; Fri, 21 Feb 2025 13:20:35 +0000 (GMT) X-AuditID: b6c32a44-36bdd70000004cfe-24-67b9adf41b9f Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2new.samsung.com (Symantec Messaging Gateway) with SMTP id 80.3F.18949.3AD78B76; Fri, 21 Feb 2025 22:20:35 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250221132032epsmtip2990f5d7d3223c90064ce128a52b2e813~mO8caHK4o0684606846epsmtip28; Fri, 21 Feb 2025 13:20:32 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, Jonathan.Cameron@Huawei.com, fan.ni@samsung.com, nifan.cxl@gmail.com, a.manzanares@samsung.com, pankaj.dubey@samsung.com, cassel@kernel.org, 18255117159@163.com, xueshuai@linux.alibaba.com, renyu.zj@linux.alibaba.com, will@kernel.org, mark.rutland@arm.com, Shradha Todi Subject: [PATCH v7 3/5] Add debugfs based silicon debug support in DWC Date: Fri, 21 Feb 2025 18:45:46 +0530 Message-Id: <20250221131548.59616-4-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250221131548.59616-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTe0xbVRzHPfe2twWH3vGYBwyzu4wsAyntKN1hPMYiIZfMhDISNRjDarlp CaVt+pgwIVSozjFhY2524ICCIF2Zg5RHyitrgAx14KYg2xRkQ0ICPpG6ZLIy+5r+9/md7/d7 fjm/cw4XD50iorjFKj2jVUmVFBHMGpzYvy/B9cWQXHDblYDmTm1xkHliD+qoVqAb56w4qu5e ZCOrq5GDbG3zBDJ+tMVG9p/n2Wh2+DKBZlqmCDQ3cI2FTI9NLLRoOs1GnXe+xZB7cAyg9gEX B7XVrAH0ZNTBQXUTlci0kIz+eNRHZO6iP7NeYNNXW64CeqhpkUNb7AbaNPkbm7bbThP0wvwo QQ89SKFX5swY3ddRRdf32wC9ad8t2VFQkqZgpEWMlseoZOqiYpU8nTqaX/hKYbJYIEwQpqCD FE8lLWXSqaxXJQnZxUrPaSneCanS4FmSSHU6KjEjTas26BmeQq3Tp1OMpkipEWn4OmmpzqCS 81WM/pBQIDiQ7DEeL1F0zHdxND8wZZa2T1hGcOq1WsDlQlIEP3ZX1IJgbig5AmBvTxPLX/wF 4IzzHvAXDwG09Ex7lCBfwnjpdkAYA/BKqxXzCqGkC8Dm33leJsg4+N7ftbiXw8n3AZxc3eUN 4OQgDp1Wq08II7Ph+BmnL8wiY+Fj5wLbyyHkIdi+vYr7u70Eu3udPg4iU6HtGzPm3QiSK1zo nlkn/KYs2FC3HAiEwfWpfo6fo+Da2Q8CLIdX+i4FPEr4sK8D8/Nh6Jy7zPIOAyf3w57hRP9y NLz49TWfBSefg3VbKwF7CHS0POUY6HKPBqYSCVtuzLL9TMOGrU7MP6F6AOvcJtY5sLvp/xYW AGwgktHoSuWMLFkjVDHv/HdrMnWpHfhedFyWA9xt3eaPA4wLxgHk4lR4SILeIQ8NKZKWn2S0 6kKtQcnoxkGyZ4ANeFSETO35Eip9oVCUIhCJxWJRSpJYSL0QUjNkkoeScqmeKWEYDaN9msO4 QVFGLH9r6XD+0t3ce+U/yZbib2JUSWRnZWZnqitv/MTL2/EXlsNizAX63AdHCcNmY8Snbblv 0/vCovZMVnSvLSdZinvl0xn1Bwfi1wduTYtWH/FNrVXumtfXjj+hJ2PA2pm8mtKKiBziZGy0 7cjYG5UlVdvsD+38t1KDBL1xWFnawK2Cncdks5V5/Irq+Xcnn9178cfMvS9mGL5UpJrB2Y07 O5e5z69ayooaGmOGv7s+PRVOj5h/uZmoUm7EWsxWXub9z7scvc+E7Tig/id1QbK6UH3/q+Gu P8eOOMrzNJv917M3m40zb07lSDKSNmZl328zzTmSDbFxNLh95Pyv8vPHKqI1gxRLp5AK43Ct TvovVCc0t1oEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeLIzCtJLcpLzFFi42LZdlhJXndx7Y50g4tNwhZX2n+zW0w/rGix pCnD4tiEFcwWTavvslqs+DKT3WLVwmtsFg09v1ktNj2+xmpxedccNouz846zWVzZuo7FouVP C4vF3ZZOVoul1y8yWfzdtpfRYtHWL+wWC5tfMlr837OD3aL3cK1Fyx1Ti/c/N7M5iHksXjGF 1WPNvDWMHjtn3WX3WLCp1KPlyFtWj02rOtk87lzbw+ax86Glx5Mr05k8Ni+p9+jbsorR4/Mm uQCeKC6blNSczLLUIn27BK6MJdeWsxfcSq1YsHAaSwNje1gXIyeHhICJRMOMC4xdjFwcQgK7 GSWedrxhg0hISny+uI4JwhaWWPnvOTtE0SdGiSud/1lAEmwCWhKNX7uYQRIiAp2MEnuPvAOr YhY4xywx83MLI0iVsICbxKHuA2CjWARUJf4cuMMKYvMKWEks+veMGWKFvMTqDQfAbE4Ba4lV 56aD1QsB1ezZcp91AiPfAkaGVYySqQXFuem5xYYFRnmp5XrFibnFpXnpesn5uZsYwZGkpbWD cc+qD3qHGJk4GA8xSnAwK4nw6pbsSBfiTUmsrEotyo8vKs1JLT7EKM3BoiTO++11b4qQQHpi SWp2ampBahFMlomDU6qBad5KjXXOaVU/7r37ki8jcIzp+818w6tLNjw0scwOP3jtebHo380l rw2Ef2dZed4s2KmVLyJz2v771JAl1QKi7fNKrDZvSDy6W+CpoN9a84btfx88L7gZZ3z1hmn3 tM3f/89r/X9472yLL2pdPAvztppO4I5y+Vd0TNVjVqPJZkW+3ScfP3uS9bpC/bWopPmWhJPf 2jd5Vvav+CV07GuIwAPOczf6smYsmZiVtyGtSjNoW63g4z2SF5K4J/GrrLCc9sRht0b+zDiG bzNuVt1X2WZ5xWzLXUvNyqrjJe0X5ThWuP6/dGPrXpNrqneL2CvNPz+T5xCUKC7+8P73C7VC 9XNyAg9uvwl/Nl10paWbaakSS3FGoqEWc1FxIgAB/lHIEwMAAA== X-CMS-MailID: 20250221132035epcas5p47221a5198df9bf86020abcefdfded789 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250221132035epcas5p47221a5198df9bf86020abcefdfded789 References: <20250221131548.59616-1-shradha.t@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250222_025905_301898_A88A9E78 X-CRM114-Status: GOOD ( 27.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support to provide silicon debug interface to userspace. This set of debug registers are part of the RASDES feature present in DesignWare PCIe controllers. Signed-off-by: Shradha Todi --- Documentation/ABI/testing/debugfs-dwc-pcie | 13 ++ drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile | 1 + .../controller/dwc/pcie-designware-debugfs.c | 176 ++++++++++++++++++ .../pci/controller/dwc/pcie-designware-ep.c | 5 + .../pci/controller/dwc/pcie-designware-host.c | 6 + drivers/pci/controller/dwc/pcie-designware.c | 6 + drivers/pci/controller/dwc/pcie-designware.h | 21 +++ include/linux/pcie-dwc.h | 2 + 9 files changed, 240 insertions(+) create mode 100644 Documentation/ABI/testing/debugfs-dwc-pcie create mode 100644 drivers/pci/controller/dwc/pcie-designware-debugfs.c diff --git a/Documentation/ABI/testing/debugfs-dwc-pcie b/Documentation/ABI/testing/debugfs-dwc-pcie new file mode 100644 index 000000000000..e8ed34e988ef --- /dev/null +++ b/Documentation/ABI/testing/debugfs-dwc-pcie @@ -0,0 +1,13 @@ +What: /sys/kernel/debug/dwc_pcie_/rasdes_debug/lane_detect +Date: Feburary 2025 +Contact: Shradha Todi +Description: (RW) Write the lane number to be checked for detection. Read + will return whether PHY indicates receiver detection on the + selected lane. The default selected lane is Lane0. + +What: /sys/kernel/debug/dwc_pcie_/rasdes_debug/rx_valid +Date: Feburary 2025 +Contact: Shradha Todi +Description: (RW) Write the lane number to be checked as valid or invalid. Read + will return the status of PIPE RXVALID signal of the selected lane. + The default selected lane is Lane0. diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index b6d6778b0698..48a10428a492 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -6,6 +6,16 @@ menu "DesignWare-based PCIe controllers" config PCIE_DW bool +config PCIE_DW_DEBUGFS + default y + depends on DEBUG_FS + depends on PCIE_DW_HOST || PCIE_DW_EP + bool "DWC PCIe debugfs entries" + help + Enables debugfs entries for the DW PCIe Controller. These entries + provide all debug features related to DW controller including the RAS + DES features to help in debug, error injection and statistical counters. + config PCIE_DW_HOST bool select PCIE_DW diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index a8308d9ea986..54565eedc52c 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_DW) += pcie-designware.o +obj-$(CONFIG_PCIE_DW_DEBUGFS) += pcie-designware-debugfs.o obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c new file mode 100644 index 000000000000..3887a6996706 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Synopsys DesignWare PCIe controller debugfs driver + * + * Copyright (C) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Author: Shradha Todi + */ + +#include + +#include "pcie-designware.h" + +#define SD_STATUS_L1LANE_REG 0xb0 +#define PIPE_RXVALID BIT(18) +#define PIPE_DETECT_LANE BIT(17) +#define LANE_SELECT GENMASK(3, 0) + +#define DWC_DEBUGFS_BUF_MAX 128 + +/** + * struct dwc_pcie_rasdes_info - Stores controller common information + * @ras_cap_offset: RAS DES vendor specific extended capability offset + * @reg_event_lock: Mutex used for RASDES shadow event registers + * + * Any parameter constant to all files of the debugfs hierarchy for a single controller + * will be stored in this struct. It is allocated and assigned to controller specific + * struct dw_pcie during initialization. + */ +struct dwc_pcie_rasdes_info { + u32 ras_cap_offset; + struct mutex reg_event_lock; +}; + +static ssize_t lane_detect_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) +{ + struct dw_pcie *pci = file->private_data; + struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; + char debugfs_buf[DWC_DEBUGFS_BUF_MAX]; + ssize_t pos; + u32 val; + + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG); + val = FIELD_GET(PIPE_DETECT_LANE, val); + if (val) + pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane Detected\n"); + else + pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane Undetected\n"); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos); +} + +static ssize_t lane_detect_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct dw_pcie *pci = file->private_data; + struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; + u32 lane, val; + + val = kstrtou32_from_user(buf, count, 0, &lane); + if (val) + return val; + + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG); + val &= ~(LANE_SELECT); + val |= FIELD_PREP(LANE_SELECT, lane); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG, val); + + return count; +} + +static ssize_t rx_valid_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) +{ + struct dw_pcie *pci = file->private_data; + struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; + char debugfs_buf[DWC_DEBUGFS_BUF_MAX]; + ssize_t pos; + u32 val; + + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG); + val = FIELD_GET(PIPE_RXVALID, val); + if (val) + pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "RX Valid\n"); + else + pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "RX Invalid\n"); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos); +} + +static ssize_t rx_valid_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) +{ + return lane_detect_write(file, buf, count, ppos); +} + +#define dwc_debugfs_create(name) \ +debugfs_create_file(#name, 0644, rasdes_debug, pci, \ + &dbg_ ## name ## _fops) + +#define DWC_DEBUGFS_FOPS(name) \ +static const struct file_operations dbg_ ## name ## _fops = { \ + .open = simple_open, \ + .read = name ## _read, \ + .write = name ## _write \ +} + +DWC_DEBUGFS_FOPS(lane_detect); +DWC_DEBUGFS_FOPS(rx_valid); + +static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci) +{ + struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; + + mutex_destroy(&rinfo->reg_event_lock); +} + +static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir) +{ + struct dentry *rasdes_debug; + struct dwc_pcie_rasdes_info *rasdes_info; + struct device *dev = pci->dev; + int ras_cap; + + ras_cap = dw_pcie_find_rasdes_capability(pci); + if (!ras_cap) { + dev_dbg(dev, "no RASDES capability available\n"); + return -ENODEV; + } + + rasdes_info = devm_kzalloc(dev, sizeof(*rasdes_info), GFP_KERNEL); + if (!rasdes_info) + return -ENOMEM; + + /* Create subdirectories for Debug, Error injection, Statistics */ + rasdes_debug = debugfs_create_dir("rasdes_debug", dir); + + mutex_init(&rasdes_info->reg_event_lock); + rasdes_info->ras_cap_offset = ras_cap; + pci->debugfs->rasdes_info = rasdes_info; + + /* Create debugfs files for Debug subdirectory */ + dwc_debugfs_create(lane_detect); + dwc_debugfs_create(rx_valid); + + return 0; +} + +void dwc_pcie_debugfs_deinit(struct dw_pcie *pci) +{ + dwc_pcie_rasdes_debugfs_deinit(pci); + debugfs_remove_recursive(pci->debugfs->debug_dir); +} + +int dwc_pcie_debugfs_init(struct dw_pcie *pci) +{ + char dirname[DWC_DEBUGFS_BUF_MAX]; + struct device *dev = pci->dev; + struct debugfs_info *debugfs; + struct dentry *dir; + int ret; + + /* Create main directory for each platform driver */ + snprintf(dirname, DWC_DEBUGFS_BUF_MAX, "dwc_pcie_%s", dev_name(dev)); + dir = debugfs_create_dir(dirname, NULL); + debugfs = devm_kzalloc(dev, sizeof(*debugfs), GFP_KERNEL); + if (!debugfs) + return -ENOMEM; + + debugfs->debug_dir = dir; + pci->debugfs = debugfs; + ret = dwc_pcie_rasdes_debugfs_init(pci, dir); + if (ret) + dev_dbg(dev, "RASDES debugfs init failed\n"); + + return 0; +} diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 72418160e658..f9d7f3f989ad 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -814,6 +814,7 @@ void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + dwc_pcie_debugfs_deinit(pci); dw_pcie_edma_remove(pci); } EXPORT_SYMBOL_GPL(dw_pcie_ep_cleanup); @@ -989,6 +990,10 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) dw_pcie_ep_init_non_sticky_registers(pci); + ret = dwc_pcie_debugfs_init(pci); + if (ret) + goto err_remove_edma; + return 0; err_remove_edma: diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index ffaded8f2df7..2081e8c72d12 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -548,6 +548,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pp->ops->post_init) pp->ops->post_init(pp); + ret = dwc_pcie_debugfs_init(pci); + if (ret) + goto err_stop_link; + return 0; err_stop_link: @@ -572,6 +576,8 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + dwc_pcie_debugfs_deinit(pci); + pci_stop_root_bus(pp->bridge->bus); pci_remove_root_bus(pp->bridge->bus); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index a7c0671c6715..3d1d95d9e380 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -323,6 +323,12 @@ static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, return 0; } +u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci) +{ + return dw_pcie_find_vsec_capability(pci, dwc_pcie_rasdes_vsec_ids); +} +EXPORT_SYMBOL_GPL(dw_pcie_find_rasdes_capability); + int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if (!IS_ALIGNED((uintptr_t)addr, size)) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 501d9ddfea16..7f9807d4e5de 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -437,6 +437,11 @@ struct dw_pcie_ops { void (*stop_link)(struct dw_pcie *pcie); }; +struct debugfs_info { + struct dentry *debug_dir; + void *rasdes_info; +}; + struct dw_pcie { struct device *dev; void __iomem *dbi_base; @@ -465,6 +470,7 @@ struct dw_pcie { struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; bool suspended; + struct debugfs_info *debugfs; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) @@ -478,6 +484,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci); u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); +u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci); int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); @@ -806,4 +813,18 @@ dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no) return NULL; } #endif + +#ifdef CONFIG_PCIE_DW_DEBUGFS +int dwc_pcie_debugfs_init(struct dw_pcie *pci); +void dwc_pcie_debugfs_deinit(struct dw_pcie *pci); +#else +static inline int dwc_pcie_debugfs_init(struct dw_pcie *pci) +{ + return 0; +} +static inline void dwc_pcie_debugfs_deinit(struct dw_pcie *pci) +{ +} +#endif + #endif /* _PCIE_DESIGNWARE_H */ diff --git a/include/linux/pcie-dwc.h b/include/linux/pcie-dwc.h index 40f3545731c8..6436e7fadc75 100644 --- a/include/linux/pcie-dwc.h +++ b/include/linux/pcie-dwc.h @@ -28,6 +28,8 @@ static const struct dwc_pcie_vsec_id dwc_pcie_rasdes_vsec_ids[] = { .vsec_id = 0x02, .vsec_rev = 0x4 }, { .vendor_id = PCI_VENDOR_ID_QCOM, .vsec_id = 0x02, .vsec_rev = 0x4 }, + { .vendor_id = PCI_VENDOR_ID_SAMSUNG, + .vsec_id = 0x02, .vsec_rev = 0x4 }, {} /* terminator */ }; From patchwork Fri Feb 21 13:15:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13986604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F01F5C021B2 for ; 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Fri, 21 Feb 2025 22:20:39 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250221132036epsmtip239bbfc8d2110e7dfeca37e78d74bc091~mO8gNLdXG0774707747epsmtip2G; Fri, 21 Feb 2025 13:20:36 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, Jonathan.Cameron@Huawei.com, fan.ni@samsung.com, nifan.cxl@gmail.com, a.manzanares@samsung.com, pankaj.dubey@samsung.com, cassel@kernel.org, 18255117159@163.com, xueshuai@linux.alibaba.com, renyu.zj@linux.alibaba.com, will@kernel.org, mark.rutland@arm.com, Shradha Todi Subject: [PATCH v7 4/5] Add debugfs based error injection support in DWC Date: Fri, 21 Feb 2025 18:45:47 +0530 Message-Id: <20250221131548.59616-5-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250221131548.59616-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTe0xTVxjAd3pvby9g5fIYHjsELDNTNqBVWg8gvlByM91GsrElW5Z6pdcW KbddH6JmbkWKTiKvZY7JkIh0hBVhhAoWBYeAwDSwMAi6jGYYGQwNAwc6B8LW0rL99zvf9zvn O+c755BYYC8hIjM4I6vnGI2Y8MWbOze9Ej1f16KSXJoNQEOnFwSotHM9sp5Uo+7iGgydrHXy Uc3ceQGyVQ4TyHx2gY8aHwzz0eC1cgL1VfQQaKipHkeW5xYcOS1n+OibuwM8tNjcBtClpjkB qsydBOifVocAFXSeQJYRGZr+207sDKGrar7g05crLgO6pcwpoC82mmhL1xSfbrSdIeiR4VaC brkfT48NlfJou/VTuvCKDdCzjWGpq97P3KZmGSWrj2C5dK0yg1Mlife9rUhWyOQSabQ0Hm0V R3BMFpsk3rM/NTolQ+M6rTjiCKMxuUKpjMEgjt2+Ta81GdkItdZgTBKzOqVGF6eLMTBZBhOn iuFYY4JUItksc4kHMtXVV8t4up/SjjYtWTEzmN6bD3xISMXBz5aeYfnAlwykrgPYMPrYO/gT wL571XzP4CmAA4+6iZUpo7kNuCfRBuC5G9Neaw7A4bpqntsiqCiY8yQfc3MwlQdg13iIW8Ko Zgy219QsJ4IoGjrKhnE349QGOHHvd1ecJIVUArzzl7+nWjisbWhf1n2oRGjrL+W514HUGAnP /tLD90h74N2cKczDQfBhzxWBh0VwsuiUl1XwW/tXXkcDn9qtPA/vgO1D5bi7LkZtgt9di/WE 18Fzt+uXFYxaDQsWxry6EDoqVjgSzi224h5eCyu6B73boeEd5ylvhwoBfPLlb7xiEFb2f4mL ANjAWlZnyFKxBpluM8dm/3dt6dqsRrD8pKNed4D7ozMxHYBHgg4ASUwcLIw2OlSBQiVz7Dir 1yr0Jg1r6AAyV/9KMNGL6VrXn+CMCmlcvCROLpfHxW+RS8VrhLktFlUgpWKMbCbL6lj9yjwe 6SMy8w47PgiN3RuJ80SKnhThRuuPoC2yqvXY8aleYtfuyIP8VRvXBf8wLp+4eSK3RHurJHxn duwixryMd119lFY4cT7yrZmpjiRjSlCi+l3Zjnx/H7yw3T8hDdYF5IXjt53aWltff2VVx67H B0vXVLxkFn39QmiiXP/hkWTYUFKOBpOJj5XP2skbD17tDXeW7O+Tc6MBxZ9TqZ/cmgOvUe8l 5i1prBxzWunMwWYzBybm/fxSFvyKtoL68aIDz38eOjwfbddYcsz18+9M2r8fM4U40Udhg9cX sJkCc9vD7RPW/jfHfLe8kXdh/WpB0oZQjeRodn9uOjkS/+uhQ0LFTTM1+4cYN6gZaRSmNzD/ AliZQORbBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHLMWRmVeSWpSXmKPExsWy7bCSvO7y2h3pBvtuSlhcaf/NbjH9sKLF kqYMi2MTVjBbNK2+y2qx4stMdotVC6+xWTT0/Ga12PT4GqvF5V1z2CzOzjvOZnFl6zoWi5Y/ LSwWd1s6WS2WXr/IZPF3215Gi0Vbv7BbLGx+yWjxf88Odovew7UWLXdMLd7/3MzmIOaxeMUU Vo8189YweuycdZfdY8GmUo+WI29ZPTat6mTzuHNtD5vHzoeWHk+uTGfy2Lyk3qNvyypGj8+b 5AJ4orhsUlJzMstSi/TtErgylm2fxVRwKbRi678lzA2M7127GDk5JARMJB40b2ABsYUEdjNK vJthBxGXlPh8cR0ThC0ssfLfc/YuRi6gmk+MEif2bQNrYBPQkmj82sUMkhAR6GSU2HvkHVgV s8A5ZomZn1sYQaqEBTwkdsy6BtbBIqAq8fzGC6AODg5eASuJ09/5ITbIS6zecIAZxOYUsJZY dW46E8RFVhJ7ttxnncDIt4CRYRWjZGpBcW56brFhgWFearlecWJucWleul5yfu4mRnAUaWnu YNy+6oPeIUYmDsZDjBIczEoivLolO9KFeFMSK6tSi/Lji0pzUosPMUpzsCiJ84q/6E0REkhP LEnNTk0tSC2CyTJxcEo1ME0NrXt9W5UnxsC8vnODVvuTStH2pO6vX1oeB5vscmyd/fMLW0RX RMKm6w0Vj5okjmm+f8/8cja37yStvLI/8Yr7S169jzmfF7lMJKLlwTkur6wHL123TH4xJU/o ++69N89asGyVdt5tonZwTXf6Ta08XdvbpZ6fJc36fk6tO36qI6/puMDmdVNfFhiWWbw667r/ 5fcZL+cxNPvsY/8892NawPWLa24rZfhzpSu+CDuZz3tw7RVG9l0Tg7Ol3/ieVTq/vHmKyI5b lllTLEQSlgXwxDQsqeO9F7DCQHHbto0PTy7/bP6/8lLIiyCrphJv28cLDX6yTC10fu11IWJO WRyP7ToL05s/BWYqv2zKnqLEUpyRaKjFXFScCAACJQ+rEQMAAA== X-CMS-MailID: 20250221132039epcas5p31913eab0acec1eb5e7874897a084c725 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250221132039epcas5p31913eab0acec1eb5e7874897a084c725 References: <20250221131548.59616-1-shradha.t@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250222_025911_460995_8DCB7132 X-CRM114-Status: GOOD ( 26.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support to provide error injection interface to userspace. This set of debug registers are part of the RASDES feature present in DesignWare PCIe controllers. Signed-off-by: Shradha Todi --- Documentation/ABI/testing/debugfs-dwc-pcie | 70 ++++++++ .../controller/dwc/pcie-designware-debugfs.c | 165 +++++++++++++++++- 2 files changed, 233 insertions(+), 2 deletions(-) diff --git a/Documentation/ABI/testing/debugfs-dwc-pcie b/Documentation/ABI/testing/debugfs-dwc-pcie index e8ed34e988ef..6ee0897fe753 100644 --- a/Documentation/ABI/testing/debugfs-dwc-pcie +++ b/Documentation/ABI/testing/debugfs-dwc-pcie @@ -11,3 +11,73 @@ Contact: Shradha Todi Description: (RW) Write the lane number to be checked as valid or invalid. Read will return the status of PIPE RXVALID signal of the selected lane. The default selected lane is Lane0. + +What: /sys/kernel/debug/dwc_pcie_/rasdes_err_inj/ +Date: Feburary 2025 +Contact: Shradha Todi +Description: rasdes_err_inj is the directory which can be used to inject errors in the + system. The possible errors that can be injected are: + + 1) TLP LCRC error injection TX Path - tx_lcrc + 2) 16b CRC error injection of ACK/NAK DLLP - b16_crc_dllp + 3) 16b CRC error injection of Update-FC DLLP - b16_crc_upd_fc + 4) TLP ECRC error injection TX Path - tx_ecrc + 5) TLP's FCRC error injection TX Path - fcrc_tlp + 6) Parity error of TSOS - parity_tsos + 7) Parity error on SKPOS - parity_skpos + 8) LCRC error injection RX Path - rx_lcrc + 9) ECRC error injection RX Path - rx_ecrc + 10) TLPs SEQ# error - tlp_err_seq + 11) DLLPS ACK/NAK SEQ# error - ack_nak_dllp_seq + 12) ACK/NAK DLLPs transmission block - ack_nak_dllp + 13) UpdateFC DLLPs transmission block - upd_fc_dllp + 14) Always transmission for NAK DLLP - nak_dllp + 15) Invert SYNC header - inv_sync_hdr_sym + 16) COM/PAD TS1 order set - com_pad_ts1 + 17) COM/PAD TS2 order set - com_pad_ts2 + 18) COM/FTS FTS order set - com_fts + 19) COM/IDL E-idle order set - com_idl + 20) END/EDB symbol - end_edb + 21) STP/SDP symbol - stp_sdp + 22) COM/SKP SKP order set - com_skp + 23) Posted TLP Header credit value control - posted_tlp_hdr + 24) Non-Posted TLP Header credit value control - non_post_tlp_hdr + 25) Completion TLP Header credit value control - cmpl_tlp_hdr + 26) Posted TLP Data credit value control - posted_tlp_data + 27) Non-Posted TLP Data credit value control - non_post_tlp_data + 28) Completion TLP Data credit value control - cmpl_tlp_data + 29) Generates duplicate TLPs - duplicate_dllp + 30) Generates Nullified TLPs - nullified_tlp + + (WO) Write to the attribute will prepare controller to inject the respective + error in the next transmission of data. Parameter required to write will + change in the following ways: + + i) Errors 9) - 10) are sequence errors. The write command for these will be + + echo > /sys/kernel/debug/dwc_pcie_/rasdes_err_inj/ + + + Number of errors to be injected + + The difference to add or subtract from natural sequence number to + generate sequence error. Range (-4095 : 4095) + + ii) Errors 23) - 28) are credit value error insertions. Write command: + + echo > /sys/kernel/debug/dwc_pcie_/rasdes_err_inj/ + + + Number of errors to be injected + + The difference to add or subtract from UpdateFC credit value. + Range (-4095 : 4095) + + Target VC number + + iii) All other errors. Write command: + + echo > /sys/kernel/debug/dwc_pcie_/rasdes_err_inj/ + + + Number of errors to be injected diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c index 3887a6996706..b7260edd2336 100644 --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -17,6 +17,20 @@ #define PIPE_DETECT_LANE BIT(17) #define LANE_SELECT GENMASK(3, 0) +#define ERR_INJ0_OFF 0x34 +#define EINJ_VAL_DIFF GENMASK(28, 16) +#define EINJ_VC_NUM GENMASK(14, 12) +#define EINJ_TYPE_SHIFT 8 +#define EINJ0_TYPE GENMASK(11, 8) +#define EINJ1_TYPE BIT(8) +#define EINJ2_TYPE GENMASK(9, 8) +#define EINJ3_TYPE GENMASK(10, 8) +#define EINJ4_TYPE GENMASK(10, 8) +#define EINJ5_TYPE BIT(8) +#define EINJ_COUNT GENMASK(7, 0) + +#define ERR_INJ_ENABLE_REG 0x30 + #define DWC_DEBUGFS_BUF_MAX 128 /** @@ -33,6 +47,72 @@ struct dwc_pcie_rasdes_info { struct mutex reg_event_lock; }; +/** + * struct dwc_pcie_rasdes_priv - Stores file specific private data information + * @pci: Reference to the dw_pcie structure + * @idx: Index to point to specific file related information in array of structs + * + * All debugfs files will have this struct as its private data. + */ +struct dwc_pcie_rasdes_priv { + struct dw_pcie *pci; + int idx; +}; + +/** + * struct dwc_pcie_err_inj - Store details about each error injection supported by DWC RASDES + * @name: Name of the error that can be injected + * @err_inj_group: Group number to which the error belongs to. Value can range from 0 - 5 + * @err_inj_type: Each group can have multiple types of error + */ +struct dwc_pcie_err_inj { + const char *name; + u32 err_inj_group; + u32 err_inj_type; +}; + +static const struct dwc_pcie_err_inj err_inj_list[] = { + {"tx_lcrc", 0x0, 0x0}, + {"b16_crc_dllp", 0x0, 0x1}, + {"b16_crc_upd_fc", 0x0, 0x2}, + {"tx_ecrc", 0x0, 0x3}, + {"fcrc_tlp", 0x0, 0x4}, + {"parity_tsos", 0x0, 0x5}, + {"parity_skpos", 0x0, 0x6}, + {"rx_lcrc", 0x0, 0x8}, + {"rx_ecrc", 0x0, 0xb}, + {"tlp_err_seq", 0x1, 0x0}, + {"ack_nak_dllp_seq", 0x1, 0x1}, + {"ack_nak_dllp", 0x2, 0x0}, + {"upd_fc_dllp", 0x2, 0x1}, + {"nak_dllp", 0x2, 0x2}, + {"inv_sync_hdr_sym", 0x3, 0x0}, + {"com_pad_ts1", 0x3, 0x1}, + {"com_pad_ts2", 0x3, 0x2}, + {"com_fts", 0x3, 0x3}, + {"com_idl", 0x3, 0x4}, + {"end_edb", 0x3, 0x5}, + {"stp_sdp", 0x3, 0x6}, + {"com_skp", 0x3, 0x7}, + {"posted_tlp_hdr", 0x4, 0x0}, + {"non_post_tlp_hdr", 0x4, 0x1}, + {"cmpl_tlp_hdr", 0x4, 0x2}, + {"posted_tlp_data", 0x4, 0x4}, + {"non_post_tlp_data", 0x4, 0x5}, + {"cmpl_tlp_data", 0x4, 0x6}, + {"duplicate_dllp", 0x5, 0x0}, + {"nullified_tlp", 0x5, 0x1}, +}; + +static const u32 err_inj_type_mask[] = { + EINJ0_TYPE, + EINJ1_TYPE, + EINJ2_TYPE, + EINJ3_TYPE, + EINJ4_TYPE, + EINJ5_TYPE, +}; + static ssize_t lane_detect_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) { struct dw_pcie *pci = file->private_data; @@ -93,6 +173,63 @@ static ssize_t rx_valid_write(struct file *file, const char __user *buf, size_t return lane_detect_write(file, buf, count, ppos); } +static ssize_t err_inj_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) +{ + struct dwc_pcie_rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; + u32 val, counter, vc_num, err_group, type_mask; + int val_diff = 0; + char *kern_buf; + + err_group = err_inj_list[pdata->idx].err_inj_group; + type_mask = err_inj_type_mask[err_group]; + + kern_buf = memdup_user_nul(buf, count); + if (IS_ERR(kern_buf)) + return PTR_ERR(kern_buf); + + if (err_group == 4) { + val = sscanf(kern_buf, "%u %d %u", &counter, &val_diff, &vc_num); + if ((val != 3) || (val_diff < -4095 || val_diff > 4095)) { + kfree(kern_buf); + return -EINVAL; + } + } else if (err_group == 1) { + val = sscanf(kern_buf, "%u %d", &counter, &val_diff); + if ((val != 2) || (val_diff < -4095 || val_diff > 4095)) { + kfree(kern_buf); + return -EINVAL; + } + } else { + val = kstrtou32(kern_buf, 0, &counter); + if (val) { + kfree(kern_buf); + return val; + } + } + + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x4 * err_group)); + val &= ~(type_mask | EINJ_COUNT); + val |= ((err_inj_list[pdata->idx].err_inj_type << EINJ_TYPE_SHIFT) & type_mask); + val |= FIELD_PREP(EINJ_COUNT, counter); + + if (err_group == 1 || err_group == 4) { + val &= ~(EINJ_VAL_DIFF); + val |= FIELD_PREP(EINJ_VAL_DIFF, val_diff); + } + if (err_group == 4) { + val &= ~(EINJ_VC_NUM); + val |= FIELD_PREP(EINJ_VC_NUM, vc_num); + } + + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x4 * err_group), val); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ_ENABLE_REG, (0x1 << err_group)); + + kfree(kern_buf); + return count; +} + #define dwc_debugfs_create(name) \ debugfs_create_file(#name, 0644, rasdes_debug, pci, \ &dbg_ ## name ## _fops) @@ -107,6 +244,11 @@ static const struct file_operations dbg_ ## name ## _fops = { \ DWC_DEBUGFS_FOPS(lane_detect); DWC_DEBUGFS_FOPS(rx_valid); +static const struct file_operations dwc_pcie_err_inj_ops = { + .open = simple_open, + .write = err_inj_write, +}; + static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci) { struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; @@ -116,10 +258,11 @@ static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci) static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir) { - struct dentry *rasdes_debug; + struct dentry *rasdes_debug, *rasdes_err_inj; struct dwc_pcie_rasdes_info *rasdes_info; + struct dwc_pcie_rasdes_priv *priv_tmp; struct device *dev = pci->dev; - int ras_cap; + int ras_cap, i, ret; ras_cap = dw_pcie_find_rasdes_capability(pci); if (!ras_cap) { @@ -133,6 +276,7 @@ static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir) /* Create subdirectories for Debug, Error injection, Statistics */ rasdes_debug = debugfs_create_dir("rasdes_debug", dir); + rasdes_err_inj = debugfs_create_dir("rasdes_err_inj", dir); mutex_init(&rasdes_info->reg_event_lock); rasdes_info->ras_cap_offset = ras_cap; @@ -142,7 +286,24 @@ static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir) dwc_debugfs_create(lane_detect); dwc_debugfs_create(rx_valid); + /* Create debugfs files for Error injection subdirectory */ + for (i = 0; i < ARRAY_SIZE(err_inj_list); i++) { + priv_tmp = devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL); + if (!priv_tmp) { + ret = -ENOMEM; + goto err_deinit; + } + + priv_tmp->idx = i; + priv_tmp->pci = pci; + debugfs_create_file(err_inj_list[i].name, 0200, rasdes_err_inj, priv_tmp, + &dwc_pcie_err_inj_ops); + } return 0; + +err_deinit: + dwc_pcie_rasdes_debugfs_deinit(pci); + return ret; } void dwc_pcie_debugfs_deinit(struct dw_pcie *pci) From patchwork Fri Feb 21 13:15:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13986605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CDD8C021B2 for ; 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Fri, 21 Feb 2025 22:20:43 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250221132040epsmtip235ddeb74662141dea8de29ac3d819bec~mO8kA6IBJ0684606846epsmtip2-; Fri, 21 Feb 2025 13:20:40 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, Jonathan.Cameron@Huawei.com, fan.ni@samsung.com, nifan.cxl@gmail.com, a.manzanares@samsung.com, pankaj.dubey@samsung.com, cassel@kernel.org, 18255117159@163.com, xueshuai@linux.alibaba.com, renyu.zj@linux.alibaba.com, will@kernel.org, mark.rutland@arm.com, Shradha Todi Subject: [PATCH v7 5/5] Add debugfs based statistical counter support in DWC Date: Fri, 21 Feb 2025 18:45:48 +0530 Message-Id: <20250221131548.59616-6-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250221131548.59616-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VTe0xTVxze6W1vC6HspiA7sIh45x6QFdtJywGBsUnwZiNZjTNuLlm5wrUl lLa0ZczNTYQ6HgqRRQcDeWOohcAsUN6kAwRx4OJa0W2wDASHM25REHGIrLSw/ff9vt/3nd/j nMPDBFfwAF6K2sDo1LSKxD3Z1sHgEKFXc5dCVJflhxy5K1xUMrgd1Wcr0fAZE4ayG6c4yLT4 LReZayZwlHV6hYMstyc4yN59HkfjlSM4crQ3s5HxqZGNpoz5HHTh5nUWWrX2AVTbvshFNTl3 AVrr7eSiwsEvkHFSgv5+0orH+lF1prMcqqmyCVBdZVNcqtqSQRmH7nMoizkfpyYnenGqazqC mnWUsKjW+uNUUZsZUAuWQJnXodQoJUMnM7ogRp2kSU5RK6LJd/fL98glUpFYKI5A4WSQmk5j osm4BJkwPkXlnJYM+oRWZTgpGa3XkztjonSaDAMTpNToDdEko01WacO0oXo6TZ+hVoSqGUOk WCR6Q+IUJqYqu+rGudqzyk8vnVhjZYGOgwXAgweJMNjb7WAXAE+egOgB8HG3mesOHgJ4rn2O 5Q6WAJzLu8fetCyXz3PXsYDoA/Dyg2Nu0SKAo9Zp1noCJ0LgiUcF2Dr2JU4COHTHb12EEVYM 2kwmV8KHSIB5A9+7TmITL8Mq06CL5xORMGv4JstdbRts/M7m4j2I3dB8rcTVEiQmedBhe7Qh ioO/WS0b7fnAP0fauG4cABf+6sPdWAEvtpZibqyCS631G943oc1x3unlObsLhi3dO930Vnju arNLghHesHBldkPOh52Vm/gluLjau1HWH1YO2zluTMHSMhvu3koRgD9ZZthnQGDZ/yWqATAD f0arT1MwSRKtWM1k/ndtSZo0C3A96ZC4TnCr6lnoAGDxwACAPIz05QsNnQoBP5k++hmj08h1 GSpGPwAkzgUWYwFbkjTOP6E2yMVhEaIwqVQaFrFLKiZf4Od0GRUCQkEbmFSG0TK6TR+L5xGQ xTL2PdUO9u8tr7p3OfxnJXvIRrXIS8nXGoXy/lfLc7fGPN539RiWGCva/U3AK2NjU7La3NK8 il+Xx1+83nZB3vFL5Kl9W270jHnsKjGXWt+j7T/cPnorePXHlr1rsvmVYt0DXvr97Yr4NNFo fnzHs/fvHk4VfPlVaHPmttrPk4KWhm6wZwufzOjQPw+vNYymeBVm9h+INnzMvzgl2XFgZLRu XBvzUY63XZlu/z3xeDE6nf1OxaUGaZOq4utqXd4d+xE/SdNibHPZkbcarlQdLviAs/+kr/dz wfa3PbloIVDW4z+/lF40/YdBPj/6+qnA8JrqQ1Ef+sh6n08Q8uOVO5bnKuZmDq6RbL2SFodg Oj39L4kdTUhbBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeLIzCtJLcpLzFFi42LZdlhJXnd17Y50g6+z5S2utP9mt5h+WNFi SVOGxbEJK5gtmlbfZbVY8WUmu8WqhdfYLBp6frNabHp8jdXi8q45bBZn5x1ns7iydR2LRcuf FhaLuy2drBZLr19ksvi7bS+jxaKtX9gtFja/ZLT4v2cHu0Xv4VqLljumFu9/bmZzEPNYvGIK q8eaeWsYPXbOusvusWBTqUfLkbesHptWdbJ53Lm2h81j50NLjydXpjN5bF5S79G3ZRWjx+dN cgE8UVw2Kak5mWWpRfp2CVwZOxefZS+YklGxsfE/UwPj9vAuRk4OCQETiR+zX7B3MXJxCAns ZpQ4feAPM0RCUuLzxXVMELawxMp/z6GKPjFKXH55ng0kwSagJdH4tYsZJCEi0MkosffIO7Aq ZoFzzBIzP7cwglQJC/hIdBw6yA5iswioSsxfcRhsBa+AlUTDsetQK+QlVm84ABbnFLCWWHVu OlhcCKhmz5b7rBMY+RYwMqxilEwtKM5Nzy02LDDMSy3XK07MLS7NS9dLzs/dxAiOJC3NHYzb V33QO8TIxMF4iFGCg1lJhFe3ZEe6EG9KYmVValF+fFFpTmrxIUZpDhYlcV7xF70pQgLpiSWp 2ampBalFMFkmDk6pBqaweEOledoPPhQ8KeXba516k7l10sbibRPnLvz06kH+7sfZtXMqC5bI xrypj++8Pm1nlsi16e94ukslJtvJaCwLK+S/Uh+dJChQsTspehb7ktfiPYEfteoZPcq45P1k 7Cf5/bDe1drt/fCJXXx29ZW5CdfmHdl2eH7umnX3d4UuX3uBy6joipDVqjeTosTtk902OPF2 zswqU/Q4c3ZqnJjSDjaj06dmHZMWjf7uui1565Pu1KW/5tY77L+1vPKcmKiHwbGj5aXJfo2b t1js8fmtoSot2cuU/KA0X7UqKGhOfumWWw9sPt54KXf0qWXYvCq3+NUhk+Jfie5vk3Sa+MZ1 ft/7+CbrOmEDjQkq0UosxRmJhlrMRcWJAF6i09UTAwAA X-CMS-MailID: 20250221132043epcas5p27fde98558b13b3311cdc467e8f246380 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250221132043epcas5p27fde98558b13b3311cdc467e8f246380 References: <20250221131548.59616-1-shradha.t@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250222_025929_428724_9BBA4BE1 X-CRM114-Status: GOOD ( 24.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support to provide statistical counter interface to userspace. This set of debug registers are part of the RASDES feature present in DesignWare PCIe controllers. Signed-off-by: Shradha Todi --- Documentation/ABI/testing/debugfs-dwc-pcie | 61 +++++ .../controller/dwc/pcie-designware-debugfs.c | 229 +++++++++++++++++- 2 files changed, 289 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/debugfs-dwc-pcie b/Documentation/ABI/testing/debugfs-dwc-pcie index 6ee0897fe753..650a89b0511e 100644 --- a/Documentation/ABI/testing/debugfs-dwc-pcie +++ b/Documentation/ABI/testing/debugfs-dwc-pcie @@ -81,3 +81,64 @@ Description: rasdes_err_inj is the directory which can be used to inject errors Number of errors to be injected + +What: /sys/kernel/debug/dwc_pcie_/rasdes_event_counters//counter_enable +Date: Feburary 2025 +Contact: Shradha Todi +Description: rasdes_event_counters is the directory which can be used to collect + statistical data about the number of times a certain event has occurred + in the controller. The list of possible events are: + + 1) EBUF Overflow + 2) EBUF Underrun + 3) Decode Error + 4) Running Disparity Error + 5) SKP OS Parity Error + 6) SYNC Header Error + 7) Rx Valid De-assertion + 8) CTL SKP OS Parity Error + 9) 1st Retimer Parity Error + 10) 2nd Retimer Parity Error + 11) Margin CRC and Parity Error + 12) Detect EI Infer + 13) Receiver Error + 14) RX Recovery Req + 15) N_FTS Timeout + 16) Framing Error + 17) Deskew Error + 18) Framing Error In L0 + 19) Deskew Uncompleted Error + 20) Bad TLP + 21) LCRC Error + 22) Bad DLLP + 23) Replay Number Rollover + 24) Replay Timeout + 25) Rx Nak DLLP + 26) Tx Nak DLLP + 27) Retry TLP + 28) FC Timeout + 29) Poisoned TLP + 30) ECRC Error + 31) Unsupported Request + 32) Completer Abort + 33) Completion Timeout + 34) EBUF SKP Add + 35) EBUF SKP Del + + (RW) Write 1 to enable the event counter and write 0 to disable the event counter. + Read will return whether the counter is currently enabled or disabled. Counter is + disabled by default. + +What: /sys/kernel/debug/dwc_pcie_/rasdes_event_counters//counter_value +Date: Feburary 2025 +Contact: Shradha Todi +Description: (RO) Read will return the current value of the event counter. To reset the counter, + counter should be disabled and enabled back using the 'counter_enable' attribute. + +What: /sys/kernel/debug/dwc_pcie_/rasdes_event_counters//lane_select +Date: Feburary 2025 +Contact: Shradha Todi +Description: (RW) Some lanes in the event list are lane specific events. These include + events 1) - 11) and 34) - 35). + Write lane number for which counter needs to be enabled/disabled/dumped. + Read will return the current selected lane number. Lane0 is selected by default. diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c index b7260edd2336..dca1e9999113 100644 --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -31,6 +31,17 @@ #define ERR_INJ_ENABLE_REG 0x30 +#define RAS_DES_EVENT_COUNTER_DATA_REG 0xc + +#define RAS_DES_EVENT_COUNTER_CTRL_REG 0x8 +#define EVENT_COUNTER_GROUP_SELECT GENMASK(27, 24) +#define EVENT_COUNTER_EVENT_SELECT GENMASK(23, 16) +#define EVENT_COUNTER_LANE_SELECT GENMASK(11, 8) +#define EVENT_COUNTER_STATUS BIT(7) +#define EVENT_COUNTER_ENABLE GENMASK(4, 2) +#define PER_EVENT_ON 0x3 +#define PER_EVENT_OFF 0x1 + #define DWC_DEBUGFS_BUF_MAX 128 /** @@ -113,6 +124,61 @@ static const u32 err_inj_type_mask[] = { EINJ5_TYPE, }; +/** + * struct dwc_pcie_event_counter - Store details about each event counter supported in DWC RASDES + * @name: Name of the error counter + * @group_no: Group number that the event belongs to. Value ranges from 0 - 4 + * @event_no: Event number of the particular event. Value ranges from - + * Group 0: 0 - 10 + * Group 1: 5 - 13 + * Group 2: 0 - 7 + * Group 3: 0 - 5 + * Group 4: 0 - 1 + */ +struct dwc_pcie_event_counter { + const char *name; + u32 group_no; + u32 event_no; +}; + +static const struct dwc_pcie_event_counter event_list[] = { + {"ebuf_overflow", 0x0, 0x0}, + {"ebuf_underrun", 0x0, 0x1}, + {"decode_err", 0x0, 0x2}, + {"running_disparity_err", 0x0, 0x3}, + {"skp_os_parity_err", 0x0, 0x4}, + {"sync_header_err", 0x0, 0x5}, + {"rx_valid_deassertion", 0x0, 0x6}, + {"ctl_skp_os_parity_err", 0x0, 0x7}, + {"retimer_parity_err_1st", 0x0, 0x8}, + {"retimer_parity_err_2nd", 0x0, 0x9}, + {"margin_crc_parity_err", 0x0, 0xA}, + {"detect_ei_infer", 0x1, 0x5}, + {"receiver_err", 0x1, 0x6}, + {"rx_recovery_req", 0x1, 0x7}, + {"n_fts_timeout", 0x1, 0x8}, + {"framing_err", 0x1, 0x9}, + {"deskew_err", 0x1, 0xa}, + {"framing_err_in_l0", 0x1, 0xc}, + {"deskew_uncompleted_err", 0x1, 0xd}, + {"bad_tlp", 0x2, 0x0}, + {"lcrc_err", 0x2, 0x1}, + {"bad_dllp", 0x2, 0x2}, + {"replay_num_rollover", 0x2, 0x3}, + {"replay_timeout", 0x2, 0x4}, + {"rx_nak_dllp", 0x2, 0x5}, + {"tx_nak_dllp", 0x2, 0x6}, + {"retry_tlp", 0x2, 0x7}, + {"fc_timeout", 0x3, 0x0}, + {"poisoned_tlp", 0x3, 0x1}, + {"ecrc_error", 0x3, 0x2}, + {"unsupported_request", 0x3, 0x3}, + {"completer_abort", 0x3, 0x4}, + {"completion_timeout", 0x3, 0x5}, + {"ebuf_skp_add", 0x4, 0x0}, + {"ebuf_skp_del", 0x4, 0x1}, +}; + static ssize_t lane_detect_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) { struct dw_pcie *pci = file->private_data; @@ -230,6 +296,127 @@ static ssize_t err_inj_write(struct file *file, const char __user *buf, size_t c return count; } +static void set_event_number(struct dwc_pcie_rasdes_priv *pdata, struct dw_pcie *pci, + struct dwc_pcie_rasdes_info *rinfo) +{ + u32 val; + + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + val &= ~EVENT_COUNTER_ENABLE; + val &= ~(EVENT_COUNTER_GROUP_SELECT | EVENT_COUNTER_EVENT_SELECT); + val |= FIELD_PREP(EVENT_COUNTER_GROUP_SELECT, event_list[pdata->idx].group_no); + val |= FIELD_PREP(EVENT_COUNTER_EVENT_SELECT, event_list[pdata->idx].event_no); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val); +} + +static ssize_t counter_enable_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) +{ + struct dwc_pcie_rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; + char debugfs_buf[DWC_DEBUGFS_BUF_MAX]; + ssize_t pos; + u32 val; + + mutex_lock(&rinfo->reg_event_lock); + set_event_number(pdata, pci, rinfo); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + mutex_unlock(&rinfo->reg_event_lock); + val = FIELD_GET(EVENT_COUNTER_STATUS, val); + if (val) + pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Enabled\n"); + else + pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Disabled\n"); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos); +} + +static ssize_t counter_enable_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct dwc_pcie_rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; + u32 val, enable; + + val = kstrtou32_from_user(buf, count, 0, &enable); + if (val) + return val; + + mutex_lock(&rinfo->reg_event_lock); + set_event_number(pdata, pci, rinfo); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + if (enable) + val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_ON); + else + val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_OFF); + + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val); + mutex_unlock(&rinfo->reg_event_lock); + + return count; +} + +static ssize_t counter_lane_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) +{ + struct dwc_pcie_rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; + char debugfs_buf[DWC_DEBUGFS_BUF_MAX]; + ssize_t pos; + u32 val; + + mutex_lock(&rinfo->reg_event_lock); + set_event_number(pdata, pci, rinfo); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + mutex_unlock(&rinfo->reg_event_lock); + val = FIELD_GET(EVENT_COUNTER_LANE_SELECT, val); + pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane: %d\n", val); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos); +} + +static ssize_t counter_lane_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct dwc_pcie_rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; + u32 val, lane; + + val = kstrtou32_from_user(buf, count, 0, &lane); + if (val) + return val; + + mutex_lock(&rinfo->reg_event_lock); + set_event_number(pdata, pci, rinfo); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + val &= ~(EVENT_COUNTER_LANE_SELECT); + val |= FIELD_PREP(EVENT_COUNTER_LANE_SELECT, lane); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val); + mutex_unlock(&rinfo->reg_event_lock); + + return count; +} + +static ssize_t counter_value_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) +{ + struct dwc_pcie_rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; + char debugfs_buf[DWC_DEBUGFS_BUF_MAX]; + ssize_t pos; + u32 val; + + mutex_lock(&rinfo->reg_event_lock); + set_event_number(pdata, pci, rinfo); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_DATA_REG); + mutex_unlock(&rinfo->reg_event_lock); + pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter value: %d\n", val); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos); +} + #define dwc_debugfs_create(name) \ debugfs_create_file(#name, 0644, rasdes_debug, pci, \ &dbg_ ## name ## _fops) @@ -249,6 +436,23 @@ static const struct file_operations dwc_pcie_err_inj_ops = { .write = err_inj_write, }; +static const struct file_operations dwc_pcie_counter_enable_ops = { + .open = simple_open, + .read = counter_enable_read, + .write = counter_enable_write, +}; + +static const struct file_operations dwc_pcie_counter_lane_ops = { + .open = simple_open, + .read = counter_lane_read, + .write = counter_lane_write, +}; + +static const struct file_operations dwc_pcie_counter_value_ops = { + .open = simple_open, + .read = counter_value_read, +}; + static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci) { struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; @@ -258,7 +462,7 @@ static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci) static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir) { - struct dentry *rasdes_debug, *rasdes_err_inj; + struct dentry *rasdes_debug, *rasdes_err_inj, *rasdes_event_counter, *rasdes_events; struct dwc_pcie_rasdes_info *rasdes_info; struct dwc_pcie_rasdes_priv *priv_tmp; struct device *dev = pci->dev; @@ -277,6 +481,7 @@ static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir) /* Create subdirectories for Debug, Error injection, Statistics */ rasdes_debug = debugfs_create_dir("rasdes_debug", dir); rasdes_err_inj = debugfs_create_dir("rasdes_err_inj", dir); + rasdes_event_counter = debugfs_create_dir("rasdes_event_counter", dir); mutex_init(&rasdes_info->reg_event_lock); rasdes_info->ras_cap_offset = ras_cap; @@ -299,6 +504,28 @@ static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir) debugfs_create_file(err_inj_list[i].name, 0200, rasdes_err_inj, priv_tmp, &dwc_pcie_err_inj_ops); } + + /* Create debugfs files for Statistical counter subdirectory */ + for (i = 0; i < ARRAY_SIZE(event_list); i++) { + priv_tmp = devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL); + if (!priv_tmp) { + ret = -ENOMEM; + goto err_deinit; + } + + priv_tmp->idx = i; + priv_tmp->pci = pci; + rasdes_events = debugfs_create_dir(event_list[i].name, rasdes_event_counter); + if (event_list[i].group_no == 0 || event_list[i].group_no == 4) { + debugfs_create_file("lane_select", 0644, rasdes_events, + priv_tmp, &dwc_pcie_counter_lane_ops); + } + debugfs_create_file("counter_value", 0444, rasdes_events, priv_tmp, + &dwc_pcie_counter_value_ops); + debugfs_create_file("counter_enable", 0644, rasdes_events, priv_tmp, + &dwc_pcie_counter_enable_ops); + } + return 0; err_deinit: