From patchwork Mon Feb 24 18:01:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 13988703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 376D0C021BC for ; Mon, 24 Feb 2025 18:17:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3Pv8LFCx4t6NMriqTItuy7XpPPudhzwAqEqZ8Lq4mjI=; b=kqwz7fnNkMZBDbXxl65X++7wck /5KeMMzlJQbBBnFgyJ/HMtAZ11vQJyOEFeZOKyu2f+o1hLw1k1SNtvhMx75d9eNz+zehD3q5gVXtI imOc0DXvKiGR4s7MQnTo2VtscHgBXekEmRhWa6ZGhtZekEOmMsWst5lGvbAvfI7anCHq4BLD/ZqPn YAcMLkO4DDNSGb8zm7bKxntWY0KgVq7TLSucCb/XRSGQoU355b1UmvBJCYYklCRZVGPjGYimPda13 f1d6RLb6r7hvg6HrfCAhF2Hp/bpw8BpW2KM9PS7DBk6PUzcYHnulrOelxEGzjGWnSz5pNyXfQQ6dp PqaXBKzg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tmd16-0000000ElqU-0hfL; Mon, 24 Feb 2025 18:17:20 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tmcxj-0000000El8g-2f1A for linux-arm-kernel@lists.infradead.org; Mon, 24 Feb 2025 18:13:53 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51OFKCXP023814; Mon, 24 Feb 2025 19:13:43 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 3Pv8LFCx4t6NMriqTItuy7XpPPudhzwAqEqZ8Lq4mjI=; b=SEzwfKKXhOi0idtv A6QNfbDuVgfR9QDuvk2NlwNvjRR2k17PvPHMp/2BgxeolZJ/7A1icFkNT5GdLttU Rs/I56jtDtEsLC208t0ujEia+MiAfKMcZMR3etFYpksvgB8ySlp+qSHCs9Y68JVD g6cJ008Q+5MbkcFSQrUMKm3HocBeNo7zHrzjny1418gl0H1KCd6RNqT0hvr6G8fT iCVoG93zwc3V2WUjEJNPg0GRSXxGJ7D9TpjoHeP1goDngUyCFQghC0GTGTUvfhI3 GKYWk8ClQujK4Vjk33KTNbK82Pk/Z+EPgZAjK2fDG+jPbCwOruto868lDCi7cmoC XxvPjQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 44y6bh0hw4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Feb 2025 19:13:38 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 184994002D; Mon, 24 Feb 2025 19:12:21 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node4.st.com [10.75.129.133]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 933E553FC05; Mon, 24 Feb 2025 19:02:30 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE4.st.com (10.75.129.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:30 +0100 Received: from localhost (10.252.23.75) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:30 +0100 From: Fabrice Gasnier To: , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH 1/8] dt-bindings: mfd: stm32-lptimer: add support for stm32mp25 Date: Mon, 24 Feb 2025 19:01:43 +0100 Message-ID: <20250224180150.3689638-2-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> References: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.23.75] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-24_09,2025-02-24_02,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250224_101351_953459_65F3319A X-CRM114-Status: GOOD ( 10.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a new stm32mp25 compatible to stm32-lptimer dt-bindings, to support STM32MP25 SoC. Some features has been added to the low-power timer like new capture compare channels (hence more PWM channels, and PWM input capture). Some registers/bits has been revisited to support this. So introduce a new compatible to handle this diversity. Signed-off-by: Fabrice Gasnier --- .../bindings/mfd/st,stm32-lptimer.yaml | 23 +++++++++++++++---- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml index d41308856408..4822ce5d0c76 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml @@ -21,7 +21,9 @@ maintainers: properties: compatible: - const: st,stm32-lptimer + enum: + - st,stm32-lptimer + - st,stm32mp25-lptimer reg: maxItems: 1 @@ -48,13 +50,18 @@ properties: minItems: 1 maxItems: 2 + power-domains: + maxItems: 1 + pwm: type: object additionalProperties: false properties: compatible: - const: st,stm32-pwm-lp + enum: + - st,stm32-pwm-lp + - st,stm32mp25-pwm-lp "#pwm-cells": const: 3 @@ -69,7 +76,9 @@ properties: properties: compatible: - const: st,stm32-lptimer-counter + enum: + - st,stm32-lptimer-counter + - st,stm32mp25-lptimer-counter required: - compatible @@ -80,7 +89,9 @@ properties: properties: compatible: - const: st,stm32-lptimer-timer + enum: + - st,stm32-lptimer-timer + - st,stm32mp25-lptimer-timer required: - compatible @@ -92,7 +103,9 @@ patternProperties: properties: compatible: - const: st,stm32-lptimer-trigger + enum: + - st,stm32-lptimer-trigger + - st,stm32mp25-lptimer-trigger reg: description: Identify trigger hardware block. From patchwork Mon Feb 24 18:01:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 13988722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F4078C021A4 for ; Mon, 24 Feb 2025 18:25:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cs7t9yYlqzv4YN0HD7elj1semSKrTp6ZNSbNhngTkWU=; b=LwiLnjp20O+B+gXDk3F7raAJcA oV3nnqcgwQW0VngE6McBnp1VwI2EWLOCRRLIv/I7HtYIKxP74tNz2gtnW1J2rKtlrY+vPCrc1VY7r 6HO+EWGWX367J01c/RciMVP5avIN5NSKUagPI3PreH/hAZMPXr9hLutcdqevsJA2ftXPrFgARMn78 2bjoC1DEuHfFlJHACrnWkayim8KHAunJflJjG5qqdjyyqC2AFRiOZAcNuX8scOgGgMtMn9svM4rRf 1nKKb4JpDnYotNuk+RJNwlBkXreUQFYl9/Pp7o2SMu/3yH6tOMu9TaYcnxm+v7TXVGKBkc5e08IZE 770TgiEw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tmd8P-0000000EnKp-2ixa; Mon, 24 Feb 2025 18:24:53 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tmcyD-0000000ElFW-04ji for linux-arm-kernel@lists.infradead.org; Mon, 24 Feb 2025 18:14:22 +0000 Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51OHE4Y5028322; Mon, 24 Feb 2025 19:14:15 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= cs7t9yYlqzv4YN0HD7elj1semSKrTp6ZNSbNhngTkWU=; b=8Yzg+y7UWMflXClg obv1uTwhz+bq4xUET27pnNg+kvad923XGuYQna/LEey+LqdTk47GES+4UfOFrLwh sVzG2nLRMsOBY7Ew9A+gvHT0Uhj1nIs1YeoE7QDLvGWaf02hcFSHpIezRLcDMJ0a tfHh1Y+W5lJQtCwKVbx+OvIE8Mfe86BepLjf8TAMDvmOVmu1IXF2uHHs15Gaawc6 VRREwRQwJ8mjwUNu6R2x2DlS0uWtSQE+HuQiX6aYhc7NRYJAEgDcKCMfEGsFhHYQ KEpGPpc4BeZQSxYr+iTgpoxu4B/8GOKgFNEKUhVbz1f5SfvcXa33r6Hl91b+Eyz1 RkFx6Q== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 44ytdn68f4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Feb 2025 19:14:14 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id ED66B40079; Mon, 24 Feb 2025 19:12:29 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node6.st.com [10.75.129.135]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 8323B545158; Mon, 24 Feb 2025 19:02:31 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE6.st.com (10.75.129.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:31 +0100 Received: from localhost (10.252.23.75) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:31 +0100 From: Fabrice Gasnier To: , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH 2/8] mfd: stm32-lptimer: add support for stm32mp25 Date: Mon, 24 Feb 2025 19:01:44 +0100 Message-ID: <20250224180150.3689638-3-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> References: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.23.75] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-24_09,2025-02-24_02,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250224_101421_349325_8F9F233B X-CRM114-Status: GOOD ( 20.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for STM32MP25 SoC. Use newly introduced compatible, to handle new features along with registers and bits diversity. A new hardware configuration register (HWCFGR2) has been added, to gather number of capture/compare channels, autonomous mode and input capture capability. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features. This can now be read from HWCFGR registers. Add new registers to the stm32-lptimer.h: CCMR1, CCR2 and HWCFGR1/2. Update the stm32_lptimer data struct so signal the number of capture/compare channels to the child devices. Also Remove some unused bit masks (CMPOK_ARROK / CMPOKCF_ARROKCF). Signed-off-by: Fabrice Gasnier --- drivers/mfd/stm32-lptimer.c | 30 ++++++++++++++++++++++++++++- include/linux/mfd/stm32-lptimer.h | 32 +++++++++++++++++++++++++++++-- 2 files changed, 59 insertions(+), 3 deletions(-) diff --git a/drivers/mfd/stm32-lptimer.c b/drivers/mfd/stm32-lptimer.c index b2704a9809c7..e5a9ceb78c10 100644 --- a/drivers/mfd/stm32-lptimer.c +++ b/drivers/mfd/stm32-lptimer.c @@ -6,6 +6,7 @@ * Inspired by Benjamin Gaignard's stm32-timers driver */ +#include #include #include #include @@ -49,6 +50,32 @@ static int stm32_lptimer_detect_encoder(struct stm32_lptimer *ddata) return 0; } +static int stm32_lptimer_detect_hwcfgr(struct stm32_lptimer *ddata) +{ + u32 val; + int ret; + + /* Try to guess parameters from HWCFGR: e.g. encodrer mode (STM32MP15) */ + ret = regmap_read(ddata->regmap, STM32MP15_LPTIM_HWCFGR, &val); + if (ret) + return ret; + + /* Fallback to legacy init if HWCFGR isn't present */ + if (!val) + return stm32_lptimer_detect_encoder(ddata); + + ddata->has_encoder = FIELD_GET(STM32MP15_LPTIM_HWCFGR_ENCODER, val); + + ret = regmap_read(ddata->regmap, STM32MP25_LPTIM_HWCFGR2, &val); + if (ret) + return ret; + + /* Number of capture/compare channels */ + ddata->num_cc_chans = FIELD_GET(STM32MP25_LPTIM_HWCFGR2_CHAN_NUM, val); + + return 0; +} + static int stm32_lptimer_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -73,7 +100,7 @@ static int stm32_lptimer_probe(struct platform_device *pdev) if (IS_ERR(ddata->clk)) return PTR_ERR(ddata->clk); - ret = stm32_lptimer_detect_encoder(ddata); + ret = stm32_lptimer_detect_hwcfgr(ddata); if (ret) return ret; @@ -84,6 +111,7 @@ static int stm32_lptimer_probe(struct platform_device *pdev) static const struct of_device_id stm32_lptimer_of_match[] = { { .compatible = "st,stm32-lptimer", }, + { .compatible = "st,stm32mp25-lptimer", }, {}, }; MODULE_DEVICE_TABLE(of, stm32_lptimer_of_match); diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lptimer.h index 06d3f11dc3c9..b9da7d0d2a36 100644 --- a/include/linux/mfd/stm32-lptimer.h +++ b/include/linux/mfd/stm32-lptimer.h @@ -17,18 +17,26 @@ #define STM32_LPTIM_IER 0x08 /* Interrupt Enable Reg */ #define STM32_LPTIM_CFGR 0x0C /* Configuration Reg */ #define STM32_LPTIM_CR 0x10 /* Control Reg */ -#define STM32_LPTIM_CMP 0x14 /* Compare Reg */ +#define STM32_LPTIM_CMP 0x14 /* Compare Reg (CCR1 on mp25) */ #define STM32_LPTIM_ARR 0x18 /* Autoreload Reg */ #define STM32_LPTIM_CNT 0x1C /* Counter Reg */ +#define STM32MP25_LPTIM_CCMR1 0x2C /* Capture/Compare Mode Reg */ +#define STM32MP25_LPTIM_CCR2 0x34 /* Compare Reg2 */ + +#define STM32MP25_LPTIM_HWCFGR2 0x3EC /* Hardware configuration register 2 */ +#define STM32MP15_LPTIM_HWCFGR 0x3F0 /* Hardware configuration register 1 */ +#define STM32MP15_LPTIM_VERR 0x3F4 /* Version identification register */ /* STM32_LPTIM_ISR - bit fields */ +#define STM32_LPTIM_CMP2_ARROK (BIT(19) | BIT(4)) #define STM32_LPTIM_CMPOK_ARROK GENMASK(4, 3) #define STM32_LPTIM_ARROK BIT(4) #define STM32_LPTIM_CMPOK BIT(3) /* STM32_LPTIM_ICR - bit fields */ -#define STM32_LPTIM_ARRMCF BIT(1) +#define STM32_LPTIM_CMP2OKCF_ARROKCF (BIT(19) | BIT(4)) #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3) +#define STM32_LPTIM_ARRMCF BIT(1) /* STM32_LPTIM_IER - bit flieds */ #define STM32_LPTIM_ARRMIE BIT(1) @@ -53,16 +61,36 @@ /* STM32_LPTIM_ARR */ #define STM32_LPTIM_MAX_ARR 0xFFFF +/* STM32MP25_LPTIM_CCMR1 */ +#define STM32MP25_LPTIM_CC2P GENMASK(19, 18) +#define STM32MP25_LPTIM_CC2E BIT(17) +#define STM32MP25_LPTIM_CC2SEL BIT(16) +#define STM32MP25_LPTIM_CC1P GENMASK(3, 2) +#define STM32MP25_LPTIM_CC1E BIT(1) +#define STM32MP25_LPTIM_CC1SEL BIT(0) + +/* STM32MP15_LPTIM_HWCFGR */ +#define STM32MP15_LPTIM_HWCFGR_ENCODER BIT(16) + +/* STM32MP25_LPTIM_HWCFGR2 */ +#define STM32MP25_LPTIM_HWCFGR2_CHAN_NUM GENMASK(3, 0) + +/* STM32MP15_LPTIM_VERR */ +#define STM32MP15_MINREV_MASK GENMASK(3, 0) +#define STM32MP15_MAJREV_MASK GENMASK(7, 4) + /** * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device * @clk: clock reference for this instance * @regmap: register map reference for this instance * @has_encoder: indicates this Low-Power Timer supports encoder mode + * @num_cc_chans: indicates the number of capture/compare channels */ struct stm32_lptimer { struct clk *clk; struct regmap *regmap; bool has_encoder; + unsigned int num_cc_chans; }; #endif From patchwork Mon Feb 24 18:01:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 13988732 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BEF54C021A4 for ; Mon, 24 Feb 2025 18:28:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Mon, 24 Feb 2025 19:02:32 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE5.st.com (10.75.129.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:32 +0100 Received: from localhost (10.252.23.75) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:31 +0100 From: Fabrice Gasnier To: , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH 3/8] iio: trigger: stm32-lptimer: add support for stm32mp25 Date: Mon, 24 Feb 2025 19:01:45 +0100 Message-ID: <20250224180150.3689638-4-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> References: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.23.75] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-24_09,2025-02-24_02,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250224_101940_670708_FA6BD10B X-CRM114-Status: GOOD ( 20.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Olivier Moysan Add support for STM32MP25 SoC. Use newly introduced compatible to handle this new HW variant. Add new trigger definitions that can be used by the stm32 analog-to-digital converter. Use compatible data to identify them. Signed-off-by: Olivier Moysan Signed-off-by: Fabrice Gasnier --- drivers/iio/trigger/stm32-lptimer-trigger.c | 109 +++++++++++++++--- include/linux/iio/timer/stm32-lptim-trigger.h | 9 ++ 2 files changed, 99 insertions(+), 19 deletions(-) diff --git a/drivers/iio/trigger/stm32-lptimer-trigger.c b/drivers/iio/trigger/stm32-lptimer-trigger.c index f1e18913236a..995234c1e7d5 100644 --- a/drivers/iio/trigger/stm32-lptimer-trigger.c +++ b/drivers/iio/trigger/stm32-lptimer-trigger.c @@ -16,16 +16,44 @@ #include #include -/* List Low-Power Timer triggers */ -static const char * const stm32_lptim_triggers[] = { - LPTIM1_OUT, - LPTIM2_OUT, - LPTIM3_OUT, +/* Maximum triggers + one trailing null entry to indicate the end of array */ +#define MAX_TRIGGERS 3 + +struct stm32_lptim_cfg { + const char * const (*triggers)[MAX_TRIGGERS]; + unsigned int nb_triggers; +}; + +/* List Low-Power Timer triggers for H7, MP13, MP15 */ +static const char * const stm32_lptim_triggers[][MAX_TRIGGERS] = { + { LPTIM1_OUT,}, + { LPTIM2_OUT,}, + { LPTIM3_OUT,}, +}; + +/* List Low-Power Timer triggers for STM32MP25 */ +static const char * const stm32mp25_lptim_triggers[][MAX_TRIGGERS] = { + { LPTIM1_CH1, LPTIM1_CH2, }, + { LPTIM2_CH1, LPTIM2_CH2, }, + { LPTIM3_CH1,}, + { LPTIM4_CH1,}, + { LPTIM5_OUT,}, +}; + +static const struct stm32_lptim_cfg stm32mp15_lptim_cfg = { + .triggers = stm32_lptim_triggers, + .nb_triggers = ARRAY_SIZE(stm32_lptim_triggers), +}; + +static const struct stm32_lptim_cfg stm32mp25_lptim_cfg = { + .triggers = stm32mp25_lptim_triggers, + .nb_triggers = ARRAY_SIZE(stm32mp25_lptim_triggers), }; struct stm32_lptim_trigger { struct device *dev; - const char *trg; + const char * const *triggers; + struct list_head tr_list; }; static int stm32_lptim_validate_device(struct iio_trigger *trig, @@ -54,25 +82,49 @@ bool is_stm32_lptim_trigger(struct iio_trigger *trig) } EXPORT_SYMBOL(is_stm32_lptim_trigger); -static int stm32_lptim_setup_trig(struct stm32_lptim_trigger *priv) +static void stm32_lptim_unregister_triggers(struct stm32_lptim_trigger *priv) { - struct iio_trigger *trig; + struct iio_trigger *tr; - trig = devm_iio_trigger_alloc(priv->dev, "%s", priv->trg); - if (!trig) - return -ENOMEM; + list_for_each_entry(tr, &priv->tr_list, alloc_list) + iio_trigger_unregister(tr); +} + +static int stm32_lptim_register_triggers(struct stm32_lptim_trigger *priv) +{ + const char * const *cur = priv->triggers; + int ret; - trig->dev.parent = priv->dev->parent; - trig->ops = &stm32_lptim_trigger_ops; - iio_trigger_set_drvdata(trig, priv); + INIT_LIST_HEAD(&priv->tr_list); - return devm_iio_trigger_register(priv->dev, trig); + while (cur && *cur) { + struct iio_trigger *trig; + + trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur); + if (!trig) + return -ENOMEM; + + trig->dev.parent = priv->dev->parent; + trig->ops = &stm32_lptim_trigger_ops; + iio_trigger_set_drvdata(trig, priv); + + ret = iio_trigger_register(trig); + if (ret) + return ret; + + list_add_tail(&trig->alloc_list, &priv->tr_list); + cur++; + } + + return 0; } static int stm32_lptim_trigger_probe(struct platform_device *pdev) { struct stm32_lptim_trigger *priv; + struct stm32_lptim_cfg const *lptim_cfg; u32 index; + int ret; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -81,23 +133,42 @@ static int stm32_lptim_trigger_probe(struct platform_device *pdev) if (device_property_read_u32(&pdev->dev, "reg", &index)) return -EINVAL; - if (index >= ARRAY_SIZE(stm32_lptim_triggers)) + lptim_cfg = device_get_match_data(&pdev->dev); + + if (index >= lptim_cfg->nb_triggers) return -EINVAL; priv->dev = &pdev->dev; - priv->trg = stm32_lptim_triggers[index]; + priv->triggers = lptim_cfg->triggers[index]; + + ret = stm32_lptim_register_triggers(priv); + if (ret) { + stm32_lptim_unregister_triggers(priv); + return ret; + } + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static void stm32_lptim_trigger_remove(struct platform_device *pdev) +{ + struct stm32_lptim_trigger *priv = platform_get_drvdata(pdev); - return stm32_lptim_setup_trig(priv); + stm32_lptim_unregister_triggers(priv); } static const struct of_device_id stm32_lptim_trig_of_match[] = { - { .compatible = "st,stm32-lptimer-trigger", }, + { .compatible = "st,stm32-lptimer-trigger", .data = (void *)&stm32mp15_lptim_cfg }, + { .compatible = "st,stm32mp25-lptimer-trigger", .data = (void *)&stm32mp25_lptim_cfg}, {}, }; MODULE_DEVICE_TABLE(of, stm32_lptim_trig_of_match); static struct platform_driver stm32_lptim_trigger_driver = { .probe = stm32_lptim_trigger_probe, + .remove = stm32_lptim_trigger_remove, .driver = { .name = "stm32-lptimer-trigger", .of_match_table = stm32_lptim_trig_of_match, diff --git a/include/linux/iio/timer/stm32-lptim-trigger.h b/include/linux/iio/timer/stm32-lptim-trigger.h index a34dcf6a6001..ce3cf0addb2e 100644 --- a/include/linux/iio/timer/stm32-lptim-trigger.h +++ b/include/linux/iio/timer/stm32-lptim-trigger.h @@ -14,6 +14,15 @@ #define LPTIM1_OUT "lptim1_out" #define LPTIM2_OUT "lptim2_out" #define LPTIM3_OUT "lptim3_out" +#define LPTIM4_OUT "lptim4_out" +#define LPTIM5_OUT "lptim5_out" + +#define LPTIM1_CH1 "lptim1_ch1" +#define LPTIM1_CH2 "lptim1_ch2" +#define LPTIM2_CH1 "lptim2_ch1" +#define LPTIM2_CH2 "lptim2_ch2" +#define LPTIM3_CH1 "lptim3_ch1" +#define LPTIM4_CH1 "lptim4_ch1" #if IS_REACHABLE(CONFIG_IIO_STM32_LPTIMER_TRIGGER) bool is_stm32_lptim_trigger(struct iio_trigger *trig); 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Mon, 24 Feb 2025 19:02:33 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE4.st.com (10.75.129.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:32 +0100 Received: from localhost (10.252.23.75) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:32 +0100 From: Fabrice Gasnier To: , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH 4/8] clocksource: stm32-lptimer: add stm32mp25 support Date: Mon, 24 Feb 2025 19:01:46 +0100 Message-ID: <20250224180150.3689638-5-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> References: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.23.75] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-24_09,2025-02-24_02,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250224_101931_845048_9B650E25 X-CRM114-Status: GOOD ( 10.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Patrick Delaunay Add the support of the new compatible for STM32MP25 SoC in driver, as described in Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml and used in arch/arm64/boot/dts/st/stm32mp251.dtsi. Signed-off-by: Patrick Delaunay Signed-off-by: Fabrice Gasnier --- drivers/clocksource/timer-stm32-lp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clocksource/timer-stm32-lp.c b/drivers/clocksource/timer-stm32-lp.c index a4c95161cb22..db055348e2cc 100644 --- a/drivers/clocksource/timer-stm32-lp.c +++ b/drivers/clocksource/timer-stm32-lp.c @@ -197,6 +197,7 @@ static int stm32_clkevent_lp_probe(struct platform_device *pdev) static const struct of_device_id stm32_clkevent_lp_of_match[] = { { .compatible = "st,stm32-lptimer-timer", }, + { .compatible = "st,stm32mp25-lptimer-timer", }, {}, }; MODULE_DEVICE_TABLE(of, stm32_clkevent_lp_of_match); From patchwork Mon Feb 24 18:01:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 13988721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 350E0C021A4 for ; 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Mon, 24 Feb 2025 19:14:03 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id DFB6E40075; Mon, 24 Feb 2025 19:12:29 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node6.st.com [10.75.129.135]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 0555D5469A3; Mon, 24 Feb 2025 19:02:34 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE6.st.com (10.75.129.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:33 +0100 Received: from localhost (10.252.23.75) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:33 +0100 From: Fabrice Gasnier To: , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH 5/8] pwm: stm32-lp: add support for stm32mp25 Date: Mon, 24 Feb 2025 19:01:47 +0100 Message-ID: <20250224180150.3689638-6-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> References: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.23.75] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-24_09,2025-02-24_02,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250224_101410_246408_61BBFCCB X-CRM114-Status: GOOD ( 29.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for STM32MP25 SoC. Use newly introduced compatible to handle new features along with registers and bits diversity. New dedicated capture/compare channels has been added: e.g. a new compare register for channel 2. Some controls (polarity / cc channel enable) are handled in CCMR register on this new variant (instead of wavepol bit). So, Low-power timer can now have up to two PWM outputs. Use device data from the MFD parent to configure the number of PWM channels e.g. 'npwm'. Update current get_state() and apply() ops to support either: - one PWM channel (as on older revision, or LPTIM5 on STM32MP25) - two PWM channels (e.g. LPTIM1/2/3/4 on STM32MP25 that has the full feature set) Introduce new routines to manage common prescaler, reload register and global enable bit. Signed-off-by: Fabrice Gasnier --- drivers/pwm/pwm-stm32-lp.c | 220 ++++++++++++++++++++++++++++++++----- 1 file changed, 194 insertions(+), 26 deletions(-) diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c index 5832dce8ed9d..cdbc31bedfcf 100644 --- a/drivers/pwm/pwm-stm32-lp.c +++ b/drivers/pwm/pwm-stm32-lp.c @@ -20,6 +20,7 @@ struct stm32_pwm_lp { struct clk *clk; struct regmap *regmap; + unsigned int num_cc_chans; }; static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip) @@ -30,13 +31,101 @@ static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip) /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */ #define STM32_LPTIM_MAX_PRESCALER 128 +static int stm32_pwm_lp_update_allowed(struct stm32_pwm_lp *priv, int channel) +{ + int ret; + u32 ccmr1; + unsigned long ccmr; + + /* Only one PWM on this LPTIMER: enable, prescaler and reload value can be changed */ + if (!priv->num_cc_chans) + return true; + + ret = regmap_read(priv->regmap, STM32MP25_LPTIM_CCMR1, &ccmr1); + if (ret) + return ret; + ccmr = ccmr1 & (STM32MP25_LPTIM_CC1E | STM32MP25_LPTIM_CC2E); + + /* More than one channel enabled: enable, prescaler or ARR value can't be changed */ + if (bitmap_weight(&ccmr, sizeof(u32) * BITS_PER_BYTE) > 1) + return false; + + /* + * Only one channel is enabled (or none): check status on the other channel, to + * report if enable, prescaler or ARR value can be changed. + */ + if (channel) + return !(ccmr1 & STM32MP25_LPTIM_CC1E); + else + return !(ccmr1 & STM32MP25_LPTIM_CC2E); +} + +static int stm32_pwm_lp_compare_channel_apply(struct stm32_pwm_lp *priv, int channel, + bool enable, enum pwm_polarity polarity) +{ + u32 ccmr1, val, mask; + bool reenable; + int ret; + + /* No dedicated CC channel: nothing to do */ + if (!priv->num_cc_chans) + return 0; + + ret = regmap_read(priv->regmap, STM32MP25_LPTIM_CCMR1, &ccmr1); + if (ret) + return ret; + + if (channel) { + /* Must disable CC channel (CCxE) to modify polarity (CCxP), then re-enable */ + reenable = (enable && FIELD_GET(STM32MP25_LPTIM_CC2E, ccmr1)) && + (polarity != FIELD_GET(STM32MP25_LPTIM_CC2P, ccmr1)); + + mask = STM32MP25_LPTIM_CC2SEL | STM32MP25_LPTIM_CC2E | STM32MP25_LPTIM_CC2P; + val = FIELD_PREP(STM32MP25_LPTIM_CC2P, polarity); + val |= FIELD_PREP(STM32MP25_LPTIM_CC2E, enable); + } else { + reenable = (enable && FIELD_GET(STM32MP25_LPTIM_CC1E, ccmr1)) && + (polarity != FIELD_GET(STM32MP25_LPTIM_CC1P, ccmr1)); + + mask = STM32MP25_LPTIM_CC1SEL | STM32MP25_LPTIM_CC1E | STM32MP25_LPTIM_CC1P; + val = FIELD_PREP(STM32MP25_LPTIM_CC1P, polarity); + val |= FIELD_PREP(STM32MP25_LPTIM_CC1E, enable); + } + + if (reenable) { + u32 cfgr, presc; + unsigned long rate; + unsigned int delay_us; + + ret = regmap_update_bits(priv->regmap, STM32MP25_LPTIM_CCMR1, + channel ? STM32MP25_LPTIM_CC2E : STM32MP25_LPTIM_CC1E, 0); + if (ret) + return ret; + /* + * After a write to the LPTIM_CCMRx register, a new write operation can only be + * performed after a delay of at least (PRESC × 3) clock cycles + */ + ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); + if (ret) + return ret; + presc = FIELD_GET(STM32_LPTIM_PRESC, cfgr); + rate = clk_get_rate(priv->clk) >> presc; + if (!rate) + return -EINVAL; + delay_us = 3 * DIV_ROUND_UP(USEC_PER_SEC, rate); + usleep_range(delay_us, delay_us * 2); + } + + return regmap_update_bits(priv->regmap, STM32MP25_LPTIM_CCMR1, mask, val); +} + static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_state *state) { struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); unsigned long long prd, div, dty; struct pwm_state cstate; - u32 val, mask, cfgr, presc = 0; + u32 arr, val, mask, cfgr, presc = 0; bool reenable; int ret; @@ -45,10 +134,28 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, if (!state->enabled) { if (cstate.enabled) { - /* Disable LP timer */ - ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); + /* Disable CC channel if any */ + ret = stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, false, + state->polarity); if (ret) return ret; + ret = regmap_write(priv->regmap, pwm->hwpwm ? + STM32MP25_LPTIM_CCR2 : STM32_LPTIM_CMP, 0); + if (ret) + return ret; + + /* Check if the timer can be disabled */ + ret = stm32_pwm_lp_update_allowed(priv, pwm->hwpwm); + if (ret < 0) + return ret; + + if (ret) { + /* Disable LP timer */ + ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); + if (ret) + return ret; + } + /* disable clock to PWM counter */ clk_disable(priv->clk); } @@ -79,6 +186,23 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, dty = prd * state->duty_cycle; do_div(dty, state->period); + ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); + if (ret) + return ret; + + /* + * When there are several channels, they share the same prescaler and reload value. + * Check if this can be changed, or the values are the same for all channels. + */ + if (!stm32_pwm_lp_update_allowed(priv, pwm->hwpwm)) { + ret = regmap_read(priv->regmap, STM32_LPTIM_ARR, &arr); + if (ret) + return ret; + + if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || (arr != prd - 1)) + return -EBUSY; + } + if (!cstate.enabled) { /* enable clock to drive PWM counter */ ret = clk_enable(priv->clk); @@ -86,15 +210,20 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, return ret; } - ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); - if (ret) - goto err; - if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || - (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) { + ((FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity) && !priv->num_cc_chans)) { val = FIELD_PREP(STM32_LPTIM_PRESC, presc); - val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); - mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL; + mask = STM32_LPTIM_PRESC; + + if (!priv->num_cc_chans) { + /* + * WAVPOL bit is only available when no capature compare channel is used, + * e.g. on LPTIMER instances that have only one output channel. CCMR1 is + * used otherwise. + */ + val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); + mask |= STM32_LPTIM_WAVPOL; + } /* Must disable LP timer to modify CFGR */ reenable = true; @@ -120,20 +249,27 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, if (ret) goto err; - ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty)); + /* Write CMP/CCRx register and ensure it's been properly written */ + ret = regmap_write(priv->regmap, pwm->hwpwm ? STM32MP25_LPTIM_CCR2 : STM32_LPTIM_CMP, + prd - (1 + dty)); if (ret) goto err; - /* ensure CMP & ARR registers are properly written */ - ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, + /* ensure ARR and CMP/CCRx registers are properly written */ + ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, pwm->hwpwm ? + (val & STM32_LPTIM_CMP2_ARROK) == STM32_LPTIM_CMP2_ARROK : (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK, 100, 1000); if (ret) { dev_err(pwmchip_parent(chip), "ARR/CMP registers write issue\n"); goto err; } - ret = regmap_write(priv->regmap, STM32_LPTIM_ICR, - STM32_LPTIM_CMPOKCF_ARROKCF); + ret = regmap_write(priv->regmap, STM32_LPTIM_ICR, pwm->hwpwm ? + STM32_LPTIM_CMP2OKCF_ARROKCF : STM32_LPTIM_CMPOKCF_ARROKCF); + if (ret) + goto err; + + ret = stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, true, state->polarity); if (ret) goto err; @@ -161,11 +297,22 @@ static int stm32_pwm_lp_get_state(struct pwm_chip *chip, { struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); unsigned long rate = clk_get_rate(priv->clk); - u32 val, presc, prd; + u32 val, presc, prd, ccmr1; + bool enabled; u64 tmp; regmap_read(priv->regmap, STM32_LPTIM_CR, &val); - state->enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val); + enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val); + if (priv->num_cc_chans) { + /* There's a CC chan, need to also check if it's enabled */ + regmap_read(priv->regmap, STM32MP25_LPTIM_CCMR1, &ccmr1); + if (pwm->hwpwm) + enabled &= !!FIELD_GET(STM32MP25_LPTIM_CC2E, ccmr1); + else + enabled &= !!FIELD_GET(STM32MP25_LPTIM_CC1E, ccmr1); + } + state->enabled = enabled; + /* Keep PWM counter clock refcount in sync with PWM initial state */ if (state->enabled) { int ret = clk_enable(priv->clk); @@ -176,14 +323,21 @@ static int stm32_pwm_lp_get_state(struct pwm_chip *chip, regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val); presc = FIELD_GET(STM32_LPTIM_PRESC, val); - state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val); + if (priv->num_cc_chans) { + if (pwm->hwpwm) + state->polarity = FIELD_GET(STM32MP25_LPTIM_CC2P, ccmr1); + else + state->polarity = FIELD_GET(STM32MP25_LPTIM_CC1P, ccmr1); + } else { + state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val); + } regmap_read(priv->regmap, STM32_LPTIM_ARR, &prd); tmp = prd + 1; tmp = (tmp << presc) * NSEC_PER_SEC; state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); - regmap_read(priv->regmap, STM32_LPTIM_CMP, &val); + regmap_read(priv->regmap, pwm->hwpwm ? STM32MP25_LPTIM_CCR2 : STM32_LPTIM_CMP, &val); tmp = prd - val; tmp = (tmp << presc) * NSEC_PER_SEC; state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); @@ -201,15 +355,25 @@ static int stm32_pwm_lp_probe(struct platform_device *pdev) struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent); struct stm32_pwm_lp *priv; struct pwm_chip *chip; + unsigned int npwm; int ret; - chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*priv)); + if (!ddata->num_cc_chans) { + /* No dedicated CC channel, so there's only one PWM channel */ + npwm = 1; + } else { + /* There are dedicated CC channels, each with one PWM output */ + npwm = ddata->num_cc_chans; + } + + chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*priv)); if (IS_ERR(chip)) return PTR_ERR(chip); priv = to_stm32_pwm_lp(chip); priv->regmap = ddata->regmap; priv->clk = ddata->clk; + priv->num_cc_chans = ddata->num_cc_chans; chip->ops = &stm32_pwm_lp_ops; ret = devm_pwmchip_add(&pdev->dev, chip); @@ -225,12 +389,15 @@ static int stm32_pwm_lp_suspend(struct device *dev) { struct pwm_chip *chip = dev_get_drvdata(dev); struct pwm_state state; - - pwm_get_state(&chip->pwms[0], &state); - if (state.enabled) { - dev_err(dev, "The consumer didn't stop us (%s)\n", - chip->pwms[0].label); - return -EBUSY; + unsigned int i; + + for (i = 0; i < chip->npwm; i++) { + pwm_get_state(&chip->pwms[i], &state); + if (state.enabled) { + dev_err(dev, "The consumer didn't stop us (%s)\n", + chip->pwms[i].label); + return -EBUSY; + } } return pinctrl_pm_select_sleep_state(dev); @@ -246,6 +413,7 @@ static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_lp_pm_ops, stm32_pwm_lp_suspend, static const struct of_device_id stm32_pwm_lp_of_match[] = { { .compatible = "st,stm32-pwm-lp", }, + { .compatible = "st,stm32mp25-pwm-lp", }, {}, }; MODULE_DEVICE_TABLE(of, stm32_pwm_lp_of_match); From patchwork Mon Feb 24 18:01:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 13988705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 067EBC021A4 for ; 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Mon, 24 Feb 2025 19:14:00 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id E45A340076; Mon, 24 Feb 2025 19:12:29 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node5.st.com [10.75.129.134]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C70D35461C4; Mon, 24 Feb 2025 19:02:34 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE5.st.com (10.75.129.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:34 +0100 Received: from localhost (10.252.23.75) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:34 +0100 From: Fabrice Gasnier To: , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH 6/8] counter: stm32-lptimer-cnt: add support for stm32mp25 Date: Mon, 24 Feb 2025 19:01:48 +0100 Message-ID: <20250224180150.3689638-7-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> References: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.23.75] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-24_09,2025-02-24_02,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250224_101408_213358_D97D9F84 X-CRM114-Status: GOOD ( 10.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for STM32MP25 SoC. Use newly introduced compatible to handle this new HW variant, even if no major change is expected on the counter driver. Signed-off-by: Fabrice Gasnier --- drivers/counter/stm32-lptimer-cnt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/counter/stm32-lptimer-cnt.c b/drivers/counter/stm32-lptimer-cnt.c index b249c8647639..a5dce017c37b 100644 --- a/drivers/counter/stm32-lptimer-cnt.c +++ b/drivers/counter/stm32-lptimer-cnt.c @@ -508,6 +508,7 @@ static SIMPLE_DEV_PM_OPS(stm32_lptim_cnt_pm_ops, stm32_lptim_cnt_suspend, static const struct of_device_id stm32_lptim_cnt_of_match[] = { { .compatible = "st,stm32-lptimer-counter", }, + { .compatible = "st,stm32mp25-lptimer-counter", }, {}, }; MODULE_DEVICE_TABLE(of, stm32_lptim_cnt_of_match); From patchwork Mon Feb 24 18:01:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 13988776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3113EC021A4 for ; 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Mon, 24 Feb 2025 19:16:32 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id EA81340078; Mon, 24 Feb 2025 19:12:29 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node4.st.com [10.75.129.133]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id AF5DB546D7A; Mon, 24 Feb 2025 19:02:35 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE4.st.com (10.75.129.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:35 +0100 Received: from localhost (10.252.23.75) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:35 +0100 From: Fabrice Gasnier To: , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH 7/8] arm64: defconfig: enable STM32 LP timers drivers Date: Mon, 24 Feb 2025 19:01:49 +0100 Message-ID: <20250224180150.3689638-8-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> References: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.23.75] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-24_09,2025-02-24_02,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250224_102147_030359_5B37F894 X-CRM114-Status: UNSURE ( 8.87 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable the STM32 timer drivers: MFD, counter, PWM and trigger as modules. Clocksource is a bool, hence set to y. These drivers can be used on STM32MP25. Signed-off-by: Fabrice Gasnier --- arch/arm64/configs/defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 1f25423de383..952eee30f21c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -775,6 +775,7 @@ CONFIG_MFD_TI_LP873X=m CONFIG_MFD_TPS65219=y CONFIG_MFD_TPS6594_I2C=m CONFIG_MFD_ROHM_BD718XX=y +CONFIG_MFD_STM32_LPTIMER=m CONFIG_MFD_WCD934X=m CONFIG_MFD_KHADAS_MCU=m CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -1401,6 +1402,7 @@ CONFIG_CLK_RENESAS_VBATTB=m CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_TEGRA186_TIMER=y +CONFIG_CLKSRC_STM32_LP=y CONFIG_RENESAS_OSTM=y CONFIG_ARM_MHU=y CONFIG_IMX_MBOX=y @@ -1526,6 +1528,7 @@ CONFIG_IIO_CROS_EC_LIGHT_PROX=m CONFIG_SENSORS_ISL29018=m CONFIG_VCNL4000=m CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_STM32_LPTIMER_TRIGGER=m CONFIG_IIO_CROS_EC_BARO=m CONFIG_MPL3115=m CONFIG_PWM=y @@ -1543,6 +1546,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_PWM_RZ_MTU3=m CONFIG_PWM_SAMSUNG=y CONFIG_PWM_SL28CPLD=m +CONFIG_PWM_STM32_LP=m CONFIG_PWM_SUN4I=m CONFIG_PWM_TEGRA=m CONFIG_PWM_TIECAP=m @@ -1682,6 +1686,7 @@ CONFIG_INTERCONNECT_QCOM_SM8750=y CONFIG_INTERCONNECT_QCOM_X1E80100=y CONFIG_COUNTER=m CONFIG_RZ_MTU3_CNT=m +CONFIG_STM32_LPTIMER_CNT=m CONFIG_HTE=y CONFIG_HTE_TEGRA194=y CONFIG_HTE_TEGRA194_TEST=m From patchwork Mon Feb 24 18:01:50 2025 Content-Type: text/plain; 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Mon, 24 Feb 2025 19:02:36 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE6.st.com (10.75.129.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:36 +0100 Received: from localhost (10.252.23.75) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 19:02:36 +0100 From: Fabrice Gasnier To: , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH 8/8] arm64: dts: st: add low-power timer nodes on stm32mp251 Date: Mon, 24 Feb 2025 19:01:50 +0100 Message-ID: <20250224180150.3689638-9-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> References: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.23.75] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-24_09,2025-02-24_02,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250224_101948_709923_3D0E0EFE X-CRM114-Status: UNSURE ( 9.54 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add low-power timer (LPTimer) support on STM32MP25 SoC. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features (no capture/compare) channel. Still, LPTIM5 can be used as single PWM, counter, trigger or timer. Signed-off-by: Fabrice Gasnier --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 177 +++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index f3c6cdfd7008..742367e4f16d 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -238,6 +238,78 @@ rifsc: bus@42080000 { #access-controller-cells = <1>; ranges; + lptimer1: timer@40090000 { + compatible = "st,stm32mp25-lptimer"; + reg = <0x40090000 0x400>; + interrupts-extended = <&exti1 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_LPTIM1>; + clock-names = "mux"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 17>; + power-domains = <&RET_PD>; + wakeup-source; + status = "disabled"; + + counter { + compatible = "st,stm32mp25-lptimer-counter"; + status = "disabled"; + }; + + pwm { + compatible = "st,stm32mp25-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32mp25-lptimer-timer"; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32mp25-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + }; + + lptimer2: timer@400a0000 { + compatible = "st,stm32mp25-lptimer"; + reg = <0x400a0000 0x400>; + interrupts-extended = <&exti1 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_LPTIM2>; + clock-names = "mux"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 18>; + power-domains = <&RET_PD>; + wakeup-source; + status = "disabled"; + + counter { + compatible = "st,stm32mp25-lptimer-counter"; + status = "disabled"; + }; + + pwm { + compatible = "st,stm32mp25-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32mp25-lptimer-timer"; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32mp25-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + }; + i2s2: audio-controller@400b0000 { compatible = "st,stm32mp25-i2s"; reg = <0x400b0000 0x400>; @@ -799,6 +871,111 @@ i2c8: i2c@46040000 { status = "disabled"; }; + lptimer3: timer@46050000 { + compatible = "st,stm32mp25-lptimer"; + reg = <0x46050000 0x400>; + interrupts-extended = <&exti2 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_LPTIM3>; + clock-names = "mux"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 19>; + wakeup-source; + status = "disabled"; + + counter { + compatible = "st,stm32mp25-lptimer-counter"; + status = "disabled"; + }; + + pwm { + compatible = "st,stm32mp25-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32mp25-lptimer-timer"; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32mp25-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + lptimer4: timer@46060000 { + compatible = "st,stm32mp25-lptimer"; + reg = <0x46060000 0x400>; + interrupts-extended = <&exti2 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_LPTIM4>; + clock-names = "mux"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 20>; + wakeup-source; + status = "disabled"; + + counter { + compatible = "st,stm32mp25-lptimer-counter"; + status = "disabled"; + }; + + pwm { + compatible = "st,stm32mp25-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32mp25-lptimer-timer"; + status = "disabled"; + }; + + trigger@3 { + compatible = "st,stm32mp25-lptimer-trigger"; + reg = <3>; + status = "disabled"; + }; + }; + + lptimer5: timer@46070000 { + compatible = "st,stm32mp25-lptimer"; + reg = <0x46070000 0x400>; + interrupts-extended = <&exti2 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_LPTIM5>; + clock-names = "mux"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 21>; + wakeup-source; + status = "disabled"; + + counter { + compatible = "st,stm32mp25-lptimer-counter"; + status = "disabled"; + }; + + pwm { + compatible = "st,stm32mp25-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32mp25-lptimer-timer"; + status = "disabled"; + }; + + trigger@4 { + compatible = "st,stm32mp25-lptimer-trigger"; + reg = <4>; + status = "disabled"; + }; + }; + csi: csi@48020000 { compatible = "st,stm32mp25-csi"; reg = <0x48020000 0x2000>;