From patchwork Tue Feb 25 12:56:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 13990004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87B45C021BB for ; Tue, 25 Feb 2025 13:18:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:In-Reply-To:References:Message-Id: MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vqHW/at71zs1jtKNIXOf6XImu9cMo2FnbsdAAt3d2KA=; b=lLaoHUFQgM+CBh v3U2xQo+XBnMln88V+HVGXE5hECrQ4pe+giWGB9jxYM+8/zcFUmZPYFXYz3O4z+jOiVSH4FypkxeR /7SHk+BBFeYyvsBZR2y9hJ9qpi9r5/fllXmpc5FARKzxFXGr4t8p7ijtLtfDclZE8fc15HnRDrQPj quBYrnnXJIFwomzLRdW1xG4mRWyRl6AG4fHVGtc/mePWXwJzgrXGGSTVmLlkm5NKTYO2NdTcWt4Zz /3rZuVFbd85dx0XddU+RyXrN35S03SwpS38D67ftqbGZ4ftDAVTySqhtrd/4Yn8VaQahQfpUbXsrz b6XRKfJqgZCcqnPfa9GQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tmuoz-0000000HLJM-1bzD; Tue, 25 Feb 2025 13:18:01 +0000 Received: from sender4-op-o14.zoho.com ([136.143.188.14]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tmuVL-0000000HHMO-3Q3Z; Tue, 25 Feb 2025 12:57:44 +0000 ARC-Seal: i=1; a=rsa-sha256; t=1740488248; cv=none; d=zohomail.com; s=zohoarc; b=lmcXg71Tfat+hgjWvLhShXas9QGFsvlWYt6HKtso735A8hdFlY7syJ2e0onyCR4aGj1YfjHOC8SucKM0+mOwIUJ97KRkHeypbiGl8kCgogRl5AhPXiiB7Cx1i0zU26BOeChFfNI+QOhWLUCBoIqwq7H5H0RXt6F4Dt2tesQq/p0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740488248; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=cWGtW43TgLnA9XLRjmVYZyHmW1immnR6brlslYhRp80=; b=mfohuTo97wtGhA6gUQ1s94iiCJzuNmrWxs5mbI13B8q59JmL36ihXBJFQKFA1tJFmBX9QEkpYd+DV29yr4fMM3Le80U8hGxXVhoaoePRH5GTwaYJs2aQT9i4foK1FA5hpXJhI0ai38N3UhVmoeDXRpIPRgD0a8kCO1emP3tkqq8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1740488248; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=cWGtW43TgLnA9XLRjmVYZyHmW1immnR6brlslYhRp80=; b=GTNrD93eBrF+xM9lAwCtYSod3XyhAMdx8D0mEBbrXSXRDEgy5QnGk0eIpXX1xh6S WkhGiLaeK+m+VuJrp9glWvadYUOMdeEswTiH7Kn07gxPl63c9NnybeCduhz1sh3yR1P KfaZ2ofWjVzkOunW+M7BApYr3UT00J+FRTEJ+6NU= Received: by mx.zohomail.com with SMTPS id 174048824766496.17668398054809; Tue, 25 Feb 2025 04:57:27 -0800 (PST) From: Nicolas Frattaroli Date: Tue, 25 Feb 2025 13:56:44 +0100 Subject: [PATCH v2 1/6] dt-bindings: rockchip-thermal: Add RK3576 compatible MIME-Version: 1.0 Message-Id: <20250225-rk3576-tsadc-upstream-v2-1-6eb7b00de89c@collabora.com> References: <20250225-rk3576-tsadc-upstream-v2-0-6eb7b00de89c@collabora.com> In-Reply-To: <20250225-rk3576-tsadc-upstream-v2-0-6eb7b00de89c@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250225_045743_933327_52C157C6 X-CRM114-Status: UNSURE ( 8.07 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add a new compatible for the thermal sensor device on the RK3576 SoC. Acked-by: Rob Herring (Arm) Signed-off-by: Nicolas Frattaroli --- Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index b717ea8261ca24ebaf709f410ec6372de1366b8a..49ceed68c92ce5a32ed8d4f39bd88fd052de0e80 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -21,6 +21,7 @@ properties: - rockchip,rk3368-tsadc - rockchip,rk3399-tsadc - rockchip,rk3568-tsadc + - rockchip,rk3576-tsadc - rockchip,rk3588-tsadc - rockchip,rv1108-tsadc From patchwork Tue Feb 25 12:56:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 13990005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BDAE2C021B2 for ; Tue, 25 Feb 2025 13:19:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:In-Reply-To:References:Message-Id: MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=h4B8oMKJbnKaiyXCyvMfZIgWNJt5DE7q/soYJw2Q3VE=; b=saqndd/qjInNlm Rh5IXlSjebywhQwsR8fSgD8g46FYrrArmrZ+m+GiU0xa7zMtI8m+XQegwL3X01GEqofQ9FDpUU78A 6IuyFXpnUQl4i1AS88yQpQJ0TBxD9PULTp1H9WO0Qo7SfkJqMc6tsD4T1NOLbVY1OoxNJECRriP40 yXgUb2OUjhQEwVWtS1icrooumyjE6743dl4q7a7BXYwnanjD71PuUTcWSFcLPC9WhtCvPMW3GhxsJ 898rxwjhAIO5b9d+VSEAvZ6gRF9lK3BrJUyPIGgJq9Fr4pTuIwftb6jZ2qgVsZzD+fGf/Ekd2i2rh XKy0e08YMaGp/E0xC1Dg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tmuqV-0000000HLjx-2F4k; Tue, 25 Feb 2025 13:19:35 +0000 Received: from sender4-op-o14.zoho.com ([136.143.188.14]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tmuVS-0000000HHNN-13EV; Tue, 25 Feb 2025 12:57:51 +0000 ARC-Seal: i=1; a=rsa-sha256; t=1740488254; cv=none; d=zohomail.com; s=zohoarc; b=Ua+9tCYwG/uB6WGs5Sr/hzyGoN8CWc+3LwZHQcmqbCzSPU4mNKXWHDTdOiZjF+rvJWwZCHnZy/Y/6nYVem3n4IVJhfJAOGiRv31mcLEU9R8QMnNg8BtBgoFun0tNRsi7+8G5eGmtDzW2QMmklMoOabWfKOCZYdtVNHjzwK0+1wQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740488254; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=yfVTwFHvZdZu0eKKCEjQDIGP9pYsfyaqZxy/3PBlt/w=; b=I+iPnB6pMsE2SbMkLHqMMdUa4iWlD43Ez01WzjZ2ETG+XFzSC/wFEtiFOR3ahnGV9utTvMt/WfXCQ1JTTnwxYsPHv9vfDAwJpd3iltOvEBeVrTqSl0QLA4Wi1t8d3rstGCn3sCarS8YpSzfMy7MlRHynyBozi88dSvzvBT/4TIc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1740488254; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=yfVTwFHvZdZu0eKKCEjQDIGP9pYsfyaqZxy/3PBlt/w=; b=Fh45I8HSEPQnvmTWXiUVK+gEDICRjjBpISjLf1LpaUDg4id2Uvsps0qi+X/NISBN fgSOZvhX4sScYn0AzZ3/LNAP2XHlVAnmIeKUpe9N+bEMuLWWEaELi4426AZauyR5DiU /CSolbpqeGs6U4b8N5lbNXAxiEmFnA57sb//Opds= Received: by mx.zohomail.com with SMTPS id 1740488252056786.637016868865; Tue, 25 Feb 2025 04:57:32 -0800 (PST) From: Nicolas Frattaroli Date: Tue, 25 Feb 2025 13:56:45 +0100 Subject: [PATCH v2 2/6] arm64: dts: rockchip: Add thermal nodes to RK3576 MIME-Version: 1.0 Message-Id: <20250225-rk3576-tsadc-upstream-v2-2-6eb7b00de89c@collabora.com> References: <20250225-rk3576-tsadc-upstream-v2-0-6eb7b00de89c@collabora.com> In-Reply-To: <20250225-rk3576-tsadc-upstream-v2-0-6eb7b00de89c@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250225_045750_360257_68EE5122 X-CRM114-Status: GOOD ( 13.46 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add the TSADC node to the RK3576. Additionally, add everything the TSADC needs to function, i.e. thermal zones, their trip points and maps, as well as adjust the CPU cooling-cells property. The polling-delay properties are set to 0 as we do have interrupts for this TSADC on this particular SoC. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 164 ++++++++++++++++++++++++++++++- 1 file changed, 162 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index db4be536918a69f6a9187bb14c43e7809e2d4678..6603f442674c09d017a256bc272e33a2fea7cb8d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3576"; @@ -113,9 +114,9 @@ cpu_l0: cpu@0 { capacity-dmips-mhz = <485>; clocks = <&scmi_clk ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; - #cooling-cells = <2>; dynamic-power-coefficient = <120>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l1: cpu@1 { @@ -127,6 +128,7 @@ cpu_l1: cpu@1 { clocks = <&scmi_clk ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l2: cpu@2 { @@ -138,6 +140,7 @@ cpu_l2: cpu@2 { clocks = <&scmi_clk ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l3: cpu@3 { @@ -149,6 +152,7 @@ cpu_l3: cpu@3 { clocks = <&scmi_clk ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b0: cpu@100 { @@ -159,9 +163,9 @@ cpu_b0: cpu@100 { capacity-dmips-mhz = <1024>; clocks = <&scmi_clk ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; - #cooling-cells = <2>; dynamic-power-coefficient = <320>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b1: cpu@101 { @@ -173,6 +177,7 @@ cpu_b1: cpu@101 { clocks = <&scmi_clk ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b2: cpu@102 { @@ -184,6 +189,7 @@ cpu_b2: cpu@102 { clocks = <&scmi_clk ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b3: cpu@103 { @@ -195,6 +201,7 @@ cpu_b3: cpu@103 { clocks = <&scmi_clk ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; idle-states { @@ -431,6 +438,143 @@ psci { method = "smc"; }; + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + /* sensor for cluster1 (big Cortex-A72 cores) */ + bigcore_thermal: bigcore-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 1>; + + trips { + bigcore_alert: bigcore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + bigcore_crit: bigcore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&bigcore_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor for cluster0 (little Cortex-A53 cores) */ + littlecore_thermal: littlecore-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 2>; + + trips { + littlecore_alert: littlecore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + littlecore_crit: littlecore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&littlecore_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 3>; + + trips { + gpu_alert: gpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 4>; + + trips { + npu_crit: npu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr_thermal: ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { + ddr_crit: ddr-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -1718,6 +1862,22 @@ saradc: adc@2ae00000 { status = "disabled"; }; + tsadc: tsadc@2ae70000 { + compatible = "rockchip,rk3576-tsadc"; + reg = <0x0 0x2ae70000 0x0 0x400>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names = "tsadc-apb", "tsadc"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + }; + i2c9: i2c@2ae80000 { compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0x2ae80000 0x0 0x1000>; From patchwork Tue Feb 25 12:56:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 13990011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B862C021B2 for ; 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dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1740488258; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=k7eNk5qHMFWPJbC7DgO4/o0LboHoTT+Aabq56bbGgPE=; b=goPqZOElyNYrdeEpebC74lPoJlQVYRpKUROR2QYNAc7RyQfZjVYcP4fnc4R6r2BB Qg+uGlpp6QZEn98l01EppOH/yWywtkWBh75qDpPlSgQgJba2qGtK/F/aFvwueu/iIHV 98UST+ls+9ckfZ6cbW5Za+EcMdTyFk/PfYM/huyQ= Received: by mx.zohomail.com with SMTPS id 1740488256566382.5081815102708; Tue, 25 Feb 2025 04:57:36 -0800 (PST) From: Nicolas Frattaroli Date: Tue, 25 Feb 2025 13:56:46 +0100 Subject: [PATCH v2 3/6] thermal: rockchip: Support RK3576 SoC in the thermal driver MIME-Version: 1.0 Message-Id: <20250225-rk3576-tsadc-upstream-v2-3-6eb7b00de89c@collabora.com> References: <20250225-rk3576-tsadc-upstream-v2-0-6eb7b00de89c@collabora.com> In-Reply-To: <20250225-rk3576-tsadc-upstream-v2-0-6eb7b00de89c@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250225_045751_962291_667FA4C6 X-CRM114-Status: GOOD ( 11.84 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ye Zhang , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Ye Zhang The RK3576 SoC has six TS-ADC channels: TOP, BIG_CORE, LITTLE_CORE, DDR, NPU and GPU. Signed-off-by: Ye Zhang [ported to mainline, reworded commit message] Signed-off-by: Nicolas Frattaroli --- drivers/thermal/rockchip_thermal.c | 42 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index a8ad85feb68fbb7ec8d79602b16c47838ecb3c00..bec1930bebd87859a7e519cfc9f05e10b1c31e87 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -1061,6 +1061,22 @@ static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs, writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); } +static void rk_tsadcv4_tshut_mode(int chn, void __iomem *regs, + enum tshut_mode mode) +{ + u32 val_gpio, val_cru; + + if (mode == TSHUT_MODE_GPIO) { + val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); + val_cru = TSADCV2_INT_SRC_EN_MASK(chn); + } else { + val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); + val_gpio = TSADCV2_INT_SRC_EN_MASK(chn); + } + writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN); + writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); +} + static const struct rockchip_tsadc_chip px30_tsadc_data = { /* cpu, gpu */ .chn_offset = 0, @@ -1284,6 +1300,28 @@ static const struct rockchip_tsadc_chip rk3568_tsadc_data = { }, }; +static const struct rockchip_tsadc_chip rk3576_tsadc_data = { + /* top, big_core, little_core, ddr, npu, gpu */ + .chn_offset = 0, + .chn_num = 6, /* six channels for tsadc */ + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp = 95000, + .initialize = rk_tsadcv8_initialize, + .irq_ack = rk_tsadcv4_irq_ack, + .control = rk_tsadcv4_control, + .get_temp = rk_tsadcv4_get_temp, + .set_alarm_temp = rk_tsadcv3_alarm_temp, + .set_tshut_temp = rk_tsadcv3_tshut_temp, + .set_tshut_mode = rk_tsadcv4_tshut_mode, + .table = { + .id = rk3588_code_table, + .length = ARRAY_SIZE(rk3588_code_table), + .data_mask = TSADCV4_DATA_MASK, + .mode = ADC_INCREMENT, + }, +}; + static const struct rockchip_tsadc_chip rk3588_tsadc_data = { /* top, big_core0, big_core1, little_core, center, gpu, npu */ .chn_offset = 0, @@ -1342,6 +1380,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = { .compatible = "rockchip,rk3568-tsadc", .data = (void *)&rk3568_tsadc_data, }, + { + .compatible = "rockchip,rk3576-tsadc", + .data = (void *)&rk3576_tsadc_data, + }, { .compatible = "rockchip,rk3588-tsadc", .data = (void *)&rk3588_tsadc_data, From patchwork Tue Feb 25 12:56:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 13990012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0B3CC021B2 for ; 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dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1740488262; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=x9lTs8zXN5HalN7kcYVDsFMxl6BV5hMT6pLsKxt4ZeQ=; b=LDDLBueTingfhbtiiCg7jZavcUthN75wUA6IGG24cjKURtDnz33+LeCmBS1PAKS1 f3cR/YHskcmad/8CdvvLrOhaKyO6/6QB9kKHmruCIo/wGiY3BvtPQzJmyiATLgnXKIw Hs9ONg7CAT/WvWVUwkNrVroUNv3WMBZkDEQvyZE4= Received: by mx.zohomail.com with SMTPS id 1740488260869522.3234869504469; Tue, 25 Feb 2025 04:57:40 -0800 (PST) From: Nicolas Frattaroli Date: Tue, 25 Feb 2025 13:56:47 +0100 Subject: [PATCH v2 4/6] dt-bindings: thermal: rockchip: document otp thermal trim MIME-Version: 1.0 Message-Id: <20250225-rk3576-tsadc-upstream-v2-4-6eb7b00de89c@collabora.com> References: <20250225-rk3576-tsadc-upstream-v2-0-6eb7b00de89c@collabora.com> In-Reply-To: <20250225-rk3576-tsadc-upstream-v2-0-6eb7b00de89c@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250225_045752_640423_86A77B72 X-CRM114-Status: GOOD ( 10.09 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Several Rockchip SoCs, such as the RK3576, can store calibration trim data for thermal sensors in OTP cells. This capability should be documented. Such a rockchip thermal sensor may reference cell handles that store both a chip-wide trim for all the sensors, as well as cell handles for each individual sensor channel pointing to that specific sensor's trim value. Additionally, the thermal sensor may optionally reference cells which store the base in terms of degrees celsius and decicelsius that the trim is relative to. Each SoC that implements this appears to have a slightly different combination of chip-wide trim, base, base fractional part and per-channel trim, so which ones do which is documented in the bindings. Signed-off-by: Nicolas Frattaroli --- .../bindings/thermal/rockchip-thermal.yaml | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index 49ceed68c92ce5a32ed8d4f39bd88fd052de0e80..eef8d2620b675fe2f871a03aebdaed13278e0884 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -11,6 +11,23 @@ maintainers: $ref: thermal-sensor.yaml# +definitions: + channel: + type: object + properties: + reg: + maxItems: 1 + description: sensor ID, a.k.a. channel number + nvmem-cells: + items: + - description: handle of cell containing the calibration data + nvmem-cell-names: + items: + - const: trim + required: + - reg + unevaluatedProperties: false + properties: compatible: enum: @@ -51,6 +68,12 @@ properties: - const: tsadc - const: tsadc-phy + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + "#thermal-sensor-cells": const: 1 @@ -80,6 +103,47 @@ required: - clock-names - resets +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-tsadc + then: + properties: + nvmem-cells: + items: + - description: cell handle to where the trim's base temperature is stored + - description: + cell handle to where the trim's tenths of Celsius base value is stored + nvmem-cell-names: + items: + - const: trim_base + - const: trim_base_frac + cpu@0: + $ref: "#/definitions/channel" + gpu@1: + $ref: "#/definitions/channel" + - if: + properties: + compatible: + contains: + const: rockchip,rk3576-tsadc + then: + properties: + soc@0: + $ref: "#/definitions/channel" + bigcores@1: + $ref: "#/definitions/channel" + littlecores@2: + $ref: "#/definitions/channel" + ddr@3: + $ref: "#/definitions/channel" + npu@4: + $ref: "#/definitions/channel" + gpu@5: + $ref: "#/definitions/channel" + unevaluatedProperties: false examples: From patchwork Tue Feb 25 12:56:48 2025 Content-Type: text/plain; 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Tue, 25 Feb 2025 04:57:45 -0800 (PST) From: Nicolas Frattaroli Date: Tue, 25 Feb 2025 13:56:48 +0100 Subject: [PATCH v2 5/6] arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes MIME-Version: 1.0 Message-Id: <20250225-rk3576-tsadc-upstream-v2-5-6eb7b00de89c@collabora.com> References: <20250225-rk3576-tsadc-upstream-v2-0-6eb7b00de89c@collabora.com> In-Reply-To: <20250225-rk3576-tsadc-upstream-v2-0-6eb7b00de89c@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250225_045757_322720_A9BFEEC8 X-CRM114-Status: GOOD ( 10.35 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Thanks to Heiko's work getting OTP working on the RK3576, we can specify the thermal sensor trim values which are stored there now, and with my driver addition to rockchip_thermal, we can make use of these. Add them to the devicetree for the SoC. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 57 ++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 6603f442674c09d017a256bc272e33a2fea7cb8d..e7ce707e6339bcdddb2914eb7e0ed8269275c679 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1465,6 +1465,30 @@ gpu_leakage: gpu-leakage@21 { log_leakage: log-leakage@22 { reg = <0x22 0x1>; }; + bigcore_tsadc_trim: bigcore-tsadc-trim@24 { + reg = <0x24 0x2>; + bits = <0 10>; + }; + litcore_tsadc_trim: litcore-tsadc-trim@26 { + reg = <0x26 0x2>; + bits = <0 10>; + }; + ddr_tsadc_trim: ddr-tsadc-trim@28 { + reg = <0x28 0x2>; + bits = <0 10>; + }; + npu_tsadc_trim: npu-tsadc-trim@2a { + reg = <0x2a 0x2>; + bits = <0 10>; + }; + gpu_tsadc_trim: gpu-tsadc-trim@2c { + reg = <0x2c 0x2>; + bits = <0 10>; + }; + soc_tsadc_trim: soc-tsadc-trim@64 { + reg = <0x64 0x2>; + bits = <0 10>; + }; }; gic: interrupt-controller@2a701000 { @@ -1876,6 +1900,39 @@ tsadc: tsadc@2ae70000 { rockchip,hw-tshut-temp = <120000>; rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + #address-cells = <1>; + #size-cells = <0>; + + soc@0 { + reg = <0>; + nvmem-cells = <&soc_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + bigcores@1 { + reg = <1>; + nvmem-cells = <&bigcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + littlecores@2 { + reg = <2>; + nvmem-cells = <&litcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + ddr@3 { + reg = <3>; + nvmem-cells = <&ddr_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + npu@4 { + reg = <4>; + nvmem-cells = <&npu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + gpu@5 { + reg = <5>; + nvmem-cells = <&gpu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; }; i2c9: i2c@2ae80000 { From patchwork Tue Feb 25 12:56:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 13990027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59965C021B2 for ; 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dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1740488272; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=2SOERDO8KDpCBQ69jB2lh1eDVl6DUgQ1HkSLtL1Yc8s=; b=PtQRLbPhIyBKSFiBwmDRX9imcNGTsgXGWGalHJ8qGaNAVzwBDdJRwEl5sOYEkX94 6WjvACujXK8Am05hCnc8fzTOkdGvjh02GqGpnN60QQJ8+rRDN6nPLMGEqmhaT4qhMbX BilfbKhSR3YE7oLjDX5ipRkY9PFSn/eBTcjs4pEk= Received: by mx.zohomail.com with SMTPS id 1740488269910474.6868374724553; Tue, 25 Feb 2025 04:57:49 -0800 (PST) From: Nicolas Frattaroli Date: Tue, 25 Feb 2025 13:56:49 +0100 Subject: [PATCH v2 6/6] thermal: rockchip: support reading trim values from OTP MIME-Version: 1.0 Message-Id: <20250225-rk3576-tsadc-upstream-v2-6-6eb7b00de89c@collabora.com> References: <20250225-rk3576-tsadc-upstream-v2-0-6eb7b00de89c@collabora.com> In-Reply-To: <20250225-rk3576-tsadc-upstream-v2-0-6eb7b00de89c@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250225_045803_443580_A5AC75F7 X-CRM114-Status: GOOD ( 33.54 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Many of the Rockchip SoCs support storing trim values for the sensors in factory programmable memory. These values specify a fixed offset from the sensor's returned temperature to get a more accurate picture of what temperature the silicon is actually at. The way this is implemented is with various OTP cells, which may be absent. There may both be whole-TSADC trim values, as well as per-sensor trim values. In the downstream driver, whole-chip trim values override the per-sensor trim values. This rewrite of the functionality changes the semantics to something I see as slightly more useful: allow the whole-chip trim values to serve as a fallback for lacking per-sensor trim values, instead of overriding already present sensor trim values. Additionally, the chip may specify an offset (trim_base, trim_base_frac) in degrees celsius and degrees decicelsius respectively which defines what the basis is from which the trim, if any, should be calculated from. By default, this is 30 degrees Celsius, but the chip can once again specify a different value through OTP cells. The implementation of these trim calculations have been tested extensively on an RK3576, where it was confirmed to get rid of pesky 1.8 degree Celsius offsets between certain sensors. Signed-off-by: Nicolas Frattaroli --- drivers/thermal/rockchip_thermal.c | 221 +++++++++++++++++++++++++++++++++---- 1 file changed, 202 insertions(+), 19 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index bec1930bebd87859a7e519cfc9f05e10b1c31e87..4868ea90237ed8c33666a15c08499024120c79d7 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -69,16 +70,18 @@ struct chip_tsadc_table { * struct rockchip_tsadc_chip - hold the private data of tsadc chip * @chn_offset: the channel offset of the first channel * @chn_num: the channel number of tsadc chip - * @tshut_temp: the hardware-controlled shutdown temperature value + * @trim_slope: used to convert the trim code to a temperature in millicelsius + * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) * @initialize: SoC special initialize tsadc controller method * @irq_ack: clear the interrupt * @control: enable/disable method for the tsadc controller - * @get_temp: get the temperature + * @get_temp: get the raw temperature, unadjusted by trim * @set_alarm_temp: set the high temperature interrupt * @set_tshut_temp: set the hardware-controlled shutdown temperature * @set_tshut_mode: set the hardware-controlled shutdown mode + * @get_trim_code: convert a hardware temperature code to one adjusted for by trim * @table: the chip-specific conversion table */ struct rockchip_tsadc_chip { @@ -86,6 +89,9 @@ struct rockchip_tsadc_chip { int chn_offset; int chn_num; + /* Used to convert trim code to trim temp */ + int trim_slope; + /* The hardware-controlled tshut property */ int tshut_temp; enum tshut_mode tshut_mode; @@ -105,6 +111,8 @@ struct rockchip_tsadc_chip { int (*set_tshut_temp)(const struct chip_tsadc_table *table, int chn, void __iomem *reg, int temp); void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); + int (*get_trim_code)(const struct chip_tsadc_table *table, + int code, int trim_base, int trim_base_frac); /* Per-table methods */ struct chip_tsadc_table table; @@ -114,12 +122,16 @@ struct rockchip_tsadc_chip { * struct rockchip_thermal_sensor - hold the information of thermal sensor * @thermal: pointer to the platform/configuration data * @tzd: pointer to a thermal zone + * @of_node: pointer to the device_node representing this sensor, if any * @id: identifier of the thermal sensor + * @trim_temp: per-sensor trim temperature value */ struct rockchip_thermal_sensor { struct rockchip_thermal_data *thermal; struct thermal_zone_device *tzd; + struct device_node *of_node; int id; + int trim_temp; }; /** @@ -132,7 +144,11 @@ struct rockchip_thermal_sensor { * @pclk: the advanced peripherals bus clock * @grf: the general register file will be used to do static set by software * @regs: the base address of tsadc controller - * @tshut_temp: the hardware-controlled shutdown temperature value + * @trim_base: major component of sensor trim value, in Celsius + * @trim_base_frac: minor component of sensor trim value, in Decicelsius + * @trim: fallback thermal trim value for each channel + * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim + * @trim_temp: the fallback trim temperature for the whole sensor * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) */ @@ -149,7 +165,12 @@ struct rockchip_thermal_data { struct regmap *grf; void __iomem *regs; + int trim_base; + int trim_base_frac; + int trim; + int tshut_temp; + int trim_temp; enum tshut_mode tshut_mode; enum tshut_polarity tshut_polarity; }; @@ -249,6 +270,9 @@ struct rockchip_thermal_data { #define GRF_CON_TSADC_CH_INV (0x10001 << 1) + +#define RK_MAX_TEMP (180000) + /** * struct tsadc_table - code to temperature conversion table * @code: the value of adc channel @@ -1077,6 +1101,15 @@ static void rk_tsadcv4_tshut_mode(int chn, void __iomem *regs, writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); } +static int rk_tsadcv2_get_trim_code(const struct chip_tsadc_table *table, + int code, int trim_base, int trim_base_frac) +{ + int temp = trim_base * 1000 + trim_base_frac * 100; + u32 base_code = rk_tsadcv2_temp_to_code(table, temp); + + return code - base_code; +} + static const struct rockchip_tsadc_chip px30_tsadc_data = { /* cpu, gpu */ .chn_offset = 0, @@ -1314,6 +1347,8 @@ static const struct rockchip_tsadc_chip rk3576_tsadc_data = { .set_alarm_temp = rk_tsadcv3_alarm_temp, .set_tshut_temp = rk_tsadcv3_tshut_temp, .set_tshut_mode = rk_tsadcv4_tshut_mode, + .get_trim_code = rk_tsadcv2_get_trim_code, + .trim_slope = 923, .table = { .id = rk3588_code_table, .length = ARRAY_SIZE(rk3588_code_table), @@ -1429,7 +1464,7 @@ static int rockchip_thermal_set_trips(struct thermal_zone_device *tz, int low, i __func__, sensor->id, low, high); return tsadc->set_alarm_temp(&tsadc->table, - sensor->id, thermal->regs, high); + sensor->id, thermal->regs, high + sensor->trim_temp); } static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_temp) @@ -1441,6 +1476,8 @@ static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_te retval = tsadc->get_temp(&tsadc->table, sensor->id, thermal->regs, out_temp); + *out_temp -= sensor->trim_temp; + return retval; } @@ -1449,6 +1486,104 @@ static const struct thermal_zone_device_ops rockchip_of_thermal_ops = { .set_trips = rockchip_thermal_set_trips, }; +/** + * rockchip_get_efuse_value - read an OTP cell from a device node + * @np: pointer to the device node with the nvmem-cells property + * @cell_name: name of cell that should be read + * @value: pointer to where the read value will be placed + * + * Return: Negative errno on failure, during which *value will not be touched, + * or 0 on success. + */ +static int rockchip_get_efuse_value(struct device_node *np, const char *cell_name, + int *value) +{ + struct nvmem_cell *cell; + int ret = 0; + size_t len; + u8 *buf; + int i; + + cell = of_nvmem_cell_get(np, cell_name); + if (IS_ERR(cell)) + return PTR_ERR(cell); + + buf = nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + if (len > sizeof(*value)) { + ret = -ERANGE; + goto exit; + } + + /* Copy with implicit endian conversion */ + *value = 0; + for (i = 0; i < len; i++) + *value |= (int) buf[i] << (8 * i); + +exit: + kfree(buf); + return ret; +} + +static int rockchip_get_trim_configuration(struct device *dev, struct device_node *np, + struct rockchip_thermal_data *thermal) +{ + const struct rockchip_tsadc_chip *tsadc = thermal->chip; + int trim_base = 0, trim_base_frac = 0, trim = 0; + int trim_code; + int ret; + + thermal->trim_base = 0; + thermal->trim_base_frac = 0; + thermal->trim = 0; + + if (!tsadc->get_trim_code) + return 0; + + ret = rockchip_get_efuse_value(np, "trim_base", &trim_base); + if (ret < 0) { + if (ret == -ENOENT) { + trim_base = 30; + dev_dbg(dev, "trim_base is absent, defaulting to 30\n"); + } else { + dev_err(dev, "failed reading nvmem value of trim_base: %pe\n", + ERR_PTR(ret)); + return ret; + } + } + ret = rockchip_get_efuse_value(np, "trim_base_frac", &trim_base_frac); + if (ret < 0) { + if (ret == -ENOENT) { + dev_dbg(dev, "trim_base_frac is absent, defaulting to 0\n"); + } else { + dev_err(dev, "failed reading nvmem value of trim_base_frac: %pe\n", + ERR_PTR(ret)); + return ret; + } + } + thermal->trim_base = trim_base; + thermal->trim_base_frac = trim_base_frac; + + /* + * If the tsadc node contains the trim property, then it is used in the + * absence of per-channel trim values + */ + if (!rockchip_get_efuse_value(np, "trim", &trim)) + thermal->trim = trim; + if (trim) { + trim_code = tsadc->get_trim_code(&tsadc->table, trim, + trim_base, trim_base_frac); + thermal->trim_temp = thermal->chip->trim_slope * trim_code; + } + + return 0; +} + static int rockchip_configure_from_dt(struct device *dev, struct device_node *np, struct rockchip_thermal_data *thermal) @@ -1509,6 +1644,8 @@ static int rockchip_configure_from_dt(struct device *dev, if (IS_ERR(thermal->grf)) dev_warn(dev, "Missing rockchip,grf property\n"); + rockchip_get_trim_configuration(dev, np, thermal); + return 0; } @@ -1519,23 +1656,50 @@ rockchip_thermal_register_sensor(struct platform_device *pdev, int id) { const struct rockchip_tsadc_chip *tsadc = thermal->chip; + struct device *dev = &pdev->dev; + int trim = thermal->trim; + int trim_code, tshut_temp; + int trim_temp = 0; int error; + if (thermal->trim_temp) + trim_temp = thermal->trim_temp; + + if (tsadc->get_trim_code && sensor->of_node) { + error = rockchip_get_efuse_value(sensor->of_node, "trim", &trim); + if (error < 0 && error != -ENOENT) { + dev_err(dev, "failed reading trim of sensor %d: %pe\n", + id, ERR_PTR(error)); + return error; + } + if (trim) { + trim_code = tsadc->get_trim_code(&tsadc->table, trim, + thermal->trim_base, + thermal->trim_base_frac); + trim_temp = thermal->chip->trim_slope * trim_code; + } + } + + sensor->trim_temp = trim_temp; + + dev_dbg(dev, "trim of sensor %d is %d\n", id, sensor->trim_temp); + + tshut_temp = min(thermal->tshut_temp + sensor->trim_temp, RK_MAX_TEMP); + tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); - error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, - thermal->tshut_temp); + error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, tshut_temp); if (error) - dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n", - __func__, thermal->tshut_temp, error); + dev_err(dev, "%s: invalid tshut=%d, error=%d\n", + __func__, tshut_temp, error); sensor->thermal = thermal; sensor->id = id; - sensor->tzd = devm_thermal_of_zone_register(&pdev->dev, id, sensor, + sensor->tzd = devm_thermal_of_zone_register(dev, id, sensor, &rockchip_of_thermal_ops); if (IS_ERR(sensor->tzd)) { error = PTR_ERR(sensor->tzd); - dev_err(&pdev->dev, "failed to register sensor %d: %d\n", + dev_err(dev, "failed to register sensor %d: %d\n", id, error); return error; } @@ -1558,9 +1722,11 @@ static int rockchip_thermal_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct rockchip_thermal_data *thermal; + struct device_node *child; int irq; int i; int error; + u32 chn; irq = platform_get_irq(pdev, 0); if (irq < 0) @@ -1611,6 +1777,18 @@ static int rockchip_thermal_probe(struct platform_device *pdev) thermal->chip->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity); + for_each_available_child_of_node(np, child) { + if (!of_property_read_u32(child, "reg", &chn)) { + if (chn < thermal->chip->chn_num) + thermal->sensors[chn].of_node = child; + else + dev_warn(&pdev->dev, + "sensor address (%d) too large, ignoring its trim\n", + chn); + } + + } + for (i = 0; i < thermal->chip->chn_num; i++) { error = rockchip_thermal_register_sensor(pdev, thermal, &thermal->sensors[i], @@ -1680,8 +1858,11 @@ static int __maybe_unused rockchip_thermal_suspend(struct device *dev) static int __maybe_unused rockchip_thermal_resume(struct device *dev) { struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); - int i; + const struct rockchip_tsadc_chip *tsadc = thermal->chip; + struct rockchip_thermal_sensor *sensor; + int tshut_temp; int error; + int i; error = clk_enable(thermal->clk); if (error) @@ -1695,21 +1876,23 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev) rockchip_thermal_reset_controller(thermal->reset); - thermal->chip->initialize(thermal->grf, thermal->regs, - thermal->tshut_polarity); + tsadc->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity); for (i = 0; i < thermal->chip->chn_num; i++) { - int id = thermal->sensors[i].id; + sensor = &thermal->sensors[i]; + + tshut_temp = min(thermal->tshut_temp + sensor->trim_temp, + RK_MAX_TEMP); - thermal->chip->set_tshut_mode(id, thermal->regs, + tsadc->set_tshut_mode(sensor->id, thermal->regs, thermal->tshut_mode); - error = thermal->chip->set_tshut_temp(&thermal->chip->table, - id, thermal->regs, - thermal->tshut_temp); + error = tsadc->set_tshut_temp(&thermal->chip->table, + sensor->id, thermal->regs, + tshut_temp); if (error) dev_err(dev, "%s: invalid tshut=%d, error=%d\n", - __func__, thermal->tshut_temp, error); + __func__, tshut_temp, error); } thermal->chip->control(thermal->regs, true);