From patchwork Tue Mar 4 08:19:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000160 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 860F6C021B8 for ; Tue, 4 Mar 2025 08:32:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 16BB610E302; Tue, 4 Mar 2025 08:32:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="W1hdi1i4"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 968E910E519; Tue, 4 Mar 2025 08:31:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077120; x=1772613120; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=buu1amdupeffLg71up5fXbkAKjtcttX81xfBF6pNmKQ=; b=W1hdi1i4RELt56W44IxdrT3V4ujZoiEpMkX+82zSAevNsTMl/kASnwzr HmaBNdzMgUuuYMsIufJxVbLxipnkqAjcTGTuU3bODem51FgIPphyidI9K dU39FUCPrHHkPNFfDQI1FOrbaVOci5haEtGr2NE952CdY2bYck/vxi1yx PFrqGuJVQadhXNQ4eS29VCoZaUC9lwV0iH5YA2TA/XhQpxkG2Z3VsPLCE xaB6RkoMeLseNan10dNDutkciNym3tFv8Ys1Er7L05I3DphyC7VzXGfqU 7K4Zy1CFudEYAbVWkby9MfVnT4T7pFFx2+6PdSkCgqzof0tuHXmAvAbPR A==; X-CSE-ConnectionGUID: 047u96krTmqJR7KclfePcw== X-CSE-MsgGUID: 9lBfQKUXQMScH6OtdNFkxw== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910125" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910125" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:31:56 -0800 X-CSE-ConnectionGUID: rDfuW0K1QhCKB2GIjEJO2Q== X-CSE-MsgGUID: shGMre97SB6YJ9Gcf7PQsQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492129" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:31:54 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 01/22] drm/i915/vrr: Remove unwanted comment Date: Tue, 4 Mar 2025 13:49:27 +0530 Message-ID: <20250304081948.3177034-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The comment about fixed average vtotal is incorrect. Remove it. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index cac49319026d..106bfaf6649b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -276,11 +276,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, */ crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display); - /* - * When panel is VRR capable and userspace has - * not enabled adaptive sync mode then Fixed Average - * Vtotal mode should be enabled. - */ if (crtc_state->uapi.vrr_enabled) { crtc_state->vrr.enable = true; crtc_state->mode_flags |= I915_MODE_FLAG_VRR; From patchwork Tue Mar 4 08:19:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E254C021B8 for ; Tue, 4 Mar 2025 08:32:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5132B10E51B; Tue, 4 Mar 2025 08:32:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="IIsbE9LR"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9670810E518; Tue, 4 Mar 2025 08:31:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077120; x=1772613120; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=juqJ0qvFmDilx/F20PaSB7Cd1TJX/eYkO/z+meC5J0I=; b=IIsbE9LRD8K+AQZnyh/jyrUUrgScsAexOcScxF41ARy90JiXm0gHLeDr gUIdHheNguhRuGCxEVe36O7+4zseuyUblkqSMqxhFZ6qoRRfnPi/uIHFd Ei+wyXPabGweSqGGVN4gzJN4FgP0MbhnCg0RhtYjiDbkiy3jSZZJiEOyh q3zduo4QpaUi5ntRyyLLq/kCp2e4kIxK+TcnaDu5ewxwitEIBNl4RR9Fu jAaMEhPwtotq+RpkgjMRD66QX3Kp3sGMEfDEJZ5bfoDgZ8XXqCQk26PXy 9OctAvr3nyWCpzTUip/h2uZgjB38u3BF8iHl5tV2HW48d7KE71SzfOHqT A==; X-CSE-ConnectionGUID: fnZw18YEQ9muNWI+1Y/mIQ== X-CSE-MsgGUID: Nv7pS4uxS2a49Q8Xa81sGw== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910138" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910138" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:31:58 -0800 X-CSE-ConnectionGUID: m68OkdrdRI6XMmsUnz7vrQ== X-CSE-MsgGUID: ucqG2xPPTbaq5bY5XS2mTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492140" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:31:56 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 02/22] drm/i915:vrr: Separate out functions to compute vmin and vmax Date: Tue, 4 Mar 2025 13:49:28 +0530 Message-ID: <20250304081948.3177034-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make helpers to compute vmin and vmax. v2: Make the adjusted mode const (Ville) Use reverse xmas tree order of declarations. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 38 +++++++++++++++++++----- 1 file changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 106bfaf6649b..a88b77114867 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -222,6 +222,34 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required) return vtotal; } +static +int intel_vrr_compute_vmin(struct intel_connector *connector, + const struct drm_display_mode *adjusted_mode) +{ + const struct drm_display_info *info = &connector->base.display_info; + int vmin; + + vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, + adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq); + vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal); + + return vmin; +} + +static +int intel_vrr_compute_vmax(struct intel_connector *connector, + const struct drm_display_mode *adjusted_mode) +{ + const struct drm_display_info *info = &connector->base.display_info; + int vmax; + + vmax = adjusted_mode->crtc_clock * 1000 / + (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq); + vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal); + + return vmax; +} + void intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -232,7 +260,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct intel_dp *intel_dp = intel_attached_dp(connector); bool is_edp = intel_dp_is_edp(intel_dp); struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - const struct drm_display_info *info = &connector->base.display_info; int vmin, vmax; /* @@ -253,13 +280,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, if (HAS_LRR(display)) crtc_state->update_lrr = true; - vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, - adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq); - vmax = adjusted_mode->crtc_clock * 1000 / - (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq); - - vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal); - vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal); + vmin = intel_vrr_compute_vmin(connector, adjusted_mode); + vmax = intel_vrr_compute_vmax(connector, adjusted_mode); if (vmin >= vmax) return; From patchwork Tue Mar 4 08:19:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 391CAC282D6 for ; Tue, 4 Mar 2025 08:32:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 55ED010E51A; Tue, 4 Mar 2025 08:32:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="45910139" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910139" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:00 -0800 X-CSE-ConnectionGUID: WxV8fJyMRKet29c2Hk8piQ== X-CSE-MsgGUID: 091ciRB9QH2Gc8vXLbckYQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492144" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:31:59 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 03/22] drm/i915/vrr: Make helpers for cmrr and vrr timings Date: Tue, 4 Mar 2025 13:49:29 +0530 Message-ID: <20250304081948.3177034-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Separate out functions for computing cmrr and vrr timings. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 45 +++++++++++++++--------- 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index a88b77114867..db0ea206e26e 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -222,6 +222,30 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required) return vtotal; } +static +void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state) +{ + crtc_state->vrr.enable = true; + crtc_state->cmrr.enable = true; + /* + * TODO: Compute precise target refresh rate to determine + * if video_mode_required should be true. Currently set to + * false due to uncertainty about the precise target + * refresh Rate. + */ + crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false); + crtc_state->vrr.vmin = crtc_state->vrr.vmax; + crtc_state->vrr.flipline = crtc_state->vrr.vmin; + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; +} + +static +void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state) +{ + crtc_state->vrr.enable = true; + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; +} + static int intel_vrr_compute_vmin(struct intel_connector *connector, const struct drm_display_mode *adjusted_mode) @@ -298,23 +322,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, */ crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display); - if (crtc_state->uapi.vrr_enabled) { - crtc_state->vrr.enable = true; - crtc_state->mode_flags |= I915_MODE_FLAG_VRR; - } else if (is_cmrr_frac_required(crtc_state) && is_edp) { - crtc_state->vrr.enable = true; - crtc_state->cmrr.enable = true; - /* - * TODO: Compute precise target refresh rate to determine - * if video_mode_required should be true. Currently set to - * false due to uncertainty about the precise target - * refresh Rate. - */ - crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false); - crtc_state->vrr.vmin = crtc_state->vrr.vmax; - crtc_state->vrr.flipline = crtc_state->vrr.vmin; - crtc_state->mode_flags |= I915_MODE_FLAG_VRR; - } + if (crtc_state->uapi.vrr_enabled) + intel_vrr_compute_vrr_timings(crtc_state); + else if (is_cmrr_frac_required(crtc_state) && is_edp) + intel_vrr_compute_cmrr_timings(crtc_state); if (HAS_AS_SDP(display)) { crtc_state->vrr.vsync_start = From patchwork Tue Mar 4 08:19:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000164 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7D24C282D3 for ; Tue, 4 Mar 2025 08:32:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C47F10E51D; Tue, 4 Mar 2025 08:32:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="U27JJw9H"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id C7E5B10E302; Tue, 4 Mar 2025 08:32:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077123; x=1772613123; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=73c77X2jtrQLzajo0bb/IL2SbaXrtR99nV38+tucoMI=; b=U27JJw9HtxeNbN7FdTfB13tUMrDcUm+BHI6M1ECjs2eI5lnSeWRdclps Osq5fZ8EW00Ri3pStBINuXQ5nTaC2+t2fFFC92nD5GOONIrKb4JPVKJ91 9DmYTo9460BIyb/3BD99KwLIkghFLxyrBqBUhrRqlh/bMqYRFoOQ29GfI UD2/I/CcMOMevzA8/WoqyIYjvGxM48dSTFDp1zSMY/7Zk0SmSD5/kdP0z woG68fu86M7Dt6dC9lzHqDj8G2/CRlfAum98gKLS68AXfjGydTMlIyeta GfAPrF/TRMN6wyEItTjXYpPxhHEyLB+ietodT/4/CCVzhRCKmWQtR9v+5 w==; X-CSE-ConnectionGUID: wYOtIPNBR12+uC7N3X7nBg== X-CSE-MsgGUID: WlDh0qclTsa6TnV0D2dVzA== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910143" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910143" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:03 -0800 X-CSE-ConnectionGUID: D4UKe881TsCvEYaGFVZLWQ== X-CSE-MsgGUID: 3aw6JMS9QCmOmy5IA27aNA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492156" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:01 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 04/22] drm/i915/vrr: Disable CMRR Date: Tue, 4 Mar 2025 13:49:30 +0530 Message-ID: <20250304081948.3177034-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Switching between variable and fixed timings is possible as for that we just need to flip between VRR timings. However for CMRR along with the timings, few other bits also need to be changed on the fly, which might cause issues. So disable CMRR for now, till we have variable and fixed timings sorted out. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index db0ea206e26e..a57659820f4b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -182,7 +182,8 @@ is_cmrr_frac_required(struct intel_crtc_state *crtc_state) int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line; struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - if (!HAS_CMRR(display)) + /* Avoid CMRR for now till we have VRR with fixed timings working */ + if (!HAS_CMRR(display) || true) return false; actual_refresh_k = From patchwork Tue Mar 4 08:19:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CC07C282E5 for ; Tue, 4 Mar 2025 08:32:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F1B810E524; Tue, 4 Mar 2025 08:32:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="GbO2mkJE"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id EEBD210E51C; Tue, 4 Mar 2025 08:32:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077125; x=1772613125; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=25AyOOFW8lx/wcVTPeUldmGb7poUa6eMHthPvWuq5aY=; b=GbO2mkJERzasUfuWOE5m0Fqe6GowckVibVeMD3TiHDpItGLXG9SIp1bW TlJprtLBrl/MgUlbnsIC3ufDgkzW3VYHcUDwzmMeysrqEO5S+2ne5Q6uz y9wcS+JtCB7WGsDpd3FeF3ED2vOGAUjvCCgyGGnFQu2o36y5ZWh7+6X03 OzQM2QpVgRbnRud+CdZDC1ZFWWkPib5WBdANSM6QEco/6ctdSckRe0dUE TtrY6ESS4hslSfWKZJD5b0CrojGmuQYppUXjQVcJdAt0oY/aJf1ggUmWY tl0A6IbeAM8CLIpK3siNJwKR5SpRTaZEQsTJoSOF6IsNEEJX9pGbuZrFM Q==; X-CSE-ConnectionGUID: VXK0EnP1R5q3GIrtjiUyjg== X-CSE-MsgGUID: rlMf3CtlR9C3U1d3iLavaw== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910151" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910151" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:05 -0800 X-CSE-ConnectionGUID: /P0O3ORbRtSYlJa4BYo7Jg== X-CSE-MsgGUID: S67nmBJdQEGgFOtJCC3rxQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492169" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:03 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 05/22] drm/i915/vrr: Track vrr.enable only for variable timing Date: Tue, 4 Mar 2025 13:49:31 +0530 Message-ID: <20250304081948.3177034-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Since CMRR is now disabled, use the flag vrr.enable to tracks if vrr timing generator is used with variable timings. Avoid setting vrr.enable for CMRR and adjust readout to not set vrr.enable when vmax == vmin == flipline (fixed refresh rate timing). v2: Use intel_vrr_vmin_flipline() to account for adjustments required for icl/tgl. (Ville) v3: Add a #TODO for handling I915_MODE_FLAG_VRR better for CMRR. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index a57659820f4b..7320eb97991f 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -226,7 +226,6 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required) static void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state) { - crtc_state->vrr.enable = true; crtc_state->cmrr.enable = true; /* * TODO: Compute precise target refresh rate to determine @@ -527,6 +526,14 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); } +static +bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->vrr.flipline && + crtc_state->vrr.flipline == crtc_state->vrr.vmax && + crtc_state->vrr.flipline == intel_vrr_vmin_flipline(crtc_state); +} + void intel_vrr_get_config(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -536,7 +543,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) trans_vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); - crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; if (HAS_CMRR(display)) crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); @@ -576,6 +582,14 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) } } + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE && + !intel_vrr_is_fixed_rr(crtc_state); + + /* + * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags. + * Since CMRR is currently disabled, set this flag for VRR for now. + * Need to keep this in mind while re-enabling CMRR. + */ if (crtc_state->vrr.enable) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } From patchwork Tue Mar 4 08:19:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B798C282EC for ; Tue, 4 Mar 2025 08:32:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 73E5E10E526; Tue, 4 Mar 2025 08:32:08 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="IUz0HYnU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5201B10E525; Tue, 4 Mar 2025 08:32:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077127; x=1772613127; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=twWhrfRdE/T3G4gmXvszKBn+QmKwSaG2Wqh/nLwfsbE=; b=IUz0HYnU8PLDI3JohCVrEFdNNmAGb20pbvZcHh8OKz9mT181DW8blVZ4 rxlAf2U05V9EEWSdAYFcsDBsp8BXzr8YuioOhZ3HzgaiULs08J1ZTS7sU XIB3uhjAQPJvuAfpu4jiTcwYpArxVYXgr1ie9Y2AzPWBAM+vWLkFeO269 urNrTorEfwmCeGyhM+aFXjYYhbIz6u+3ZLXMtEYTe/jRmRiYU6K8izf79 i2GDjH6Ug/8k+xo210j8WR8ONVtVhrvX9Lw80JmlQRPYFXPY21XLSqaxL Vx1keps+6Y1y5PBtaeuyv3xsFAnnWaUQkt+z9XkIrlFmOfK7Atx6Mu9Cc w==; X-CSE-ConnectionGUID: TefhRS0MQNGJVLzybwazIA== X-CSE-MsgGUID: H67XrGYZSH+eGh8GRyQOmw== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910157" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910157" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:07 -0800 X-CSE-ConnectionGUID: tpICJJKlQDS/UAg7QeE8hg== X-CSE-MsgGUID: zb341rkTReil4KGceIg+9A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492188" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:05 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 06/22] drm/i915/vrr: Use crtc_vtotal for vmin Date: Tue, 4 Mar 2025 13:49:32 +0530 Message-ID: <20250304081948.3177034-7-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To have fixed refresh rate with VRR timing generator the guardband/pipeline full can't be programmed on the fly. So we need to ensure that the values satisfy both the fixed and variable refresh rates. Since we compute these value based on vmin, lets set the vmin to crtc_vtotal for both fixed and variable timings instead of using the current refresh rate based approach. This way the guardband remains sufficient for both cases. v2: Avoid using vblank delay while computing vtotal, as this comes into the picture later. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 7320eb97991f..e0573e28014b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -247,17 +247,16 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state) } static -int intel_vrr_compute_vmin(struct intel_connector *connector, - const struct drm_display_mode *adjusted_mode) +int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state) { - const struct drm_display_info *info = &connector->base.display_info; - int vmin; - - vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, - adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq); - vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal); - - return vmin; + /* + * To make fixed rr and vrr work seamless the guardband/pipeline full + * should be set such that it satisfies both the fixed and variable + * timings. + * For this set the vmin as crtc_vtotal. With this we never need to + * change anything to do with the guardband. + */ + return crtc_state->hw.adjusted_mode.crtc_vtotal; } static @@ -304,7 +303,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, if (HAS_LRR(display)) crtc_state->update_lrr = true; - vmin = intel_vrr_compute_vmin(connector, adjusted_mode); + vmin = intel_vrr_compute_vmin(crtc_state); vmax = intel_vrr_compute_vmax(connector, adjusted_mode); if (vmin >= vmax) From patchwork Tue Mar 4 08:19:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACE57C282D3 for ; Tue, 4 Mar 2025 08:32:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3AF2010E52A; Tue, 4 Mar 2025 08:32:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EJrTVS6i"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3734310E529; Tue, 4 Mar 2025 08:32:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077129; x=1772613129; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Kp9Qsz2dGOe9obFssM/CfPuREbA6rPuooAAHFumdEK4=; b=EJrTVS6iGkdhWWCVt7faLRiPVz4az8Balcs2K4aND9BtRwAZB2YIPZUY tslygD3PVgFg2nbF5VrT4UolTIg5Sf8SRws0xu9iPviAhG5HYjaLIegWz G1Wfs7MV3aYx/nMuF+CwEdrmfpTTV3HOAs/Mo9hRwbopQsWIpUlu1VNTw U2/zJi8nNGJCXSEMa58FPfk0qVOhjrVSk8g94H3UnHD2o4l+iFt8CE3tG j6nRGOiu4dup1dOFfVQEVEdiIqvY9m8yyKi9kUQG1rnpZGBlfm9BUUeRd jkgHOJK1xZQtQBeQjVH8dJhw0zhhd/ZZhF+7TX4e9EbUyWDqtw8iak4cE Q==; X-CSE-ConnectionGUID: /HeGjagdTFWMYtIL1TvSTw== X-CSE-MsgGUID: 6bWpS6Q8RtOLDnI0Oxus5Q== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910161" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910161" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:09 -0800 X-CSE-ConnectionGUID: RzYetYBPTPOUP7qaO2QTSQ== X-CSE-MsgGUID: tGyVM2k8T66BZPX0nnmj0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492193" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:07 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 07/22] drm/i915/vrr: Prepare for fixed refresh rate timings Date: Tue, 4 Mar 2025 13:49:33 +0530 Message-ID: <20250304081948.3177034-8-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we always compute the timings as if vrr is enabled. With this approach the state checker becomes complicated when we introduce fixed refresh rate mode with vrr timing generator. To avoid the complications, instead of always computing vrr timings, we compute vrr timings based on uapi.vrr_enable knob. So when the knob is disabled we always compute vmin=flipline=vmax. v2: Use actual timings without any adjustments while preparing for fixed timings in compute_config. (Ville) v3: Avoid setting fixed timings if !vrr_possible(). Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä (#v2) --- drivers/gpu/drm/i915/display/intel_vrr.c | 73 ++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index e0573e28014b..0e606dfe4a56 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -246,6 +246,68 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } +/* + * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to + * Vtotal value. + */ +static +int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal; + + if (DISPLAY_VER(display) >= 13) + return crtc_vtotal; + else + return crtc_vtotal - + intel_vrr_real_vblank_delay(crtc_state); +} + +static +int intel_vrr_fixed_rr_vmax(const struct intel_crtc_state *crtc_state) +{ + return intel_vrr_fixed_rr_vtotal(crtc_state); +} + +static +int intel_vrr_fixed_rr_vmin(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + + return intel_vrr_fixed_rr_vtotal(crtc_state) - + intel_vrr_flipline_offset(display); +} + +static +int intel_vrr_fixed_rr_flipline(const struct intel_crtc_state *crtc_state) +{ + return intel_vrr_fixed_rr_vtotal(crtc_state); +} + +static +void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (!intel_vrr_possible(crtc_state)) + return; + + intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), + intel_vrr_fixed_rr_vmin(crtc_state) - 1); + intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), + intel_vrr_fixed_rr_vmax(crtc_state) - 1); + intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), + intel_vrr_fixed_rr_flipline(crtc_state) - 1); +} + +static +void intel_vrr_prepare_fixed_timings(struct intel_crtc_state *crtc_state) +{ + crtc_state->vrr.vmax = intel_vrr_vmin_flipline(crtc_state); + crtc_state->vrr.flipline = intel_vrr_vmin_flipline(crtc_state); +} + static int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state) { @@ -325,6 +387,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, intel_vrr_compute_vrr_timings(crtc_state); else if (is_cmrr_frac_required(crtc_state) && is_edp) intel_vrr_compute_cmrr_timings(crtc_state); + else + intel_vrr_prepare_fixed_timings(crtc_state); if (HAS_AS_SDP(display)) { crtc_state->vrr.vsync_start = @@ -496,6 +560,13 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) if (!crtc_state->vrr.enable) return; + intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), + crtc_state->vrr.vmin - 1); + intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), + crtc_state->vrr.vmax - 1); + intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), + crtc_state->vrr.flipline - 1); + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN); @@ -523,6 +594,8 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) TRANS_VRR_STATUS(display, cpu_transcoder), VRR_STATUS_VRR_EN_LIVE, 1000); intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); + + intel_vrr_set_fixed_rr_timings(old_crtc_state); } static From patchwork Tue Mar 4 08:19:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1C31C282D9 for ; Tue, 4 Mar 2025 08:32:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 828BB10E52E; Tue, 4 Mar 2025 08:32:13 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="N9fPh8DW"; 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d="scan'208";a="45910167" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:11 -0800 X-CSE-ConnectionGUID: +Ktu8hViQUSFpWlAcSVjLg== X-CSE-MsgGUID: YciReWpZQfmTjxnQsm0BwA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492199" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:09 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 08/22] drm/i915/display: Enable MSA Ignore Timing PAR only when in not fixed_rr mode Date: Tue, 4 Mar 2025 13:49:34 +0530 Message-ID: <20250304081948.3177034-9-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" MSA Ignore Timing PAR enable is set in the DP sink when we enable variable refresh rate. Currently for link training we depend on flipline to decide whether we want to ignore the msa timings. With fixed refresh rate we will still fill the flipline in all cases whether panel supports VRR or not. Change the condition for link training to ignore the msa timings if vrr.in_range. v2: Add more documentation and a #TODO for readout of vrr.in_range. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 2966f5b39392..ea225496a96e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -711,8 +711,21 @@ void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, b static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { + /* + * Currently, we set the MSA ignore bit based on vrr.in_range. + * We can't really read that out during driver load since we don't have + * the connector information read in yet. So if we do end up doing a + * modeset during initial_commit() we'll clear the MSA ignore bit. + * GOP likely wouldn't have set this bit so after the initial commit, + * if there are no modesets and we enable VRR mode seamlessly + * (without a full modeset), the MSA ignore bit might never get set. + * + * #TODO: Implement readout of vrr.in_range. + * We need fastset support for setting the MSA ignore bit in DPCD, + * especially on the first real commit when clearing the inherited flag. + */ intel_dp_link_training_set_mode(intel_dp, - crtc_state->port_clock, crtc_state->vrr.flipline); + crtc_state->port_clock, crtc_state->vrr.in_range); } void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, From patchwork Tue Mar 4 08:19:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2505C021B8 for ; Tue, 4 Mar 2025 08:32:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C86210E52F; Tue, 4 Mar 2025 08:32:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="VbfAd/1O"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8E45C10E52F; Tue, 4 Mar 2025 08:32:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077134; x=1772613134; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wTrBq0rmVsGk9LwWbSeVbEPwVwTPlUS/aQDJWPq0ILA=; b=VbfAd/1O16ph2zST++73AGr4nzpAe+r+96ig9DqX5MGnDLvtdGBuklpQ Ic9WLWIDy32vIkSWXb5nRUFFifi3etYGLF+chaXhNSh1pB52oOA3duaHk AJKiCmtCwBwUmsXq5JfPwM2q8VgCjGVHvWcdBiH3YbvhIrebjAAJyNUxW NOwleA1yWJawpdjNi5NtFBp2GOiO/t4UYqWFcS56B2mTlQ+tPlxaUEKMp r0Y50UlXigkH3Vp89vUBxHWwvbQCxAnnfVbcfFMdxnuBOFIyPJqoWMdSI azxdmpJQxFdw+hb1ySWim/8imrq+WDbVvFXViqOwsZ1wJ67d30xRRfTsQ A==; X-CSE-ConnectionGUID: kSdpYbNsRti8Q7ZjcxikxQ== X-CSE-MsgGUID: 7c1Sk1yJQhOmhrdQfCHTVw== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910174" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910174" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:13 -0800 X-CSE-ConnectionGUID: JC80cfZjTKWkF6sTt/97oA== X-CSE-MsgGUID: 7Q2+o6AJQGyaCoxsbNvlTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492206" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:11 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 09/22] drm/i915/hdmi: Use VRR Timing generator for HDMI for fixed_rr Date: Tue, 4 Mar 2025 13:49:35 +0530 Message-ID: <20250304081948.3177034-10-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently VRR is not supported with HDMI, but we can still leverage the VRR Timing Generator to achieve a fixed refresh rate. Call intel_vrr_compute_config() for HDMI which will handle the vrr timings to have fixed refresh rate with VRR Timing Generator. v2: Improve commit message. (Ville). Signed-off-by: Ankit Nautiyal Reviewed-by: Mitul Golani (#v1) --- drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 33b8d5229db0..f9fa17e1f584 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -64,6 +64,7 @@ #include "intel_panel.h" #include "intel_pfit.h" #include "intel_snps_phy.h" +#include "intel_vrr.h" static void assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) @@ -2384,6 +2385,8 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, } } + intel_vrr_compute_config(pipe_config, conn_state); + intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); From patchwork Tue Mar 4 08:19:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000170 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD4DBC282D3 for ; Tue, 4 Mar 2025 08:32:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 719E810E540; Tue, 4 Mar 2025 08:32:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="R8XQ50BN"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id A71B410E532; Tue, 4 Mar 2025 08:32:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077136; x=1772613136; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tmvCnc9s58wM8BwoeBBwcUB3y48arWkHN/04vZDKAEQ=; b=R8XQ50BN5EiKlb4NrLxSaM138p8SHjKNvza0H/yEXie1olE0qNWasLq4 XXnjQaAQTKyR+ZRmRm3ztCG/D80DC4s1Ji6tRLfG7gYpUODoSoNqipKP4 27ha3axG4Iq0OxUeTeG39WYYzQcfwH7DUqkjnkHdztpoflCDtVvKzwzI2 Lgkmit7QIYvBy+b01ByMehKgMTXzxQ2Xbu6i5479FNaR4lbdScWPRFzh6 n4OwRMrVvfrE40zyByuRuxWmkBrJUYM3BdueNdWyWsWRodDRzUH9b62RH +hxmovR1bOX+TRST0jBset55UXjQuMdVTmxeflK9Gkm56y886GRNu+W+j A==; X-CSE-ConnectionGUID: oN7mczthRrKoXnw411gL3Q== X-CSE-MsgGUID: XYVE++YgTtaywIQpaIHbTw== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910176" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910176" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:15 -0800 X-CSE-ConnectionGUID: sha9AFqBSKin7LXbDeXCGw== X-CSE-MsgGUID: Bx+tyoTXT66/1M5PJi85cA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492210" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:14 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 10/22] drm/i915/dp_mst: Use VRR Timing generator for DP MST for fixed_rr Date: Tue, 4 Mar 2025 13:49:36 +0530 Message-ID: <20250304081948.3177034-11-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently the variable timings are supported only for DP and eDP and not for DP MST. Call intel_vrr_compute_config() for MST which will configure fixed refresh rate timings irrespective of whether VRR is supported or not. Since vrr_capable still doesn't have support for DP MST this will be just treated as non VRR case and vrr.vmin/vmax/flipline will be all set to adjusted_mode->crtc_vtotal. This will help to move away from the legacy timing generator and always use VRR timing generator by default. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 02f95108c637..bd47cf127b4c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -52,6 +52,7 @@ #include "intel_pfit.h" #include "intel_psr.h" #include "intel_vdsc.h" +#include "intel_vrr.h" #include "skl_scaler.h" /* @@ -710,6 +711,8 @@ static int mst_stream_compute_config(struct intel_encoder *encoder, pipe_config->lane_lat_optim_mask = bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); + intel_vrr_compute_config(pipe_config, conn_state); + intel_dp_audio_compute_config(encoder, pipe_config, conn_state); intel_ddi_compute_min_voltage_level(pipe_config); From patchwork Tue Mar 4 08:19:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03577C021B8 for ; Tue, 4 Mar 2025 08:32:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A70310E53D; Tue, 4 Mar 2025 08:32:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="TwJQD7y9"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id C337E10E541; Tue, 4 Mar 2025 08:32:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077138; x=1772613138; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EplFRRENTlGMF8A0LS5XqA/T4jHSSFnCeHe9aUzueKY=; b=TwJQD7y96CHr+vf1TTlotbIPxScMFLFNAAn5wnNYuipNek33yaGJU0G7 mL8W3uIpQwBAQpIiCm/SMHAiCuuzShfebjKS9T47rLolSx2l/8EjWC+w0 HlSanbNm3dF2TyFilSlbCcjSivB5BzThGkWli21bW/PXH+pR0mM/XzXae mj0Tb6w65QJBpc8W6Knp9McoKh4cDf2aMURT3NXpwYaSk7NEaHji+V4KL QCmbdyB6fB5W9ydm74TNgPqpIbn2LXGxtQS4ld8U8fAvyxOa5Vy2OQekG tsRGhrUtIMThT2aDqqewx9V/jepKb4yrd5ta2pAHYk+ZLG7RyqD4dEdNg w==; X-CSE-ConnectionGUID: KHTAU1QoTmWpwwQEO75EBw== X-CSE-MsgGUID: aXGxLNXxSEaFIFDHPHdynQ== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910180" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910180" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:18 -0800 X-CSE-ConnectionGUID: 3OKTB9PkTiqe0KqUbx87Ew== X-CSE-MsgGUID: mfZ43aldROiBeRG6lSJdEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492216" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:16 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 11/22] drm/i915/display: Disable PSR before disabling VRR Date: Tue, 4 Mar 2025 13:49:37 +0530 Message-ID: <20250304081948.3177034-12-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" As per bspec 49268: Disable PSR before disabling VRR. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c4b0ec60fded..d1f814050274 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1173,6 +1173,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; + intel_psr_pre_plane_update(state, crtc); + if (intel_crtc_vrr_disabling(state, crtc)) { intel_vrr_disable(old_crtc_state); intel_crtc_update_active_timings(old_crtc_state, false); @@ -1183,8 +1185,6 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_drrs_deactivate(old_crtc_state); - intel_psr_pre_plane_update(state, crtc); - if (hsw_ips_pre_update(state, crtc)) intel_crtc_wait_for_next_vblank(crtc); From patchwork Tue Mar 4 08:19:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6613C282D3 for ; Tue, 4 Mar 2025 08:32:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4519710E522; Tue, 4 Mar 2025 08:32:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CBr2A3hw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id E311410E535; Tue, 4 Mar 2025 08:32:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077140; x=1772613140; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sLcVJYyPe+eQ1EGi3djoLJw21g7jlTfzxUazH19/w04=; b=CBr2A3hwJpOGziNg2wzvEZJNLDKVbPsk/nDGZEI4MD3+ap8Kdu7KZzeh js3sbHy4iERiqEk1O47K8c4M+WVLl1I8lpxSZsiYQ06y4juI8J8EdyWgq G8gwRxNc6XLpjEe/PBidtGDWH7M5XYXf/sO49+ZaeiLRgWiGc8bTtB+2a +tjp8cVHsfmvoj4EmT0+hbmiBi0FXvUJELLWhnd2zotr9AhfGftgUgbd4 nC5eSBIZp8k9cHXu2WXPSFN5kx6yws1OrEVl6ta6ByqCbR3FRuz9xFwHJ 3+dNIA+GDTc4KLk36fipnweTlCrE5DwAI39IkJ/am0evd53Yg3ceBRfRZ g==; X-CSE-ConnectionGUID: bn2iGeS2QqmEQn8g/GzrQQ== X-CSE-MsgGUID: w5pG5xCbSH22UaEXWlXDpQ== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910182" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910182" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:20 -0800 X-CSE-ConnectionGUID: LhlQvrPsSZK3qbc1Njp0lg== X-CSE-MsgGUID: BGLpLl0eRQ+Pm01JE2Frag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492229" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:18 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 12/22] drm/i915/display: Move intel_psr_post_plane_update() at the later Date: Tue, 4 Mar 2025 13:49:38 +0530 Message-ID: <20250304081948.3177034-13-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In intel_post_plane_update() there are things which might need to do vblank waits, so enabling PSR as early as we do now is simply counter-productive. Therefore move intel_psr_post_plane_update() at the last of intel_post_plane_update(). Signed-off-by: Ankit Nautiyal Suggested-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d1f814050274..a885694df90a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1048,8 +1048,6 @@ static void intel_post_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - intel_psr_post_plane_update(state, crtc); - intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) @@ -1078,6 +1076,8 @@ static void intel_post_plane_update(struct intel_atomic_state *state, if (audio_enabling(old_crtc_state, new_crtc_state)) intel_encoders_audio_enable(state, crtc); + + intel_psr_post_plane_update(state, crtc); } static void intel_post_plane_update_after_readout(struct intel_atomic_state *state, From patchwork Tue Mar 4 08:19:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32A71C021B8 for ; Tue, 4 Mar 2025 08:32:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D168510E51F; Tue, 4 Mar 2025 08:32:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="jVFUOaRV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 10E3E10E519; Tue, 4 Mar 2025 08:32:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077142; x=1772613142; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UCTmCW86ldIr8zVnXMD0WqqnHm76GUdVcbDaQxngBkM=; b=jVFUOaRV4jDF1Pr3CK0pklENu42893hWsEVXuzTfI/ko3HgK5w4kH7Jf DIZE88nR1sXjKMBP2o1WMTGujzXNsESitrTUZ8OfQlW97vyRUXhyt9a/b MZDhFdQiPpX00DKcfTYv+wknseHEGNCFTb+ronDuRgzIKNz4C7ALsywEj rlpBwS9Uzil/zMJOmzdkaqBRmxQFZCpenSzFh3oWfJTkZnkjdYs9ve8tF yDdrJ/c9goO7AekjZnxewWsz5qxZjUdJg9qoiA19HYHbFAAR5zvZs0v/W EyWOjKoXbXw81bzbzMjbFOYkCWi/nyyX4TKp0J7yNkYskCpF2/mQKSNnm A==; X-CSE-ConnectionGUID: eEHTGlw0RJGGlAIAsruBdw== X-CSE-MsgGUID: bMuldxJgSGmdmyBLPFme7g== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910184" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910184" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:22 -0800 X-CSE-ConnectionGUID: s8K3gDymQm+nD4GvYMKIlQ== X-CSE-MsgGUID: 45738EE3SfmdAuC3jmA4zQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492238" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:20 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 13/22] drm/i915/vrr: Refactor condition for computing vmax and LRR Date: Tue, 4 Mar 2025 13:49:39 +0530 Message-ID: <20250304081948.3177034-14-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" LRR and Vmax can be computed only if VRR is supported and vrr.in_range is set. Currently we proceed with vrr timings only for VRR supporting panels and return otherwise. For using VRR TG with fix timings, need to continue even for panels that do not support VRR. To achieve this, refactor the condition for computing vmax and update_lrr so that we can continue for fixed timings for panels that do not support VRR. v2: Set vmax = vmin for non VRR panels. (Ville) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 0e606dfe4a56..fbb8a5a5f444 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -359,14 +359,16 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->vrr.in_range = intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)); - if (!crtc_state->vrr.in_range) - return; - - if (HAS_LRR(display)) - crtc_state->update_lrr = true; vmin = intel_vrr_compute_vmin(crtc_state); - vmax = intel_vrr_compute_vmax(connector, adjusted_mode); + + if (crtc_state->vrr.in_range) { + if (HAS_LRR(display)) + crtc_state->update_lrr = true; + vmax = intel_vrr_compute_vmax(connector, adjusted_mode); + } else { + vmax = vmin; + } if (vmin >= vmax) return; From patchwork Tue Mar 4 08:19:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94229C282D0 for ; Tue, 4 Mar 2025 08:32:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3287910E534; Tue, 4 Mar 2025 08:32:25 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="P5GxEWZy"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C10810E533; Tue, 4 Mar 2025 08:32:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077144; x=1772613144; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UrOstT9nDIP1gH0abZ36+tZpxYJVMX0d0gj77KPUHn0=; b=P5GxEWZyQSq549JlCmRwEbaDE1PjtHJu0IJQhcnFaGx0sGLlZGrYzQyj LDP9RAPsBKWXOyTW5hbiV137OxpX8H6dV+iISX/4RAfu6xcpcURc88ia+ 10ioZltj7m1lYhJPQl2g3h+kYMvuQjkhtnzgHVlH62tDkgV35peXN2gnf YX/QGgMQ19BfWY9GN4Pj1nkisoR+UIedgBq4F6rZHOfQtdh2UQGN4iJi2 O74LEbdrFyPNku3zFu1JRfl1lJ1iP7X6dKU80hLpqm6jEW+XDlAWBkOLZ ADAgo/VqASBwtjSiWv1CZnBvGqo6n0JYbDknQnEdvXoGiUOuAwzEKcJ+K w==; X-CSE-ConnectionGUID: ru1WhOPpRDuMlPgsipC+iQ== X-CSE-MsgGUID: Ajr4+vrzSgy12TAzr6IO8A== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910186" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910186" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:24 -0800 X-CSE-ConnectionGUID: 0KtR4JZ3Si60jyt4FMZKgQ== X-CSE-MsgGUID: c49/xGA/TvKEYtU89APvVw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492242" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:22 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 14/22] drm/i915/vrr: Always set vrr vmax/vmin/flipline in vrr_{enable/disable} Date: Tue, 4 Mar 2025 13:49:40 +0530 Message-ID: <20250304081948.3177034-15-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For platforms for which vrr timing generator is always set, VRR_CTL enable bit does not need to toggle, so modify the vrr_{enable/disable} for this. At the moment the helper intel_vrr_always_use_vrr_tg() return false for all cases. This will be set later when all other bits are in place. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 40 ++++++++++++++++-------- 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index fbb8a5a5f444..c1387d3f60b2 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -554,6 +554,16 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; } +static +bool intel_vrr_always_use_vrr_tg(struct intel_display *display) +{ + if (!HAS_VRR(display)) + return false; + + /* #TODO return true for platforms supporting fixed_rr */ + return false; +} + void intel_vrr_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -572,13 +582,15 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN); - if (crtc_state->cmrr.enable) { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | - trans_vrr_ctl(crtc_state)); - } else { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (!intel_vrr_always_use_vrr_tg(display)) { + if (crtc_state->cmrr.enable) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } else { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } } } @@ -590,12 +602,14 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) if (!old_crtc_state->vrr.enable) return; - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - trans_vrr_ctl(old_crtc_state)); - intel_de_wait_for_clear(display, - TRANS_VRR_STATUS(display, cpu_transcoder), - VRR_STATUS_VRR_EN_LIVE, 1000); - intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); + if (!intel_vrr_always_use_vrr_tg(display)) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(old_crtc_state)); + intel_de_wait_for_clear(display, + TRANS_VRR_STATUS(display, cpu_transcoder), + VRR_STATUS_VRR_EN_LIVE, 1000); + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); + } intel_vrr_set_fixed_rr_timings(old_crtc_state); } From patchwork Tue Mar 4 08:19:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9757C021B8 for ; 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X-CSE-ConnectionGUID: /7GeHdtNSSaBQLbpRlaiDg== X-CSE-MsgGUID: dbnrCxwQRTOwZavQoFX9Zg== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910189" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910189" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:26 -0800 X-CSE-ConnectionGUID: I6ESeCCIR3CLfGldAiIGzA== X-CSE-MsgGUID: QhSiiJ71TO2RqYnnLzx7WQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492245" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:24 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 15/22] drm/i915/display: Use fixed_rr timings in modeset sequence Date: Tue, 4 Mar 2025 13:49:41 +0530 Message-ID: <20250304081948.3177034-16-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During modeset enable sequence, program the fixed timings, and turn on the VRR Timing Generator (VRR TG) for platforms that always use VRR TG. For this intel_vrr_set_transcoder now always programs fixed timings. Later if vrr timings are required, vrr_enable() will switch to the real VRR timings. For platforms that will always use VRR TG, the VRR_CTL Enable bit is set and reset in the transcoder enable/disable path. v2: Update intel_vrr_set_transcoder_timings for fixed_rr. v3: Update intel_set_transcoder_timings_lrr for fixed_rr. (Ville) v4: Have separate functions to enable/disable VRR CTL v5: -For platforms that do not always have VRRTG on, do write bits other than enable bit and also use write the TRANS_VRR_PUSH register. (Ville) -Avoid writing trans_ctl_vrr if !vrr_possible(). Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++ drivers/gpu/drm/i915/display/intel_vrr.c | 59 ++++++++++++++++----- drivers/gpu/drm/i915/display/intel_vrr.h | 3 ++ 4 files changed, 57 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 20fc258a4d6d..6f083c28c455 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -78,6 +78,7 @@ #include "intel_tc.h" #include "intel_vdsc.h" #include "intel_vdsc_regs.h" +#include "intel_vrr.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -3273,6 +3274,8 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { + intel_vrr_transcoder_disable(old_crtc_state); + if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, old_conn_state); @@ -3521,6 +3524,8 @@ static void intel_ddi_enable(struct intel_atomic_state *state, intel_ddi_enable_transcoder_func(encoder, crtc_state); + intel_vrr_transcoder_enable(crtc_state); + /* Enable/Disable DP2.0 SDP split config before transcoder */ intel_audio_sdp_split_update(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index bd47cf127b4c..7dbc9b3bdbe4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1049,6 +1049,8 @@ static void mst_stream_post_disable(struct intel_atomic_state *state, intel_crtc_vblank_off(old_pipe_crtc_state); } + intel_vrr_transcoder_disable(old_crtc_state); + intel_disable_transcoder(old_crtc_state); drm_dp_remove_payload_part1(&intel_dp->mst.mgr, new_mst_state, new_payload); @@ -1326,6 +1328,8 @@ static void mst_stream_enable(struct intel_atomic_state *state, intel_ddi_enable_transcoder_func(encoder, pipe_config); + intel_vrr_transcoder_enable(pipe_config); + intel_ddi_clear_act_sent(encoder, pipe_config); intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, trans), 0, diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index c1387d3f60b2..97040ab9ed86 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -456,12 +456,6 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0, PIPE_VBLANK_WITH_DELAY); - if (!intel_vrr_possible(crtc_state)) { - intel_de_write(display, - TRANS_VRR_CTL(display, cpu_transcoder), 0); - return; - } - if (crtc_state->cmrr.enable) { intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), upper_32_bits(crtc_state->cmrr.cmrr_m)); @@ -473,14 +467,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) lower_32_bits(crtc_state->cmrr.cmrr_n)); } - intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), - crtc_state->vrr.vmin - 1); - intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), - crtc_state->vrr.vmax - 1); - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - trans_vrr_ctl(crtc_state)); - intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), - crtc_state->vrr.flipline - 1); + intel_vrr_set_fixed_rr_timings(crtc_state); if (HAS_AS_SDP(display)) intel_de_write(display, @@ -614,6 +601,50 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) intel_vrr_set_fixed_rr_timings(old_crtc_state); } +void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (!HAS_VRR(display)) + return; + + if (!intel_vrr_possible(crtc_state)) + return; + + if (!intel_vrr_always_use_vrr_tg(display)) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(crtc_state)); + return; + } + + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), + TRANS_PUSH_EN); +} + +void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (!HAS_VRR(display)) + return; + + if (!intel_vrr_possible(crtc_state)) + return; + + if (!intel_vrr_always_use_vrr_tg(display)) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(crtc_state)); + return; + } + + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 0); +} + static bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state) { diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 514822577e8a..c81f98f83b58 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -12,6 +12,7 @@ struct drm_connector_state; struct intel_atomic_state; struct intel_connector; struct intel_crtc_state; +struct intel_display; struct intel_dsb; bool intel_vrr_is_capable(struct intel_connector *connector); @@ -35,5 +36,7 @@ int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state); int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state); int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state); int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state); +void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); +void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ From patchwork Tue Mar 4 08:19:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2540BC282D0 for ; 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X-CSE-ConnectionGUID: UmqvXoObQOWlCTWbM2pM2g== X-CSE-MsgGUID: 1OK/vCjFRfyprntSCxwEzA== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910192" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910192" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:28 -0800 X-CSE-ConnectionGUID: 1fzhsJdWQ3Sr/RVMK00P+w== X-CSE-MsgGUID: tiMuDnPUTsSkCzndZvbhog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492250" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:26 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 16/22] drm/i915/vrr: Use fixed timings for platforms that support VRR Date: Tue, 4 Mar 2025 13:49:42 +0530 Message-ID: <20250304081948.3177034-17-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For fixed refresh rate use fixed timings for all platforms that support VRR. For this add checks to avoid computing and reading VRR for platforms that do not support VRR. v2: Avoid touching check for VRR_CTL_FLIP_LINE_EN. (Ville) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_vrr.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 97040ab9ed86..11f23affd13a 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -347,6 +347,9 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int vmin, vmax; + if (!HAS_VRR(display)) + return; + /* * FIXME all joined pipes share the same transcoder. * Need to account for that during VRR toggle/push/etc. @@ -370,8 +373,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, vmax = vmin; } - if (vmin >= vmax) - return; + vmin = intel_vrr_compute_vmin(crtc_state); crtc_state->vrr.vmin = vmin; crtc_state->vrr.vmax = vmax; @@ -385,7 +387,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, */ crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display); - if (crtc_state->uapi.vrr_enabled) + if (crtc_state->uapi.vrr_enabled && vmin < vmax) intel_vrr_compute_vrr_timings(crtc_state); else if (is_cmrr_frac_required(crtc_state) && is_edp) intel_vrr_compute_cmrr_timings(crtc_state); @@ -659,6 +661,9 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 trans_vrr_ctl, trans_vrr_vsync; + if (!HAS_VRR(display)) + return; + trans_vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); From patchwork Tue Mar 4 08:19:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC626C282D6 for ; Tue, 4 Mar 2025 08:32:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8399F10E539; Tue, 4 Mar 2025 08:32:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="g4X6AgDU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 886B410E539; Tue, 4 Mar 2025 08:32:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077150; x=1772613150; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YWmI73TmA0Odt/a2tugjrvYJIByk8WEFCxMuXe9Mlsk=; b=g4X6AgDUQW0VK0OHIJ6Cv7KrasVPWRvH3tRZ9M2ATjqf3WzMEt2pXLHd 9YilTrhfAQJvjrD0rkXqvfOTlRo3ckVig14JgZHw0ZfvNzJXlPjnO4dkE 14XYUPCJrICaLD3H1v3dLPdfrYIMxsHYGzmzmwCq6/tpnZONI2j+ghGJy woZaihgBYCKL0Gv1268ysI/DZWOY5aJt5AuRrncikmIj2StWqzhBmwB+U gVepk/WARLvcF9Cqqf2KnVqvmQePLUwvmHfy8kPInValb4J38QqsLAUpl Xe+Qh6l72rq2/0Yi9B0X9xkYRlMcwciG+jQZQ7We0Jgj1XfV3ebJJ8bkg Q==; X-CSE-ConnectionGUID: Q7w9gVFwTwKwLZmq2momJg== X-CSE-MsgGUID: BGGHu+w2QM6Jr5zs2KyigQ== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910195" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910195" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:30 -0800 X-CSE-ConnectionGUID: 1W1cfav0QeW/MDscU5LwUw== X-CSE-MsgGUID: Izk9tBlfSeKAwDYOLXrurg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492253" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:28 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 17/22] drm/i915/display: Move vrr.guardband/pipeline_full out of !fastset block Date: Tue, 4 Mar 2025 13:49:43 +0530 Message-ID: <20250304081948.3177034-18-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The vrr.guardband/pipeline_full depend on the vrr.vmin. Since we have set vrr.vmin to adjusted_mode->crtc_vtotal, this shouldn't change on the fly. With this we can move vrr.guardband/pipeline_full out from !fastset block. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a885694df90a..3e8ceafcbbb4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5411,8 +5411,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.vmin); PIPE_CONF_CHECK_I(vrr.vmax); PIPE_CONF_CHECK_I(vrr.flipline); - PIPE_CONF_CHECK_I(vrr.pipeline_full); - PIPE_CONF_CHECK_I(vrr.guardband); PIPE_CONF_CHECK_I(vrr.vsync_start); PIPE_CONF_CHECK_I(vrr.vsync_end); PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); @@ -5420,6 +5418,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(cmrr.enable); } + PIPE_CONF_CHECK_I(vrr.pipeline_full); + PIPE_CONF_CHECK_I(vrr.guardband); + #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_LLI From patchwork Tue Mar 4 08:19:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61AABC282D0 for ; Tue, 4 Mar 2025 08:32:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0511D10E541; Tue, 4 Mar 2025 08:32:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SDmxwK/+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id A6B4B10E531; Tue, 4 Mar 2025 08:32:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077153; x=1772613153; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wcFBev/dLHA0u3Cje/XPuQfJBQreuJaodRuWU+zw0P4=; b=SDmxwK/+6Z3ZbI1JFjEAUuLJGRtaXXVXo355NN56Pv4nkwdRWRLqO76g 6Y+esQx6fNG0hQygiHFk2+qNsuE/s78FBJH5OPbYq92oRzrVfYldkhcog 97ce3du1YfB4LOkyROt5YELqydmjZ7ccPJLDdCpi062Vu6piK6YmjzGC9 d3MBjltEL1VgVZTF2gQOJpIwp6vunYVbrMlvD07RdDGnLLVfs+EEP/Sam jTZmQ6BqsDfvF46F/su2cV3ogiPxq0+lgv6XsWi0+oL9tXeJ2u1AkL0Ru ReYqRJuo1Xm34Brm7iCVjEh7T9FbKfgoewn27tLtlAxW5Xc1141oCXnYJ w==; X-CSE-ConnectionGUID: PGoObkokRvu3TSbYCle1kA== X-CSE-MsgGUID: fFTl9QMsR5GfpAM+uBsS0A== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910198" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910198" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:32 -0800 X-CSE-ConnectionGUID: v0Ee6RtlTkC/8WHyWmpjkg== X-CSE-MsgGUID: d2D5my0nQB60iic/bwNfIA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492256" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:31 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 18/22] drm/i915/display: Use fixed rr timings in intel_set_transcoder_timings_lrr() Date: Tue, 4 Mar 2025 13:49:44 +0530 Message-ID: <20250304081948.3177034-19-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To have Guardband/Pipeline_full reconfigured seamlessly, move the guardband and pipeline_full from intel_pipe_config_compare() to fastboot exception. Update the intel_set_transcoder_timings_lrr() function to use fixed refresh rate timings for platforms which always use VRR timing generator. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- drivers/gpu/drm/i915/display/intel_vrr.c | 1 - drivers/gpu/drm/i915/display/intel_vrr.h | 1 + 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 3e8ceafcbbb4..c31a87d8afd3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2768,6 +2768,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); + + intel_vrr_set_fixed_rr_timings(crtc_state); + intel_vrr_transcoder_enable(crtc_state); } static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) @@ -5418,8 +5421,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(cmrr.enable); } - PIPE_CONF_CHECK_I(vrr.pipeline_full); - PIPE_CONF_CHECK_I(vrr.guardband); + if (!fastset && !allow_vblank_delay_fastset(current_config)) { + PIPE_CONF_CHECK_I(vrr.pipeline_full); + PIPE_CONF_CHECK_I(vrr.guardband); + } #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 11f23affd13a..0dfe6220ff4a 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -284,7 +284,6 @@ int intel_vrr_fixed_rr_flipline(const struct intel_crtc_state *crtc_state) return intel_vrr_fixed_rr_vtotal(crtc_state); } -static void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index c81f98f83b58..0e1becd7a0c0 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -38,5 +38,6 @@ int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state); int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); +void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ From patchwork Tue Mar 4 08:19:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36053C282D6 for ; Tue, 4 Mar 2025 08:32:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C92CA10E53B; Tue, 4 Mar 2025 08:32:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="U3xRcYL3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 076AF10E542; Tue, 4 Mar 2025 08:32:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077155; x=1772613155; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=a4DG9h/pgIFoTAb6S8cqy8VCXsAhPBA59p/sj4OW1Eg=; b=U3xRcYL3Yos1GuuW7qhIaNZegZ9bux9oHj12PIr9sZrt9MlyxGyS2SPI NAGdUOXkCyIhQjNn4G8exg7NSXhF6Q+x90UYsehzjsxAV+lJQ2qEg7Jo7 2BH5sj78jxlF/aapykYiOjynFznVQ+VlAUAXmqb6dY7ZjUPonnmGIlxwW E6bC7sCKvtt41KV7l8Ko4Vf/5vkUY1EqSbOOXKpUYA+GgyLBgxMXBbQby eYPhTgYzFmAyf+hUvGiNgaTUppHoSOjPdu1VPWJ1VMpvzMSmr+kv0wmLp 2fAo5DlvAOa819K562gomV5gHELo3Qh7aq+SZIG1m9FnyivEdW8N7S3mg A==; X-CSE-ConnectionGUID: L0+LUa44Q167/nysalzYKw== X-CSE-MsgGUID: BA9EYqErQ1eIu+kAakMjzg== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910203" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910203" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:35 -0800 X-CSE-ConnectionGUID: q6OiRE0kQIW8FcVVZ0chxg== X-CSE-MsgGUID: /OPEOtvfSZK+uwMJOXG6nQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492260" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:33 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 19/22] drm/i915/vrr: Allow fixed_rr with pipe joiner Date: Tue, 4 Mar 2025 13:49:45 +0530 Message-ID: <20250304081948.3177034-20-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" VRR with joiner is currently disabled as it still needs some work to correctly sequence the primary and secondary transcoders. However, we can still use VRR Timing generator in fixed refresh rate for joiner and since it just need to program vrr timings once and does not involve changing timings on the fly. We still need to skip the VRR and LRR for joiner. To achieve this set vrr.in_range to 0 for joiner case, so that we do not try VRR and LRR for the joiner case. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_vrr.c | 38 +++++++++++++++++++----- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 0dfe6220ff4a..2b6d022434d2 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -292,6 +292,9 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state) if (!intel_vrr_possible(crtc_state)) return; + if (intel_crtc_is_joiner_secondary(crtc_state)) + return; + intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), intel_vrr_fixed_rr_vmin(crtc_state) - 1); intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), @@ -349,19 +352,23 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, if (!HAS_VRR(display)) return; - /* - * FIXME all joined pipes share the same transcoder. - * Need to account for that during VRR toggle/push/etc. - */ - if (crtc_state->joiner_pipes) - return; - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) return; crtc_state->vrr.in_range = intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)); + /* + * Allow fixed refresh rate with VRR Timing Generator. + * For now set the vrr.in_range to 0, to allow fixed_rr but skip actual + * VRR and LRR. + * #TODO For actual VRR with joiner, we need to figure out how to + * correctly sequence transcoder level stuff vs. pipe level stuff + * in the commit. + */ + if (crtc_state->joiner_pipes) + crtc_state->vrr.in_range = 0; + vmin = intel_vrr_compute_vmin(crtc_state); if (crtc_state->vrr.in_range) { @@ -448,6 +455,8 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + if (intel_crtc_is_joiner_secondary(crtc_state)) + return; /* * This bit seems to have two meanings depending on the platform: * TGL: generate VRR "safe window" for DSB vblank waits @@ -486,6 +495,9 @@ void intel_vrr_send_push(struct intel_dsb *dsb, if (!crtc_state->vrr.enable) return; + if (intel_crtc_is_joiner_secondary(crtc_state)) + return; + if (dsb) intel_dsb_nonpost_start(dsb); @@ -560,6 +572,9 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) if (!crtc_state->vrr.enable) return; + if (intel_crtc_is_joiner_secondary(crtc_state)) + return; + intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), crtc_state->vrr.vmin - 1); intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), @@ -590,6 +605,9 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) if (!old_crtc_state->vrr.enable) return; + if (intel_crtc_is_joiner_secondary(old_crtc_state)) + return; + if (!intel_vrr_always_use_vrr_tg(display)) { intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), trans_vrr_ctl(old_crtc_state)); @@ -613,6 +631,9 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state) if (!intel_vrr_possible(crtc_state)) return; + if (intel_crtc_is_joiner_secondary(crtc_state)) + return; + if (!intel_vrr_always_use_vrr_tg(display)) { intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), trans_vrr_ctl(crtc_state)); @@ -637,6 +658,9 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state) if (!intel_vrr_possible(crtc_state)) return; + if (intel_crtc_is_joiner_secondary(crtc_state)) + return; + if (!intel_vrr_always_use_vrr_tg(display)) { intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), trans_vrr_ctl(crtc_state)); From patchwork Tue Mar 4 08:19:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 088E5C282D3 for ; Tue, 4 Mar 2025 08:32:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A6A7210E544; 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X-CSE-ConnectionGUID: /2rx2qHxTnuEmXHanBJzow== X-CSE-MsgGUID: WH2vs0oqQguf9gYDYHiSGQ== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910208" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910208" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:37 -0800 X-CSE-ConnectionGUID: 53Yq1gZhQwitZQelkINBCw== X-CSE-MsgGUID: C/HtzeixSZyNx4NiaN+SVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492264" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:35 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 20/22] drm/i915/vrr: Always use VRR timing generator for MTL+ Date: Tue, 4 Mar 2025 13:49:46 +0530 Message-ID: <20250304081948.3177034-21-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently VRR timing generator is used only when VRR is enabled by userspace for sinks that support VRR. From MTL+ gradually move away from the older timing generator and use VRR timing generator for both variable and fixed timings. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_vrr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 2b6d022434d2..bb6825c20330 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -560,7 +560,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display) if (!HAS_VRR(display)) return false; - /* #TODO return true for platforms supporting fixed_rr */ + if (DISPLAY_VER(display) >= 14) + return true; + return false; } From patchwork Tue Mar 4 08:19:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C17EC282D0 for ; Tue, 4 Mar 2025 08:32:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D2BCB10E51E; Tue, 4 Mar 2025 08:32:40 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CqvAyCTl"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0F6BF10E545; Tue, 4 Mar 2025 08:32:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077159; x=1772613159; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AX5vNP1FgTEBHopl9t1dT2LYAOIG7X/6QGVbDEWz1jY=; b=CqvAyCTlESGzN265juDY1ryY5xRagYp9zmc8mzFQ5BJHzqp93BGdk8tV qsjRnQrPMgMaHI6nbLdakzeaclXFq1xjKxGdC5Y1kUVbrn2rABgprMSSs Y0KX5o30UMSVTi1e7iTBaCu/FCAEUwn79Jw+0yZ67DHH7pdKeJAMVPYQl pfSk+RhKXO5pyVnySOpGTsD4v01ym9Am7jjFEqquKUYy0A1tVzf1m0Tcs MWk9jWQmPVPIDBjp2MLsgDrN3SlqnYCpBBPpqksK8LNygFCTpAwTH1z7z B5voUbVy6RL+C2M6gzS2tvdCHJEIuy6HcP1DMg6JcYhAKZ6TSR4a7qsGB g==; X-CSE-ConnectionGUID: de9bzqvXTxO65A7UpW3sYA== X-CSE-MsgGUID: v5wj3s5DSFyoPU/NHUOfhw== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910216" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910216" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:39 -0800 X-CSE-ConnectionGUID: MJVWXQCjQXWQzE/Ae72ISA== X-CSE-MsgGUID: 1sAV00rqQSiqAXKO+VrkXw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492267" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:37 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 21/22] drm/i915/display: Add fixed_rr to crtc_state dump Date: Tue, 4 Mar 2025 13:49:47 +0530 Message-ID: <20250304081948.3177034-22-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add fixed refresh rate mode in crtc_state dump. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 ++- drivers/gpu/drm/i915/display/intel_vrr.c | 1 - drivers/gpu/drm/i915/display/intel_vrr.h | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 599ddce96371..f204a5830c29 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -294,8 +294,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, pipe_config->hw.adjusted_mode.crtc_vdisplay, pipe_config->framestart_delay, pipe_config->msa_timing_delay); - drm_printf(&p, "vrr: %s, vmin: %d, vmax: %d, flipline: %d, pipeline full: %d, guardband: %d vsync start: %d, vsync end: %d\n", + drm_printf(&p, "vrr: %s, fixed_rr: %s, vmin: %d, vmax: %d, flipline: %d, pipeline full: %d, guardband: %d vsync start: %d, vsync end: %d\n", str_yes_no(pipe_config->vrr.enable), + str_yes_no(intel_vrr_is_fixed_rr(pipe_config)), pipe_config->vrr.vmin, pipe_config->vrr.vmax, pipe_config->vrr.flipline, pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, pipe_config->vrr.vsync_start, pipe_config->vrr.vsync_end); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index bb6825c20330..7c9560df81b1 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -672,7 +672,6 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state) intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 0); } -static bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state) { return crtc_state->vrr.flipline && diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 0e1becd7a0c0..780246231d35 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -39,5 +39,6 @@ int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state); +bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ From patchwork Tue Mar 4 08:19:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88362C282D3 for ; Tue, 4 Mar 2025 08:32:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A0C310E547; Tue, 4 Mar 2025 08:32:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SlpW6SgL"; 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d="scan'208";a="45910226" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:41 -0800 X-CSE-ConnectionGUID: ZQHaGxsHRqGq9Z8/5r/xeA== X-CSE-MsgGUID: 0jRMa/2MSJGHLskRKxa2JQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492270" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:39 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 22/22] drm/i915/display: Avoid use of VTOTAL.Vtotal bits Date: Tue, 4 Mar 2025 13:49:48 +0530 Message-ID: <20250304081948.3177034-23-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal bits are not required. Since the support for these bits is going to be deprecated in upcoming platforms, avoid writing these bits for the platforms that do not use legacy Timing Generator. Since for these platforms TRAN_VMIN is always filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for adjusted_mode. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 68 ++++++++++++++++---- drivers/gpu/drm/i915/display/intel_vrr.c | 1 - drivers/gpu/drm/i915/display/intel_vrr.h | 1 + 3 files changed, 55 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c31a87d8afd3..daea0eefc0ec 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -121,6 +121,7 @@ #include "intel_vdsc_regs.h" #include "intel_vga.h" #include "intel_vrr.h" +#include "intel_vrr_regs.h" #include "intel_wm.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -2636,8 +2637,30 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, PIPE_LINK_N2(display, transcoder)); } +static void intel_crtc_set_vtotal(struct intel_display *display, + enum transcoder cpu_transcoder, + u32 crtc_vdisplay, u32 crtc_vtotal) +{ + u32 vtotal_bits; + + /* + * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal + * bits are not required. Since the support for these bits is going to + * be deprecated in upcoming platforms, avoid writing these bits for the + * platforms that do not use legacy Timing Generator. + */ + if (intel_vrr_always_use_vrr_tg(display)) + vtotal_bits = 0; + else + vtotal_bits = VTOTAL(crtc_vtotal - 1); + + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), + VACTIVE(crtc_vdisplay - 1) | vtotal_bits); +} + static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; @@ -2700,9 +2723,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); - intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), - VACTIVE(crtc_vdisplay - 1) | - VTOTAL(crtc_vtotal - 1)); + intel_crtc_set_vtotal(display, cpu_transcoder, crtc_vdisplay, crtc_vtotal); + intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), VBLANK_START(crtc_vblank_start - 1) | VBLANK_END(crtc_vblank_end - 1)); @@ -2716,13 +2738,13 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta * bits. */ if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && (pipe == PIPE_B || pipe == PIPE_C)) - intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, pipe), - VACTIVE(crtc_vdisplay - 1) | - VTOTAL(crtc_vtotal - 1)); + intel_crtc_set_vtotal(display, (enum transcoder)pipe, + crtc_vdisplay, crtc_vtotal); } static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; @@ -2765,9 +2787,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc * The double buffer latch point for TRANS_VTOTAL * is the transcoder's undelayed vblank. */ - intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), - VACTIVE(crtc_vdisplay - 1) | - VTOTAL(crtc_vtotal - 1)); + intel_crtc_set_vtotal(display, cpu_transcoder, crtc_vdisplay, crtc_vtotal); intel_vrr_set_fixed_rr_timings(crtc_state); intel_vrr_transcoder_enable(crtc_state); @@ -2805,6 +2825,29 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; } +static void intel_crtc_get_vtotal(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + u32 tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)); + + adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; + + /* + * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal + * bits are not filled. Since for these platforms TRAN_VMIN is always + * filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for + * adjusted_mode. + */ + if (intel_vrr_always_use_vrr_tg(display)) { + tmp = intel_de_read(display, TRANS_VRR_VMIN(display, cpu_transcoder)); + adjusted_mode->crtc_vtotal = tmp + 1; + } else { + adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; + } +} + static void intel_get_transcoder_timings(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { @@ -2829,9 +2872,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; - tmp = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)); - adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; - adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; + intel_crtc_get_vtotal(pipe_config); /* FIXME TGL+ DSI transcoders have this! */ if (!transcoder_is_dsi(cpu_transcoder)) { @@ -8192,8 +8233,7 @@ void i830_enable_pipe(struct intel_display *display, enum pipe pipe) HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); - intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), - VACTIVE(480 - 1) | VTOTAL(525 - 1)); + intel_crtc_set_vtotal(display, cpu_transcoder, 480, 525); intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 7c9560df81b1..8631d97d0291 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -554,7 +554,6 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; } -static bool intel_vrr_always_use_vrr_tg(struct intel_display *display) { if (!HAS_VRR(display)) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 780246231d35..3908e7e3c0e9 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -40,5 +40,6 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state); bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state); +bool intel_vrr_always_use_vrr_tg(struct intel_display *display); #endif /* __INTEL_VRR_H__ */