From patchwork Tue Mar 4 12:00:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 14000618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43581C282D3 for ; Tue, 4 Mar 2025 12:10:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=C0+VCgio1tUjlLnBhjdP1KU//uFP0aIvLX5Mxj6nLmk=; b=KBwJbPQl1j56xu jrZlQoNyHoBBsyxVLqskeCAYdUmO8o+KhK2FYqZWEX+iOz2ttrou68bc92ETluueFPvw917NTWHcU nhL7W+oo+M/QQ1qa6TFK61ktuChu0qZBg47dHv+65IOn+0qw0yfFXRD7gUR0yRD8MSenHLHA4YYiS bVVtdp6Rc75jh0/eSlo+wuQx89RnE7PnIn3A/tGEq0nlEe8wT6ZuIVD9gRf2epaYS4QjE7wkb18Pc QXPlQfnitPFgqqXymp/eAdTETvabqlNhnoMeNLSUEzFjjm8t9k+8ohKDTONjrRQttcqm5ifAKr/GR j6v/tNDOOZ+kZIX/KJqA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpR6f-00000004ZbJ-3EHk; Tue, 04 Mar 2025 12:10:41 +0000 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpQwc-00000004V6I-2fa5 for linux-riscv@lists.infradead.org; Tue, 04 Mar 2025 12:00:19 +0000 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-390dd35c78dso3565634f8f.1 for ; Tue, 04 Mar 2025 04:00:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1741089617; x=1741694417; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dsOXXT+GJOZQxfHaJbyOnCfiUI8BUwrK26GnKW4Oj7U=; b=oL8pxaaUCRitafsnnNsvDLJvjnRvI9fXlAims+FMhe4T6JlX0FeYfuRFy1K7COLTQd iGSL3k/P6E+QLB4T1sbmyLJtszq7HrpB3rNt87Bxu3pmsIgLscPbh98Jk/fuw1ZXQty7 rI9Wv+WLPuMmFfcmPvtQG3NwZ/6xg7zhPR/VdNiLflMwluUNGzGgX35g1TOfqJbvo8iE 4mZrHhevWqsrPLWzptp9q71lQACTq281YxS43SReVZphRq96aAFCIsRAs0cB9mORK7w5 Go6/2wk/Z0uFDaNqBS4JS99YjzQR6VohYKH1YRHVPEb7S0d7raGOzwkLPpxGMC8ZcCBZ 0QAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741089617; x=1741694417; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dsOXXT+GJOZQxfHaJbyOnCfiUI8BUwrK26GnKW4Oj7U=; b=JGrMe8oDFy1w1CzDDz95c8u+IcyhSnKHaVo+ZlBUakkaOsY1C8CCVMzJ9Gz5T64DeW 26XASx43Q/gHBaNJbOZx0IELRc97SoquocTGFKZiSgSLEkhP6URk1KFuXVhsV7zkPno9 jllT8eO/hbgfTEvZ1mICAeNCywNrbefR+tpOq/sUz6p7RMtRHNy9of91aWL2UvfLVo4O uVWmAfFEfQU+9HRP5Dj8K7zKKx5hGrGdKSzSdjVs1JfiGKUhtNE9TjXFriqNmbJ7UgiS FhNt3oyc8euUqFR8KtxFXLMaTTvDNiodjYH+AAGIwL3b3ASUAkLWNE2TnaNf0M89uQ5z uneg== X-Gm-Message-State: AOJu0Yz2065hzUxhCY7cfs6+WqiD580mT1WTC6l2LyfOSrUtOF62C7H+ YySG1yqAmKSR5E5eF7XntqgS6EnEVUiZseIchYq/u7HHpbpuTikMAj8veKcaSoyfHDjSV17jgO8 k X-Gm-Gg: ASbGnctgxcUnYYHO3HZlkrSoBmb3fgWlBlFMteyT9azM2lhCF5vmr3BrPVwZPO6c19s 9E1MHgsmSYsTI0crZ/CQeKKKp+U+3ARDf3rgMJ/ezjEnFCJZ4dZsxtJsDdY/ytADU/Rvn3gAMu4 xF4aR28tZTtaQ3/iHLHG51bAw9z2JCueJxuqv1UKP6M1WQYat4xSa2Hl+Vme6IY9AG/qKGT5/9/ Xp0kDVP6+tN9p3gX+NkUgicB4o+kfnbWFWZIj8H0FtxoijrMW39eAEww38d6pSDkHDS3tVXpN3/ G1fwTw5nOI1e7a3BPJ90foO3Wxu/6H7h X-Google-Smtp-Source: AGHT+IHfvp/euog7c3Gu4POXjA8Lq4HBzrln9LMIjOKJFZe5dI3SCeWKlW6YsuSzufoq3FjOtkj5Fg== X-Received: by 2002:a5d:59af:0:b0:388:c61d:4415 with SMTP id ffacd0b85a97d-3911560f325mr2216933f8f.18.1741089617020; Tue, 04 Mar 2025 04:00:17 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::688c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e4844ac6sm17312025f8f.71.2025.03.04.04.00.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 04:00:16 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, cleger@rivosinc.com, alex@ghiti.fr, Anup Patel , corbet@lwn.net, Alexandre Ghiti Subject: [PATCH v3 1/8] riscv: Annotate unaligned access init functions Date: Tue, 4 Mar 2025 13:00:16 +0100 Message-ID: <20250304120014.143628-11-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250304120014.143628-10-ajones@ventanamicro.com> References: <20250304120014.143628-10-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250304_040018_675493_72BC8693 X-CRM114-Status: GOOD ( 10.56 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Several functions used in unaligned access probing are only run at init time. Annotate them appropriately. Fixes: f413aae96cda ("riscv: Set unaligned access speed at compile time") Reviewed-by: Alexandre Ghiti Signed-off-by: Andrew Jones --- arch/riscv/include/asm/cpufeature.h | 4 ++-- arch/riscv/kernel/traps_misaligned.c | 8 ++++---- arch/riscv/kernel/unaligned_access_speed.c | 14 +++++++------- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 569140d6e639..19defdc2002d 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -63,7 +63,7 @@ void __init riscv_user_isa_enable(void); #define __RISCV_ISA_EXT_SUPERSET_VALIDATE(_name, _id, _sub_exts, _validate) \ _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate) -bool check_unaligned_access_emulated_all_cpus(void); +bool __init check_unaligned_access_emulated_all_cpus(void); #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) void check_unaligned_access_emulated(struct work_struct *work __always_unused); void unaligned_emulation_finish(void); @@ -76,7 +76,7 @@ static inline bool unaligned_ctl_available(void) } #endif -bool check_vector_unaligned_access_emulated_all_cpus(void); +bool __init check_vector_unaligned_access_emulated_all_cpus(void); #if defined(CONFIG_RISCV_VECTOR_MISALIGNED) void check_vector_unaligned_access_emulated(struct work_struct *work __always_unused); DECLARE_PER_CPU(long, vector_misaligned_access); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 7cc108aed74e..aacbd9d7196e 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -605,7 +605,7 @@ void check_vector_unaligned_access_emulated(struct work_struct *work __always_un kernel_vector_end(); } -bool check_vector_unaligned_access_emulated_all_cpus(void) +bool __init check_vector_unaligned_access_emulated_all_cpus(void) { int cpu; @@ -625,7 +625,7 @@ bool check_vector_unaligned_access_emulated_all_cpus(void) return true; } #else -bool check_vector_unaligned_access_emulated_all_cpus(void) +bool __init check_vector_unaligned_access_emulated_all_cpus(void) { return false; } @@ -659,7 +659,7 @@ void check_unaligned_access_emulated(struct work_struct *work __always_unused) } } -bool check_unaligned_access_emulated_all_cpus(void) +bool __init check_unaligned_access_emulated_all_cpus(void) { int cpu; @@ -684,7 +684,7 @@ bool unaligned_ctl_available(void) return unaligned_ctl; } #else -bool check_unaligned_access_emulated_all_cpus(void) +bool __init check_unaligned_access_emulated_all_cpus(void) { return false; } diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index 91f189cf1611..b7a8ff7ba6df 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -121,7 +121,7 @@ static int check_unaligned_access(void *param) return 0; } -static void check_unaligned_access_nonboot_cpu(void *param) +static void __init check_unaligned_access_nonboot_cpu(void *param) { unsigned int cpu = smp_processor_id(); struct page **pages = param; @@ -175,7 +175,7 @@ static void set_unaligned_access_static_branches(void) modify_unaligned_access_branches(&fast_and_online, num_online_cpus()); } -static int lock_and_set_unaligned_access_static_branch(void) +static int __init lock_and_set_unaligned_access_static_branch(void) { cpus_read_lock(); set_unaligned_access_static_branches(); @@ -218,7 +218,7 @@ static int riscv_offline_cpu(unsigned int cpu) } /* Measure unaligned access speed on all CPUs present at boot in parallel. */ -static int check_unaligned_access_speed_all_cpus(void) +static int __init check_unaligned_access_speed_all_cpus(void) { unsigned int cpu; unsigned int cpu_count = num_possible_cpus(); @@ -264,7 +264,7 @@ static int check_unaligned_access_speed_all_cpus(void) return 0; } #else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ -static int check_unaligned_access_speed_all_cpus(void) +static int __init check_unaligned_access_speed_all_cpus(void) { return 0; } @@ -379,7 +379,7 @@ static int riscv_online_cpu_vec(unsigned int cpu) } /* Measure unaligned access speed on all CPUs present at boot in parallel. */ -static int vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) +static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) { schedule_on_each_cpu(check_vector_unaligned_access); @@ -393,13 +393,13 @@ static int vec_check_unaligned_access_speed_all_cpus(void *unused __always_unuse return 0; } #else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */ -static int vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) +static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) { return 0; } #endif -static int check_unaligned_access_all_cpus(void) +static int __init check_unaligned_access_all_cpus(void) { bool all_cpus_emulated, all_cpus_vec_unsupported; From patchwork Tue Mar 4 12:00:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 14000620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5CCE9C282D0 for ; Tue, 4 Mar 2025 12:10:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=I1DnT6sZyI5qTF4jDohntVLmIllhQRLXXojCtZHnxVs=; b=nGaY61/jQbrVy8 yHaNMhe+057FSiqiFfqVe/7fEPwO7Hx9wlpluS84UhDs5loqj5AyM48KSVyTRgCaHm9Fos+RaB+Iu OOd6p8I6HvHNJZcODOZGei70tXU+xqOlysVTjdmaJ6cfhntwSIyr7x0wqDuiypRfZurTsjUc7+XlC c6+gt5Odi81wJSsuIM+BVXxHcBch1hvgZ1O1t+adUWHOv2d7PxiPvA4AGfY0jKShOgQox4WnRPGWK 7xAKczpCt5A365a+N/BKM+MITvjuYxfTuIkVB73bRDaVg2mRnGX3dXbWQKm0yBFnmjL7OLQBPBxVC yDgVdkh47ZRSlH0LxsnQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpR6h-00000004ZdM-0V6X; Tue, 04 Mar 2025 12:10:43 +0000 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpQwd-00000004V6y-2Car for linux-riscv@lists.infradead.org; Tue, 04 Mar 2025 12:00:20 +0000 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-439846bc7eeso35510355e9.3 for ; Tue, 04 Mar 2025 04:00:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1741089618; x=1741694418; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XoVXTPIMs1CQCffXwitKYw9GB5bSc15mRPYc+pFsBJQ=; b=bp9uWF/N3m9h7O+QY06iRMaRtgfJDK0MphoD9+ygt0i1yZz6/cEAtZ664ccuBA9PCt yYBGmlexx+g5GirY5zgl6ovFNfeZGdqsQSCBPdUsQzqPEyVplhCvd+icF0IZrFrnSkFe Es08vzviMY1gQ+a5yeQh7UTI+ocXN1gc0mCnfALBFZODzkFHG3fjzbmg0HQUGLHcnax2 v9cRh4QT8RojLp5wVJBfFs+W+I6UrWYgxpTNNzTA3bYSD3Oz5aXi4Wfj+AdG5TMdaKwv f+/0cXLk26vhB4E2NM+uztaISf9gxESgGcZSV5PwM48clAXzQ/gcGmxhyQKzKJdFJq/6 aVHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741089618; x=1741694418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XoVXTPIMs1CQCffXwitKYw9GB5bSc15mRPYc+pFsBJQ=; b=kKPpLatTeE5qpvmE3xbOS9P6KkLViQuX+M7rzybbllOFYbu387Je8AGB+G3uUEl/zF VHCRAgcdbkHDL6P/Jiso9KuBzGaxSNGYHUa+hlIORoaWawv/9EedKrqP7y//CeL1t1yU /mw4uPgU/wuhip6jq1wD72BxGuIgtC3iwaO2DcawpS+JTJuD72bA9u/2LLdqnEf952oD JJi2NL1rwtKGyCm+WFY3XE+/b5HkJM28guE5P4mg5AExJ9gNod5kki/dGXOSq82nNCzD /qrhGrSS+CryBF4oxZZ/PUUAjbAtLJwWpbn5cbL1V1zRByWXHiDKXeI+arI5TE6Tnh/A M9BA== X-Gm-Message-State: AOJu0YzgRviYN/lRR4xDLdkzHaFog/mH53P06ETl80ZoTpsGjjlBvH4t GqgXVKNJ3oY2OX/pwMcUUe4KE3pZ/fyPliwPmAunYVnd4TBkTR4anKG2I2a/OpcHt9bUqH/nF1G K X-Gm-Gg: ASbGncuK9et5n6u9lFIYHnFgE9zLGywreMbWs2ny8rAfkgz1v2leSpVEXrZE3qipp5M lr4nO2fYvju0VZUkzIBjeJJI8yWtGP+g1UC77izbimyOyPvJqqhzrrE/jWAWxmDqS6Hbz3p0yS8 jSLJqLqg4Vrmqz3cMjk7/Q6gcKj3wsVelCwDHBc2vZB7ilj2XIAw1GNrZnMh78A91myWm8J6plv UwpfQsOnCrZTEUmcNZktI+JfAYChwT9I7aPRSp5v99H4adG0RKIoa9kqKu7K4YNoi5iuoGSUajT iBJmO9CkXIjNxiEuDr9x6u5Sr7lDfOex X-Google-Smtp-Source: AGHT+IGSlj+jarr0JPc4Azcvd/gVJrRnnAK8bPpcD6KvNf1uMYM/W8wrPief42jLDcp+dxdCRnmVUw== X-Received: by 2002:a05:600c:19cd:b0:439:8346:505f with SMTP id 5b1f17b1804b1-43ba6747836mr129232375e9.20.1741089618179; Tue, 04 Mar 2025 04:00:18 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::688c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e485e13fsm17295914f8f.100.2025.03.04.04.00.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 04:00:17 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, cleger@rivosinc.com, alex@ghiti.fr, Anup Patel , corbet@lwn.net, Alexandre Ghiti Subject: [PATCH v3 2/8] riscv: Fix riscv_online_cpu_vec Date: Tue, 4 Mar 2025 13:00:17 +0100 Message-ID: <20250304120014.143628-12-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250304120014.143628-10-ajones@ventanamicro.com> References: <20250304120014.143628-10-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250304_040019_563831_571190D5 X-CRM114-Status: GOOD ( 11.65 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We shouldn't probe when we already know vector is unsupported and we should probe when we see we don't yet know whether it's supported. Furthermore, we should ensure we've set the access type to unsupported when we don't have vector at all. Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe") Reviewed-by: Alexandre Ghiti Signed-off-by: Andrew Jones --- arch/riscv/kernel/unaligned_access_speed.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index b7a8ff7ba6df..161964cf2abc 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -367,10 +367,12 @@ static void check_vector_unaligned_access(struct work_struct *work __always_unus static int riscv_online_cpu_vec(unsigned int cpu) { - if (!has_vector()) + if (!has_vector()) { + per_cpu(vector_misaligned_access, cpu) = RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED; return 0; + } - if (per_cpu(vector_misaligned_access, cpu) != RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED) + if (per_cpu(vector_misaligned_access, cpu) != RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN) return 0; check_vector_unaligned_access_emulated(NULL); From patchwork Tue Mar 4 12:00:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 14000621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F806C282D6 for ; Tue, 4 Mar 2025 12:10:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GkR79wiuhsu0+PIfkmWVmXvotHR7UmV5EAxnnDOMpEY=; b=kJkNlBsMTGKWvb BrUQZmN4DNqh7q7kNSksznYOiNzVYFci4fVvq+MbD12rG9mgPqc75e+mVNeeRHYn6Ey5tQAf1n1Qb 1Wvm6f2AwWeb5Two3EM7BpeEjxPzcThFZM6b8vGkfduE7EL4Uu1dVQBIAhVnAnO2ghN4lBajDy8fF JL6NungdfFyXwQUDu6cAVhctojvlNV1wW/M8Xh0LetylN3Ia1t3U2fusu8iV0Cyx/ZlUlsW7slpUs kYDrkhpTF7VwzrbBAZ1bJ2PjRqyEnmlUrsJ0eHEnSOnnujB6jdZY6Yv4zFUFY0KOL9LRoVr5Hojed i4pkMcp0+ImlkrfFvIlA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpR6i-00000004ZgG-1xy2; Tue, 04 Mar 2025 12:10:44 +0000 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpQwf-00000004V7o-1znZ for linux-riscv@lists.infradead.org; Tue, 04 Mar 2025 12:00:22 +0000 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-390f69e71c8so2289717f8f.0 for ; Tue, 04 Mar 2025 04:00:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1741089620; x=1741694420; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BL25umXnpXBBzwUoMnOj2fRLliDIrDaDucRmmKK49J0=; b=lA+d/neL0HjIX7rppyGjdcewmWAeSS0BQEymuWOMd21+h3eyT/7nWgrf5k3TLznk6F DD63vkAqOVRSCpvdVX1WAwOsaqHVf3Jhi4Yr8jn8MPeZDE8cSF8nchpW03hTzl7r7YkY oOW5WY2EMtfHwD6xFLOmDRQjmR1Y2IbhjWVdjkudO/g+3WmU29rs67+S10tf4VDOl5Dg T8FAlFLQ18EnqDcUKzV1AhiWQXyuzkbfx55dJPdP5sJ0KAxAkR+2hT86KzTJ9JNhNr4k B6m9Q+YGt317E5Kk026f7G9DtjKtxuXUU1eFZyRbHeqYZbTop9Eow8FA0TQHpLSkhNyp xTjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741089620; x=1741694420; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BL25umXnpXBBzwUoMnOj2fRLliDIrDaDucRmmKK49J0=; b=XLDQRKtHqUBpg91dlevJ64q+AUpwZx85zIuJ5xKKMkRZi4BJ9xPxYXB/i2PUc2/huT L7SL91Fc/UIkAjXIU6SiC0lDLt1OAkzLyHWkDoJT+GtF9rXv1zs6EuiUHHmpI9IFG9wB QCRdm1K/gI/iiUrgm4C78BK3rJwXZGTRektjSe0GzYXx62rofclFAMLE36aHG6JSI8O6 +g7PVPsIH0EtvEEISK3+vO0iH6keUATVdYQsPyZA6eYVIMDOK4L9Vw0fNYAosBKGoUpo ojUp9k91O7wSLab2rlP5Dr68YZrXGM9mDbLkXWSkxuMcwkpmChH+heJOioqgooRsHGRD vwcQ== X-Gm-Message-State: AOJu0YzqddKv9izElx0Z3jih0eIbZID+w1ebMq3KctAqxfxU2x37kmu+ HpxoFG/7NtmVrWEPQRSD7nKf2S8abjWBB0ZdsnByfqRZfKCE1EgtnirGIf9pyBpeU/GCmrU/bGy a X-Gm-Gg: ASbGncsuWk7Msr9SIMvNomT+sDOEZ9s8rJJ822ysqxociMKS3kjrdV82QxB9JM4ACfV 1DWcTzJQ7CNaMhOLTn0cN5GxK4RS/ruC1nhgeYT0y0DNRl/i3FaW2MbMMvFJAo3QF2+OSrEf06u 4CzhDtcWZO6pp5O1h9PmwqY9T8oiW62YsHcIWEUXygTfXS3ESaaHa1+/+HjTMzhzRl+GrIp6q85 3pRSOCBjx98ik7/t/Neme4lk9NVa53aqwNUkSnE3BNGDfZ6SpP1+fupKP5OxSRV7SbhjsaOHF7u z4zZQCJHprKaTqNHKbdWgnqYTS1wW/zo X-Google-Smtp-Source: AGHT+IHGl4juoP1IGvAETEutihGGilncidBGnRXIsTr2+3oea3NO/pXu/tqvOIeNlFeGq7iMlTLrtA== X-Received: by 2002:a5d:64e8:0:b0:38d:df15:2770 with SMTP id ffacd0b85a97d-391154af01cmr2483532f8f.0.1741089619498; Tue, 04 Mar 2025 04:00:19 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::688c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bcbdf7a9esm21728565e9.13.2025.03.04.04.00.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 04:00:19 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, cleger@rivosinc.com, alex@ghiti.fr, Anup Patel , corbet@lwn.net, Alexandre Ghiti Subject: [PATCH v3 3/8] riscv: Fix check_unaligned_access_all_cpus Date: Tue, 4 Mar 2025 13:00:18 +0100 Message-ID: <20250304120014.143628-13-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250304120014.143628-10-ajones@ventanamicro.com> References: <20250304120014.143628-10-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250304_040021_514340_307B09CD X-CRM114-Status: GOOD ( 12.77 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org check_vector_unaligned_access_emulated_all_cpus(), like its name suggests, will return true when all cpus emulate unaligned vector accesses. If the function returned false it may have been because vector isn't supported at all (!has_vector()) or because at least one cpu doesn't emulate unaligned vector accesses. Since false may be returned for two cases, checking for it isn't sufficient when attempting to determine if we should proceed with the vector speed check. Move the !has_vector() functionality to check_unaligned_access_all_cpus() in order for check_vector_unaligned_access_emulated_all_cpus() to return false for a single case. Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe") Reviewed-by: Alexandre Ghiti Signed-off-by: Andrew Jones --- arch/riscv/kernel/traps_misaligned.c | 6 ------ arch/riscv/kernel/unaligned_access_speed.c | 11 +++++++---- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index aacbd9d7196e..4354c87c0376 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -609,12 +609,6 @@ bool __init check_vector_unaligned_access_emulated_all_cpus(void) { int cpu; - if (!has_vector()) { - for_each_online_cpu(cpu) - per_cpu(vector_misaligned_access, cpu) = RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED; - return false; - } - schedule_on_each_cpu(check_vector_unaligned_access_emulated); for_each_online_cpu(cpu) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index 161964cf2abc..02b485dc4bc4 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -403,13 +403,16 @@ static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __alway static int __init check_unaligned_access_all_cpus(void) { - bool all_cpus_emulated, all_cpus_vec_unsupported; + bool all_cpus_emulated; + int cpu; all_cpus_emulated = check_unaligned_access_emulated_all_cpus(); - all_cpus_vec_unsupported = check_vector_unaligned_access_emulated_all_cpus(); - if (!all_cpus_vec_unsupported && - IS_ENABLED(CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS)) { + if (!has_vector()) { + for_each_online_cpu(cpu) + per_cpu(vector_misaligned_access, cpu) = RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED; + } else if (!check_vector_unaligned_access_emulated_all_cpus() && + IS_ENABLED(CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS)) { kthread_run(vec_check_unaligned_access_speed_all_cpus, NULL, "vec_check_unaligned_access_speed_all_cpus"); } From patchwork Tue Mar 4 12:00:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 14000622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35616C282D9 for ; Tue, 4 Mar 2025 12:10:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KGYBBpwnt3hWw/5C3fwSPGMNcDYClNDq6N78sbu4zpg=; b=btKLtDQN2+6k51 Run7KfTTmOdg7kvq4A6329MkD+yS6CJwpRblCtYxaRrwNiOrxEifPFZG7+w8xEJhy1ukCzrJNqDMQ PewFZ/qKT+F7IddRZ9XjWUKGaN4B0jBFMVWC8kp1peDJpwMc3XmTurbO5VVIJXRYbbGVBOv20XLoS MF89A1a4Yd9xJKiL0r+OcE1qvJB8ctI8z9my08oSaahpmn0NCJQIjgglNnekb1DabA09G5tTQDGza RSUjlvtMIjWD01skmQvfGFeQ2hwEqdipPYQNL0EJy9JNBWdBsronSmEsu6a9KAWEqscM5kMUmuyxu vHYnccRnGkQAeHmE9t5Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpR6j-00000004Zhc-1vR4; Tue, 04 Mar 2025 12:10:45 +0000 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpQwg-00000004V7u-1Qr5 for linux-riscv@lists.infradead.org; Tue, 04 Mar 2025 12:00:23 +0000 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-438a39e659cso37699295e9.2 for ; Tue, 04 Mar 2025 04:00:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1741089621; x=1741694421; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v5+0DAJFyGg9dqAHMt/74M2g7aCiRWRLOEFqoe5G5I8=; b=KGxWbbLwsAQdDJQi8q2Vn7Df2w0luLTHHOKGEmn457XByLwx2ugI2SiqO5eJSFPvKp CCwf8rvdezJd9fluJWrmI4g5fFO+DHLEzrq4GCiLDum7pWexRMmdXa+ar+o1+l1bDSNB vC2S6BCYnyhiWFAZbXEg6MdZvAS7R3ijB8WrqQYa77/ecMEfr6SQbyaVAZmVvFTlAQfs gbS9x757m/59x6W7pZES8bvLcHiL3uKUhb/dU6MMixElOlVYlde1IU5IuEO+Re4Gl2oF Cz1zguEOLE8tFp9sHd6ihOF02U2/v1PKR2V1a12je5YVxkoDSoC8Oj1F8tsSxmGe3vAw EpVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741089621; x=1741694421; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v5+0DAJFyGg9dqAHMt/74M2g7aCiRWRLOEFqoe5G5I8=; b=kdmGDrhCl6/VUzyFq/wMxIcwFYHsGBu5nZX8EAT4PVhH+mW7qI+3941ZMS4wsS5UdE LIjzLUwRvz03zC5NIycW5Mpre61wWI1SsJdV/OlkdThu/CrZePwoJjrm0ug1pELi018U jFFsoCf88CVd6kV4Yolwd2tEKdAZjSqAWgnWjMdIXT65VgwGdBhjA2cDOLCfLGEHeXUU ZRn2ztFB02aKGoPwoLVwWRf5rnpZxTuy4UowzTORtzwpERyKMfLdXFqeQRvcl8nc5oUw TKWfOtpLAX/8U5I/DYQ2QQsg9Cxk2oy2OwyhsE9Dj9sGdzTkYxE8Gb7xCNCBul/Cc6ff RCBg== X-Gm-Message-State: AOJu0YyLt3HNZnEjMZ2+RpWdeKy6wHqaiMXh9zJSEFNgkTO3QjjzkSBy w1BjLMZJWJEPkOis9yUzJd9FGtvYmos1wPi2/5Zw1SOnH22AKUPNlPwHWKX/7+jOgLYRQUymbhu e X-Gm-Gg: ASbGncserPuDSD9imBBcdGAvvjiavw2jmY/nTL/8GdqPsyLAM1KHgHz94LbQTcxb3kR 7EeOvcdloxL/hQealPjX2IoQ5zx0cRm9lK3vlxy6Ap3UCGCA8smxS1zx972DesqBbWmYX0HlqBB DKGhPmyIW0GOklhY8k91QDI8W3Sr/JwxvWdHcscoBYtnibOMP6g0JCX/BloACl2bbngIuShFs37 wH5RGmIuvT+eTnv54Ejbg7aQDMhtAwDQeS4CrqfnRHzmF50oLfrF3M5nqMCxk7NH9vcdBRbfngE 0bi29akOUJWf7ykQllqXdONqyWnONZe2 X-Google-Smtp-Source: AGHT+IEqMgV5t8PcK9JSG+SOO4LPXPlwofpngejjCplSgEhGn5nYR0XjUC86Q3nC0sypwkMwdVM5mQ== X-Received: by 2002:a05:600c:4693:b0:439:8523:36cc with SMTP id 5b1f17b1804b1-43ba66e66d7mr161122735e9.11.1741089620734; Tue, 04 Mar 2025 04:00:20 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::688c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e4795962sm17966864f8f.13.2025.03.04.04.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 04:00:20 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, cleger@rivosinc.com, alex@ghiti.fr, Anup Patel , corbet@lwn.net, Alexandre Ghiti Subject: [PATCH v3 4/8] riscv: Change check_unaligned_access_speed_all_cpus to void Date: Tue, 4 Mar 2025 13:00:19 +0100 Message-ID: <20250304120014.143628-14-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250304120014.143628-10-ajones@ventanamicro.com> References: <20250304120014.143628-10-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250304_040022_379179_F023380F X-CRM114-Status: GOOD ( 12.17 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The return value of check_unaligned_access_speed_all_cpus() is always zero, so make the function void so we don't need to concern ourselves with it. The change also allows us to tidy up check_unaligned_access_all_cpus() a bit. Reviewed-by: Clément Léger Reviewed-by: Alexandre Ghiti Signed-off-by: Andrew Jones --- arch/riscv/kernel/unaligned_access_speed.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index 02b485dc4bc4..780f1c5f512a 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -218,7 +218,7 @@ static int riscv_offline_cpu(unsigned int cpu) } /* Measure unaligned access speed on all CPUs present at boot in parallel. */ -static int __init check_unaligned_access_speed_all_cpus(void) +static void __init check_unaligned_access_speed_all_cpus(void) { unsigned int cpu; unsigned int cpu_count = num_possible_cpus(); @@ -226,7 +226,7 @@ static int __init check_unaligned_access_speed_all_cpus(void) if (!bufs) { pr_warn("Allocation failure, not measuring misaligned performance\n"); - return 0; + return; } /* @@ -261,12 +261,10 @@ static int __init check_unaligned_access_speed_all_cpus(void) } kfree(bufs); - return 0; } #else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ -static int __init check_unaligned_access_speed_all_cpus(void) +static void __init check_unaligned_access_speed_all_cpus(void) { - return 0; } #endif @@ -403,10 +401,10 @@ static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __alway static int __init check_unaligned_access_all_cpus(void) { - bool all_cpus_emulated; int cpu; - all_cpus_emulated = check_unaligned_access_emulated_all_cpus(); + if (!check_unaligned_access_emulated_all_cpus()) + check_unaligned_access_speed_all_cpus(); if (!has_vector()) { for_each_online_cpu(cpu) @@ -417,9 +415,6 @@ static int __init check_unaligned_access_all_cpus(void) NULL, "vec_check_unaligned_access_speed_all_cpus"); } - if (!all_cpus_emulated) - return check_unaligned_access_speed_all_cpus(); - return 0; } From patchwork Tue Mar 4 12:00:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 14000623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA6A0C021B8 for ; Tue, 4 Mar 2025 12:10:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=i9fDrrYpNE0FocQ/dpWLcBDDyuVQdM6n1DalHmOzbCk=; b=tm7/LlcbsqQIIZ J6efxyVLe0gzVSqpnJrJfGjW4TsGVNzWhaYMi1C289VkRUxuuEdVChooaRru7T9boZNBNaEK58x8S gRnjQBMXLhSJJZqrDCHgHPAHrZxFJOHqo09H8mR/l3uZS4gI53qrer4e3l2yZ3vVzXZbco6ikHIvb qoxvkX72eK//bRDpfWW3eR70u1u0jcwYy9FwlfH89v63l/l0byrRvjOtPNfuM/Nt3l9wrr493a64C d/WLAx3L+A2nX0BrZIV/y3213QGuCqT+/KP9PR68kRLFnWbVrtrkHkjXjQCPFx23dAS50uSH9rCyv rPfHK1DElfPaOZkkkxRA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpR6k-00000004Zj1-1aRS; Tue, 04 Mar 2025 12:10:46 +0000 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpQwh-00000004V8M-26aR for linux-riscv@lists.infradead.org; Tue, 04 Mar 2025 12:00:24 +0000 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-390f5556579so2145538f8f.1 for ; Tue, 04 Mar 2025 04:00:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1741089622; x=1741694422; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wuV5PBYNprCWaplq1fE9KG6ZTDkt+mehdrAbLFdmJ0U=; b=M6mit9Wa9WzsEGxd1TaedSBng5J5cr6fQZUvTwkHvOnT1WRNoE+NGzSeXDRgHEtNFv GdOvXCLNhBAiBTYOUpcAd+tgWjDgBDy07Mnz0tgwQpbCqjORJuj2ordhctYnLWWJokYs FSPOToK65v2rEgec0vAzPU1W+7yyx+s1Nos/Ti9FZH3t5eHrGkC0LBO3jKj4UVvTKW1f 1T8RRrVuUUB8QL7/tzRZcgZdYKtoaFTmD9pyrGzON6IAUDVfb1FIC/HNY0uKaUeI6bQr 5h50JnxgOpXnJzaTSWo63n7hdCNqnVBkttvro2Zd2nvIInLsFoaOy+BN7O4DFtYI9CyY yYAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741089622; x=1741694422; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wuV5PBYNprCWaplq1fE9KG6ZTDkt+mehdrAbLFdmJ0U=; b=S33+HCJ2MvGRr74BOurbzNmC6moYIZd8gCa2V6EvmdCYUvKxEaZMJ+PIFOBfgSGcwn 5f7TWK4paGSJSH5dSeamP0fXTYiJ9P1PM4/cdj34+ch7cTW6mlloOysJFXoY9ue9hyn8 /Ivv8q6AxyKTmiLjUtSRC093lsZr69qb2U5uXRxHCuXYnG7OEvd2C7MBs3CFlBRprCPW fvKntx0OfBMTT1KraaxErrg/9PNEkK65vzor1lV7XekLN7NBJ5LOZ9oMNLuWnhgDnixl uAuOwanvAv9AMniUqXCRdvRJ/etNV9CucOuEz973c0sHNO4lyeFEeDkhZaMO4+kep9Mk 3p7Q== X-Gm-Message-State: AOJu0YxzhBSoE+r9CSiKbU6zuhkjyRAK20R8LuxeHGo+CUqWcO/4r3hn VaQuvnok4V524BEi50nFdjpal9FvvaTrTWxnx+NAgrttpPUhTkINtmIZlGSyYxXjzMgQpIaJD4P M X-Gm-Gg: ASbGncsOfn0knCnV+hKxq8NfF6mjFeKmet+E4a9FubokrcvDYC7rkWuzA4EJ4lpmvD9 Vn0JS4yIWBrOWtYw5AbApIdHQmSQqHepY7HvwGaKvCiOfXO3Rg165RSDguuA4WGtYeE/izSZYCT zror2QJydt2ZERImoEUIDt6nTV+Izugbahp84ImdJdhSozDJgY7w2Mb04K+Ipe5M+z/t7quGd8g VxisADfvTMeJ/9cmKZZzQJmF/P7vbg6OjyWAX0ZWHzUZh51PZCl7JAt8VaH530KMvJtho6Rk6wa ZPiH+5wENBb6/r2xXY7QK7JflWrKcDZF X-Google-Smtp-Source: AGHT+IGcci4G63CqfkUGtRt/jLkQ1vLNMVzi6Jgp49YWUaQ3MwCP8mUgjvhFVQaeb/Hx3FHq79pKNw== X-Received: by 2002:a05:6000:42c9:b0:38f:43c8:f765 with SMTP id ffacd0b85a97d-390ec7d2e69mr10172733f8f.26.1741089621937; Tue, 04 Mar 2025 04:00:21 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::688c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e4844892sm17593655f8f.64.2025.03.04.04.00.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 04:00:21 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, cleger@rivosinc.com, alex@ghiti.fr, Anup Patel , corbet@lwn.net, Alexandre Ghiti Subject: [PATCH v3 5/8] riscv: Fix set up of cpu hotplug callbacks Date: Tue, 4 Mar 2025 13:00:20 +0100 Message-ID: <20250304120014.143628-15-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250304120014.143628-10-ajones@ventanamicro.com> References: <20250304120014.143628-10-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250304_040023_540049_8486DA8B X-CRM114-Status: GOOD ( 13.42 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org CPU hotplug callbacks should be set up even if we detected all current cpus emulate misaligned accesses, since we want to ensure our expectations of all cpus emulating is maintained. Fixes: 6e5ce7f2eae3 ("riscv: Decouple emulated unaligned accesses from access speed") Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe") Reviewed-by: Clément Léger Reviewed-by: Alexandre Ghiti Signed-off-by: Andrew Jones --- arch/riscv/kernel/unaligned_access_speed.c | 27 +++++++++++----------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index 780f1c5f512a..c9d3237649bb 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -247,13 +247,6 @@ static void __init check_unaligned_access_speed_all_cpus(void) /* Check core 0. */ smp_call_on_cpu(0, check_unaligned_access, bufs[0], true); - /* - * Setup hotplug callbacks for any new CPUs that come online or go - * offline. - */ - cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", - riscv_online_cpu, riscv_offline_cpu); - out: for_each_cpu(cpu, cpu_online_mask) { if (bufs[cpu]) @@ -383,13 +376,6 @@ static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __alway { schedule_on_each_cpu(check_vector_unaligned_access); - /* - * Setup hotplug callbacks for any new CPUs that come online or go - * offline. - */ - cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", - riscv_online_cpu_vec, NULL); - return 0; } #else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */ @@ -415,6 +401,19 @@ static int __init check_unaligned_access_all_cpus(void) NULL, "vec_check_unaligned_access_speed_all_cpus"); } + /* + * Setup hotplug callbacks for any new CPUs that come online or go + * offline. + */ +#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS + cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", + riscv_online_cpu, riscv_offline_cpu); +#endif +#ifdef CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS + cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", + riscv_online_cpu_vec, NULL); +#endif + return 0; } From patchwork Tue Mar 4 12:00:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 14000624 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A905BC282D0 for ; Tue, 4 Mar 2025 12:10:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=A4SDhEzFReJxYBAatnlb+d6HWOuH1ybaHSxyWdRWTMM=; b=WM2wkiNzxO95zX qRG2QnB9vFCiNnNEmsuNiQNlKsEVdnBHL5hWt1GT5/zSYgNfmsU/9rvyUFfHDF1B1wM/J0vtnTVRb cr6Uelj5U+cK+mtCSgiODIe3zAzstyVfg3on6dprzvpkFo4MIhLFS09OvCJWuq3ufjvRGReNEa9B2 qs7Qm4iASLHY//qbF+xHBqvMIZ1QjJYPCYUrat+EwR+WthrYESBMLUtdSN8L+ZQBswVph9n9zeluc 9HCtDRjfRr4pv/85NPVO+aH2mwRG7PxlEN+GHWJno0BOHtdmN0tNWSi72DoI+3fREeVE+l+SoMJw3 ynX7OXQfrv9UrqSix35A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpR6l-00000004Zkl-22a7; Tue, 04 Mar 2025 12:10:47 +0000 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpQwi-00000004V8p-3qjx for linux-riscv@lists.infradead.org; Tue, 04 Mar 2025 12:00:26 +0000 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4394a0c65fcso59251235e9.1 for ; Tue, 04 Mar 2025 04:00:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1741089623; x=1741694423; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qKhFFnzXyWbQAGhMWM6ZzS3r16qIjR6tEgWbgaYi/y8=; b=WjDW5w0V8Y2Yi1IEcXujdnvYK6tyYLx5HU1Mia7L23lr+udZvsHg3SujrmBUO8jmN4 Nbt6c7aJ2TkWObqp8YEsBOAsUMEn93AXSJXVSsNPmtECPT+dXfEx6QjOipmHbSnCkY7i 646FdyW8EnRWjrzBeyOTYUfKTXD9UMyCpTILuECZ9hnhXNUlXcCdhQWx0KlHly0dJ1c3 v8R/yLvG8baDE/Mc1OUMzpVTcY8dAX7SEqpkfhtUhqEMNpo4Z/IGssDP4/ojI4xJkN13 i1qmP7n7Aw9DNcPGBjm/3TuZq4+ffvdgimhx0lPf/QaiwzQ5ZTbkVIcq4qbojupk/JkJ vy7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741089623; x=1741694423; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qKhFFnzXyWbQAGhMWM6ZzS3r16qIjR6tEgWbgaYi/y8=; b=c7dUVKzPugY4tGLfSBoqx7R9KonZ9EkX6aBubW/GzvckunQhlAQqwRK1TES5QfqqrX s1zMZsESCGAIQ+AExFXFIL7Ol5oHSTWS1wbENE3Ljs/NUeijQ5ZxL8AQYx+JdDzgJgFs xMUeXgXbuGgnkR6Jr4bEy1OquEj2XHD1S8jGxgYVa71GMFQ21A3V441PntyGtcKh4/hE WltfylEue2hFJkg66Gjtj2wchbKhuCxg9ruKY4fBjUxgFpimXXn6K6pQImcn0udiyFfH mmGYRIdzACnC9wS6410UzMssQK/07USARPkvQ4X4jqMYztVhDwyKX1dRltJD4ua/w81I q7fw== X-Gm-Message-State: AOJu0YzaxkfDID2LPa/QPHyoHP6XREgIu0v5nSFfoHSg3P3GfCWeBBjV 2s+NPgQFDz+ET5IayJ0o6dnbZBCGjnJb+wC/T6SVFRaA+wYHsnfrObLf3hPXKez1deHMMo9QybH G X-Gm-Gg: ASbGncuFpg0+kpvNDybxHnMvH22JaQK/v2WtT/y9FwghcqhJ8zV+4sX66RCfIA/0kFE pVuZuXXNqcjewn4BxLgzZ8xI3qzU02YJdUQt71/64NMm7NP3WQBscuf+K7B9jib59oXnNZMVGan GyzZbG5WkmFqKiQ271jIv1yMRDC/mCv/hf4AM0yKcN6n9nPJpvRA3KMgwXcvCAm24SpfArxYJN8 nZ8zSw4u9VKZENwQIIx8h9TkKeQ4Ud+eGsc6NkWRfyvhshgI+jeduf4+X1/ZmzLB48LqqIJeAic r0RXSoI2H/uIJ29Monm2oOQmntoUQnqr X-Google-Smtp-Source: AGHT+IGwC3NsIIWUjYgv3G2JO2vmP8wTEbddF/LPoT4rEkNoTbLO+SirlMYHhSaFI3g4F2HReIh7PQ== X-Received: by 2002:a05:600c:1d8e:b0:439:b565:f457 with SMTP id 5b1f17b1804b1-43ba675c3afmr162133765e9.27.1741089623258; Tue, 04 Mar 2025 04:00:23 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::688c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43aba5871f4sm230729625e9.39.2025.03.04.04.00.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 04:00:22 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, cleger@rivosinc.com, alex@ghiti.fr, Anup Patel , corbet@lwn.net, Alexandre Ghiti Subject: [PATCH v3 6/8] riscv: Fix set up of vector cpu hotplug callback Date: Tue, 4 Mar 2025 13:00:21 +0100 Message-ID: <20250304120014.143628-16-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250304120014.143628-10-ajones@ventanamicro.com> References: <20250304120014.143628-10-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250304_040024_955657_AEB2E294 X-CRM114-Status: GOOD ( 11.78 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Whether or not we have RISCV_PROBE_VECTOR_UNALIGNED_ACCESS we need to set up a cpu hotplug callback to check if we have vector at all, since, when we don't have vector, we need to set vector_misaligned_access to unsupported rather than leave it the default of unknown. Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe") Reviewed-by: Alexandre Ghiti Signed-off-by: Andrew Jones --- arch/riscv/kernel/unaligned_access_speed.c | 31 +++++++++++----------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index c9d3237649bb..d9d4ca1fadc7 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -356,6 +356,20 @@ static void check_vector_unaligned_access(struct work_struct *work __always_unus per_cpu(vector_misaligned_access, cpu) = speed; } +/* Measure unaligned access speed on all CPUs present at boot in parallel. */ +static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) +{ + schedule_on_each_cpu(check_vector_unaligned_access); + + return 0; +} +#else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */ +static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) +{ + return 0; +} +#endif + static int riscv_online_cpu_vec(unsigned int cpu) { if (!has_vector()) { @@ -363,27 +377,16 @@ static int riscv_online_cpu_vec(unsigned int cpu) return 0; } +#ifdef CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS if (per_cpu(vector_misaligned_access, cpu) != RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN) return 0; check_vector_unaligned_access_emulated(NULL); check_vector_unaligned_access(NULL); - return 0; -} - -/* Measure unaligned access speed on all CPUs present at boot in parallel. */ -static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) -{ - schedule_on_each_cpu(check_vector_unaligned_access); +#endif return 0; } -#else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */ -static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) -{ - return 0; -} -#endif static int __init check_unaligned_access_all_cpus(void) { @@ -409,10 +412,8 @@ static int __init check_unaligned_access_all_cpus(void) cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", riscv_online_cpu, riscv_offline_cpu); #endif -#ifdef CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", riscv_online_cpu_vec, NULL); -#endif return 0; } From patchwork Tue Mar 4 12:00:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 14000625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF0D8C021B8 for ; Tue, 4 Mar 2025 12:10:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qeTHQkL5UHRRRsp5bXVZpmWtPelOEQgsqPl/ld58ZrE=; b=wA4QBT5cqcOoXm wMntxBnEO5lScf8sJimGc9edo39dGfL3e4FaoRzz/opzM7n+FhdctbcOpGmvGgx07cU7RMjqfHZ73 1IqFSlL6F40V6bhSomLJGAe3MJU29leBE+tiCUk0LjYg1+2okQclyvGk6Gi21EToJcvICGkWQj5Ou 5msZGFyTie5FljsOWVljJxvKX+DHXS3aogANGoTR4N29Ubg5fV5uNssBwteZUv/w/z7W73ANAJ9b7 M4caiYH3yVKLGxRWnw56bWEvLZt7ZwMfSHQQtEHigVNr/DdmEjVQuSq+uSWxuQjP8/VdAWY8wBEgh Ncp3iOkf+F3MFzWC9AHg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpR6n-00000004ZnH-0XxM; Tue, 04 Mar 2025 12:10:49 +0000 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpQwj-00000004V9O-45Zu for linux-riscv@lists.infradead.org; Tue, 04 Mar 2025 12:00:27 +0000 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-390f69e71c8so2289773f8f.0 for ; Tue, 04 Mar 2025 04:00:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1741089625; x=1741694425; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GsvuidqxLzlkQbg+w8AmHQXcpq7FTNK4bF6tx3heuhc=; b=OyexBKcyRq6FlewGAWy2JffLuPIPIr18Ngaktu0eGfvLAoWkhJ9kEREbq/G/VCInEF PbwwYriKOtIxa78iOG2eXBwHcyL9tQQstzSH1tNS5JUGXL/ZLV0mKGdzJLRntxRAxz0U FWaha+PhPTaXGbrAVe3qtEWPmCzPHZAlXeXba1RpfH59XGdcaW4hBejowI98PP3GVh5A ygimVqQDiJpvIBshFAGApPkeBChZK2AMZx6/jq1MEV9VKhPcmbKI8rOrI5JM7uJcoLfc Aii9a0OoSsv02MrpihdtgsOOsTun+VZym1vJSojINfpOzh+Yels7gTzRr6ii6hddNDa0 fHNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741089625; x=1741694425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GsvuidqxLzlkQbg+w8AmHQXcpq7FTNK4bF6tx3heuhc=; b=hNyn6Iibe/cmAm9K6caFeJyIOJ4RykEtOdkqvjk7Ypm8/xcwzaN/7T//wY+oBPrGVs Z9MJM5/6rA2gIWpmqCpSMOnhN+02JTVW6+JZabhPiOuIzXQ3Vw2hqaiXB9wDfwPWy4JY 8UTD9NFo1LyQMyHB5HO17bS+ZcigLh0tgZwL459/ouBQScVXPoyni+0/MQNjuMCdn73B /vvu6BtJypieeXwo7wlC/sf6p9y9uIdZa8sXR7wd8KgeTdP+omkLOSDiNqu1HCmfL0fj eKWXhLXbpCCUCJuQL2cvLZ+Y4Yo8VfLHC0c77UqR6M7isgQ8k3RNy5+O5xdf0yZte7DA vjgQ== X-Gm-Message-State: AOJu0YxYq0a+k3/fQuSuPodDwhlk/0BFXEcCxOdSC6Suurkd/6esQ1xc emWNdJhG4Y/k89wj9+FUaNefOZBWFUm4E+Ceg06fagXdsQayj23M1dmBJ6YXGNN1HxGJ+k9tyDL B X-Gm-Gg: ASbGncsSX3CAMj03vy0MnDZjxEd74hiW3/SSW6og/UzvT2dLI9xhHPBQwIAGTPeE5kL 7Tmcs3fNMP1OBEEBdCz7FnSpi5dnHSeL7AbYPxheWFEAMfaaPyN7Q9kaie3w28q5oUUr/ykSv4h Wd43KYlOTNqBAwZmv0nBLSpd1YiSTtQggmuX9zsB/mH561dSnZuNS+bI1Yer7RpNueDUmgrMlz9 xL3XQtcryPOBvC0E+nHGS3aHY78VOkqvix44Pi2Yz/GGsFAMuZBa+yIOIkKVeUCUK8Pckso7Ikf Oqzzz8h/vgwwJT0OvkkPWQAlw31uc4Oe X-Google-Smtp-Source: AGHT+IGQ5X8LL0DZ3UPHsnfOapJsPrretEHDDQzUDGpCH+nIE/GuITrQTn3tEhqjhrUytGCLIAwsgA== X-Received: by 2002:a05:6000:144a:b0:391:bc8:564a with SMTP id ffacd0b85a97d-3911561aaeemr2394550f8f.22.1741089624562; Tue, 04 Mar 2025 04:00:24 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::688c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e4844ac6sm17312277f8f.71.2025.03.04.04.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 04:00:24 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, cleger@rivosinc.com, alex@ghiti.fr, Anup Patel , corbet@lwn.net Subject: [PATCH v3 7/8] riscv: Add parameter for skipping access speed tests Date: Tue, 4 Mar 2025 13:00:22 +0100 Message-ID: <20250304120014.143628-17-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250304120014.143628-10-ajones@ventanamicro.com> References: <20250304120014.143628-10-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250304_040026_064620_82689B5F X-CRM114-Status: GOOD ( 20.98 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Allow skipping scalar and vector unaligned access speed tests. This is useful for testing alternative code paths and to skip the tests in environments where they run too slowly. All CPUs must have the same unaligned access speed. The code movement is because we now need the scalar cpu hotplug callback to always run, so we need to bring it and its supporting functions out of CONFIG_RISCV_PROBE_UNALIGNED_ACCESS. Signed-off-by: Andrew Jones --- arch/riscv/kernel/unaligned_access_speed.c | 187 +++++++++++++-------- 1 file changed, 121 insertions(+), 66 deletions(-) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index d9d4ca1fadc7..18e334549544 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -24,8 +24,12 @@ DEFINE_PER_CPU(long, misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN; DEFINE_PER_CPU(long, vector_misaligned_access) = RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED; -#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS +static long unaligned_scalar_speed_param = RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN; +static long unaligned_vector_speed_param = RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN; + static cpumask_t fast_misaligned_access; + +#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS static int check_unaligned_access(void *param) { int cpu = smp_processor_id(); @@ -130,6 +134,50 @@ static void __init check_unaligned_access_nonboot_cpu(void *param) check_unaligned_access(pages[cpu]); } +/* Measure unaligned access speed on all CPUs present at boot in parallel. */ +static void __init check_unaligned_access_speed_all_cpus(void) +{ + unsigned int cpu; + unsigned int cpu_count = num_possible_cpus(); + struct page **bufs = kcalloc(cpu_count, sizeof(*bufs), GFP_KERNEL); + + if (!bufs) { + pr_warn("Allocation failure, not measuring misaligned performance\n"); + return; + } + + /* + * Allocate separate buffers for each CPU so there's no fighting over + * cache lines. + */ + for_each_cpu(cpu, cpu_online_mask) { + bufs[cpu] = alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); + if (!bufs[cpu]) { + pr_warn("Allocation failure, not measuring misaligned performance\n"); + goto out; + } + } + + /* Check everybody except 0, who stays behind to tend jiffies. */ + on_each_cpu(check_unaligned_access_nonboot_cpu, bufs, 1); + + /* Check core 0. */ + smp_call_on_cpu(0, check_unaligned_access, bufs[0], true); + +out: + for_each_cpu(cpu, cpu_online_mask) { + if (bufs[cpu]) + __free_pages(bufs[cpu], MISALIGNED_BUFFER_ORDER); + } + + kfree(bufs); +} +#else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ +static void __init check_unaligned_access_speed_all_cpus(void) +{ +} +#endif + DEFINE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key); static void modify_unaligned_access_branches(cpumask_t *mask, int weight) @@ -188,21 +236,29 @@ arch_initcall_sync(lock_and_set_unaligned_access_static_branch); static int riscv_online_cpu(unsigned int cpu) { - static struct page *buf; - /* We are already set since the last check */ - if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN) + if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN) { + goto exit; + } else if (unaligned_scalar_speed_param != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN) { + per_cpu(misaligned_access_speed, cpu) = unaligned_scalar_speed_param; goto exit; - - check_unaligned_access_emulated(NULL); - buf = alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); - if (!buf) { - pr_warn("Allocation failure, not measuring misaligned performance\n"); - return -ENOMEM; } - check_unaligned_access(buf); - __free_pages(buf, MISALIGNED_BUFFER_ORDER); +#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS + { + static struct page *buf; + + check_unaligned_access_emulated(NULL); + buf = alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); + if (!buf) { + pr_warn("Allocation failure, not measuring misaligned performance\n"); + return -ENOMEM; + } + + check_unaligned_access(buf); + __free_pages(buf, MISALIGNED_BUFFER_ORDER); + } +#endif exit: set_unaligned_access_static_branches(); @@ -217,50 +273,6 @@ static int riscv_offline_cpu(unsigned int cpu) return 0; } -/* Measure unaligned access speed on all CPUs present at boot in parallel. */ -static void __init check_unaligned_access_speed_all_cpus(void) -{ - unsigned int cpu; - unsigned int cpu_count = num_possible_cpus(); - struct page **bufs = kcalloc(cpu_count, sizeof(*bufs), GFP_KERNEL); - - if (!bufs) { - pr_warn("Allocation failure, not measuring misaligned performance\n"); - return; - } - - /* - * Allocate separate buffers for each CPU so there's no fighting over - * cache lines. - */ - for_each_cpu(cpu, cpu_online_mask) { - bufs[cpu] = alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); - if (!bufs[cpu]) { - pr_warn("Allocation failure, not measuring misaligned performance\n"); - goto out; - } - } - - /* Check everybody except 0, who stays behind to tend jiffies. */ - on_each_cpu(check_unaligned_access_nonboot_cpu, bufs, 1); - - /* Check core 0. */ - smp_call_on_cpu(0, check_unaligned_access, bufs[0], true); - -out: - for_each_cpu(cpu, cpu_online_mask) { - if (bufs[cpu]) - __free_pages(bufs[cpu], MISALIGNED_BUFFER_ORDER); - } - - kfree(bufs); -} -#else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ -static void __init check_unaligned_access_speed_all_cpus(void) -{ -} -#endif - #ifdef CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS static void check_vector_unaligned_access(struct work_struct *work __always_unused) { @@ -372,8 +384,8 @@ static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __alway static int riscv_online_cpu_vec(unsigned int cpu) { - if (!has_vector()) { - per_cpu(vector_misaligned_access, cpu) = RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED; + if (unaligned_vector_speed_param != RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN) { + per_cpu(vector_misaligned_access, cpu) = unaligned_vector_speed_param; return 0; } @@ -388,30 +400,73 @@ static int riscv_online_cpu_vec(unsigned int cpu) return 0; } +static const char * const speed_str[] __initconst = { NULL, NULL, "slow", "fast", "unsupported" }; + +static int __init set_unaligned_scalar_speed_param(char *str) +{ + if (!strcmp(str, speed_str[RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW])) + unaligned_scalar_speed_param = RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW; + else if (!strcmp(str, speed_str[RISCV_HWPROBE_MISALIGNED_SCALAR_FAST])) + unaligned_scalar_speed_param = RISCV_HWPROBE_MISALIGNED_SCALAR_FAST; + else if (!strcmp(str, speed_str[RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED])) + unaligned_scalar_speed_param = RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED; + else + return -EINVAL; + + return 1; +} +__setup("unaligned_scalar_speed=", set_unaligned_scalar_speed_param); + +static int __init set_unaligned_vector_speed_param(char *str) +{ + if (!strcmp(str, speed_str[RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW])) + unaligned_vector_speed_param = RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW; + else if (!strcmp(str, speed_str[RISCV_HWPROBE_MISALIGNED_VECTOR_FAST])) + unaligned_vector_speed_param = RISCV_HWPROBE_MISALIGNED_VECTOR_FAST; + else if (!strcmp(str, speed_str[RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED])) + unaligned_vector_speed_param = RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED; + else + return -EINVAL; + + return 1; +} +__setup("unaligned_vector_speed=", set_unaligned_vector_speed_param); + static int __init check_unaligned_access_all_cpus(void) { int cpu; - if (!check_unaligned_access_emulated_all_cpus()) + if (unaligned_scalar_speed_param == RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN && + !check_unaligned_access_emulated_all_cpus()) { check_unaligned_access_speed_all_cpus(); - - if (!has_vector()) { + } else { + pr_info("scalar unaligned access speed set to '%s' by command line\n", + speed_str[unaligned_scalar_speed_param]); for_each_online_cpu(cpu) - per_cpu(vector_misaligned_access, cpu) = RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED; - } else if (!check_vector_unaligned_access_emulated_all_cpus() && - IS_ENABLED(CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS)) { + per_cpu(misaligned_access_speed, cpu) = unaligned_scalar_speed_param; + } + + if (!has_vector()) + unaligned_vector_speed_param = RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED; + + if (unaligned_vector_speed_param == RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN && + !check_vector_unaligned_access_emulated_all_cpus() && + IS_ENABLED(CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS)) { kthread_run(vec_check_unaligned_access_speed_all_cpus, NULL, "vec_check_unaligned_access_speed_all_cpus"); + } else { + pr_info("vector unaligned access speed set to '%s' by command line\n", + speed_str[unaligned_vector_speed_param]); + for_each_online_cpu(cpu) + per_cpu(vector_misaligned_access, cpu) = unaligned_vector_speed_param; } /* * Setup hotplug callbacks for any new CPUs that come online or go * offline. */ -#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", riscv_online_cpu, riscv_offline_cpu); -#endif cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", riscv_online_cpu_vec, NULL); From patchwork Tue Mar 4 12:00:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 14000626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0B02C282D6 for ; Tue, 4 Mar 2025 12:10:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hpVytkROoQ8KLEo5D8s+IvnezSvzbcCbkVQipzKtc1E=; b=DXifLunf29yThE uIhxEz2aNslydUcg+V3Z2ZQaFzLZvg53urDkFuZoTUEtSrFPgMtB2/izf9X9/tpMSpwtXcg+xYr3y oqMZNExZJiPDVWxQASOFykZH4bup1mchVbXPIDp4whsv2ZUdYa00R0UNvQYaSeBCgmWdMi+FVf1mf Ss1nIBKxBReoW7lpMVNtZ9JIYpXsx96nnDwxhpYDMfiCtzBr6XpLGZVzh7NVOTUmGoEvsE1DxnA1f pVEfWH9knWChm0vY5EKNMyBLkepdIMbi69suS9Oj7WJuJ11L1bCw3Kr2kD0JwnbfTXfag1y04l0nH 4gnNaPFLLc1uu7BtM3tA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpR6o-00000004ZpE-2MD2; Tue, 04 Mar 2025 12:10:50 +0000 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpQwl-00000004V9z-0MKy for linux-riscv@lists.infradead.org; Tue, 04 Mar 2025 12:00:28 +0000 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-43690d4605dso35696815e9.0 for ; Tue, 04 Mar 2025 04:00:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1741089626; x=1741694426; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KvHP2BboCGauKM0TvBqQfBu7j1TlN9OaRIMMc+Vl6gA=; b=WptdLqCbjnvTOIRtYxAsKIo8k5oO7NXNRM1VRgEdyHXOwdGn4ZejbWEytuW0zkCNhM uVYha8T5/epgYK2ArwTq3YQ1Zye4WGbv5NocfxtJ5HuT40fJ/n9FsHFl0iNrJBEqHPbP RCMXiozaXpPijsAfOgSWezfWOybgtfXBWyxUFzASz71PSQFlm/be8seAGn8OyP6jI69/ 68nPI7QzB7a50Yu0tpbIWAHXs/UC0+ltbZCWtfNx3GvOxzmON05lQe+LJmQhmJ3dCwnD lZ9E54vJSTolLQ/2aQOFZ/8Cxb5juZ2avsAx27O9NpXoTkDR4iaO7FRrSROSG1ex3uQ+ 8Byw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741089626; x=1741694426; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KvHP2BboCGauKM0TvBqQfBu7j1TlN9OaRIMMc+Vl6gA=; b=ctXyZbDHWDcRPTZH0Pmsw0N3RDBztJ8j649hy3QK9aPJ0erVEeO0/QWvG+3Fa5yN4w nmshrA2ahzkU6pWRoEEihMUrF/qbey8xlsTz0+m5Ruipd7w8cJZVEypCaOQ/lCRBTxdF 9EXbJk++Lm6vhOG07FxhRA10NcQHFNFbRWeYpyBsN00WKHX1FBvKGo5ewze7YN/XYPHt PBwUWUlFj0379A9uHZMoulAJmpw+j1L47azI62WtEe3cBE61UtTVKb2TuI+Gn6uNN3vD N5fPIWXGOvsr0vE8GOnO3YCDtQYkZcSZKWaslYmzdTa1sd5Am6iew9FGw0EGeg8zyg7k Yzuw== X-Gm-Message-State: AOJu0YxoynvsvV7SpdyZZZOyDPUsN8xGacUaSXV/kmMhoRREjQ1PuSW8 pjfXIdBNKYcyC3ZwO+CwfItsM1IP2Q09UEWYLB6D/hkygcV6u/MKsWluLXQ212+9fjRJlQ5IHBm q X-Gm-Gg: ASbGncu9u+2KyV2owhsl+9yc2aO0+hvzNrFx7pnWMPJ73zXFh7dhiYngHNCPCGuci22 u3aiaUdvu2Qv7Qy+9V74vX/r4wrjycZqScyP+bymBGqFt1GaBOVOYTAjCPOucr5jlxqoRK1WiQx iqE5IFedLjkRUEqoZejycv+H5HgrpspQqROGnAVQmODIIsZUZABZnptpOcxUdxINbRHzrHQ+3iR 4dDuN2iEDBgT9DvWvyc3Jm6cUDXpzJSC4Ed5I5vDwC65GtxCiPtN4JDJw2TG5eI4hFhDPcZegHG WoPf9oPrkb+tUFD+XSgVaoMwnpY4DQPD X-Google-Smtp-Source: AGHT+IELzkVFh9RITGThHEwxgYy+2Ld8GAacL3JsxhdPQ1ZeOzGuZugE0nk+z2RxPZrajYXuj5Csrw== X-Received: by 2002:a05:6000:2101:b0:390:f750:40df with SMTP id ffacd0b85a97d-390f750412amr7616475f8f.34.1741089625766; Tue, 04 Mar 2025 04:00:25 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::688c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e4796517sm17247748f8f.5.2025.03.04.04.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 04:00:25 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, cleger@rivosinc.com, alex@ghiti.fr, Anup Patel , corbet@lwn.net Subject: [PATCH v3 8/8] Documentation/kernel-parameters: Add riscv unaligned speed parameters Date: Tue, 4 Mar 2025 13:00:23 +0100 Message-ID: <20250304120014.143628-18-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250304120014.143628-10-ajones@ventanamicro.com> References: <20250304120014.143628-10-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250304_040027_124018_5FB55F67 X-CRM114-Status: UNSURE ( 9.02 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Document riscv parameters used to select scalar and vector unaligned access speeds. Signed-off-by: Andrew Jones --- Documentation/admin-guide/kernel-parameters.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index fb8752b42ec8..9e3c5fecfa52 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -7477,6 +7477,22 @@ Note that genuine overcurrent events won't be reported either. + unaligned_scalar_speed= + [RISCV] + Format: {slow | fast | unsupported} + Allow skipping scalar unaligned access speed tests. This + is useful for testing alternative code paths and to skip + the tests in environments where they run too slowly. All + CPUs must have the same scalar unaligned access speed. + + unaligned_vector_speed= + [RISCV] + Format: {slow | fast | unsupported} + Allow skipping vector unaligned access speed tests. This + is useful for testing alternative code paths and to skip + the tests in environments where they run too slowly. All + CPUs must have the same vector unaligned access speed. + unknown_nmi_panic [X86] Cause panic on unknown NMI.