From patchwork Wed Mar 5 00:21:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 14001685 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7622017548; Wed, 5 Mar 2025 00:21:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741134097; cv=none; b=mXd0ZkthbiwRJGiP7q6wSAwtM+fG6NzCcTDodLj6lr7F8kgg+VZHuQ0dm1wuLqTiSijllGahyoVEqhEjbodUlTDRkP1JG0+eGEWnFv9LJfb0+gSq0oS9bzznhnOVmpvjZYSNQa3/4pMhxiC2SmlGXNDFHgOoO2/K9ev5s5C5E5g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741134097; c=relaxed/simple; bh=fvdCac4sqR/Njza0af2NCC5OdP/Mbpr38b1QkpUuv0s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DLjuJc1blwjiW2l/l8xaJjS7XHP8AZSZtqYMMZQubJi/F2IsL4NoVdIf9euVsKmPuOFJKBRk3WDVcEe6FDBBw7ArVnXpLENTzvRW1D3xAv1yskvknhCejzzh4aAuLN0lioWtd7Qnq10/+WoUWZQrQYAVlh1A7rivnnOjpGEl/co= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: QRjrZrDXSLuPei8IAKHW9g== X-CSE-MsgGUID: 1HANV2RgRFuB5sLgM/3SRw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 05 Mar 2025 09:21:30 +0900 Received: from mulinux.home (unknown [10.226.92.17]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id ECF9A404D874; Wed, 5 Mar 2025 09:21:25 +0900 (JST) From: Fabrizio Castro To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven Cc: Fabrizio Castro , Magnus Damm , Biju Das , Wolfram Sang , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Lad Prabhakar , Conor Dooley Subject: [PATCH v5 1/6] dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H Date: Wed, 5 Mar 2025 00:21:07 +0000 Message-Id: <20250305002112.5289-2-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250305002112.5289-1-fabrizio.castro.jz@renesas.com> References: <20250305002112.5289-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Make sure we don't allow for the clocks, clock-names, resets, reset-names. and power-domains properties for the Renesas RZ/A1H SoC because its DMAC doesn't have clocks, resets, and power domains. Fixes: 209efec19c4c ("dt-bindings: dma: rz-dmac: Document RZ/A1H SoC") Signed-off-by: Fabrizio Castro Acked-by: Conor Dooley Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v4->v5: * Collected tags. v3->v4: * No change. v2->v3: * No change. v1->v2: * No change. --- .../devicetree/bindings/dma/renesas,rz-dmac.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index b356251de5a8..82de3b927479 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -112,6 +112,14 @@ allOf: - resets - reset-names + else: + properties: + clocks: false + clock-names: false + power-domains: false + resets: false + reset-names: false + additionalProperties: false examples: From patchwork Wed Mar 5 00:21:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 14001686 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5258A1F92E; Wed, 5 Mar 2025 00:21:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741134098; cv=none; b=nNUx55eX3KSbmnBUozZ2y1pzL+WOCnx4x8Hpem4ubXPhrK0hQ1raeNSD/6TJslkBHi2ZMKkiWG+AXFEdD/uun+gPWhbJ8CxLCFc4BPHoc1oT+7RscUfWII320DxaNWQ7Y9LN/+SejCF9PwbmdbtVihZl2JiI/9PpSyGuaypEq0A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741134098; c=relaxed/simple; bh=HImcmdxrLsCIHglzEZQXg+KUA1++25unHgW8DqZp6w4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QbNEv6o4Mvl+v9BSwIloHZwaQQvrKWBGVORmxzxnLwfr1xLKOQZzcuRe0tLQOOPtFHzfwVs98CaKCGJNQEyz9ZisPwoCoGKhJCp+WBtAHD4Z8PH/RrEKpEbaSC532unhlNit5qMD0mYu1OHAddE6Cf7aDW0tH48UKrEOZrFk8Qc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: 3paNilXAQRW/T9mlYE9LRA== X-CSE-MsgGUID: hYtxhYYiTPekh5KNIyfFGA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 05 Mar 2025 09:21:34 +0900 Received: from mulinux.home (unknown [10.226.92.17]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id BB244404E420; Wed, 5 Mar 2025 09:21:30 +0900 (JST) From: Fabrizio Castro To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven Cc: Fabrizio Castro , Magnus Damm , Biju Das , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Lad Prabhakar , Conor Dooley Subject: [PATCH v5 2/6] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs Date: Wed, 5 Mar 2025 00:21:08 +0000 Message-Id: <20250305002112.5289-3-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250305002112.5289-1-fabrizio.castro.jz@renesas.com> References: <20250305002112.5289-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document the Renesas RZ/V2H(P) family of SoCs DMAC block. The Renesas RZ/V2H(P) DMAC is very similar to the one found on the Renesas RZ/G2L family of SoCs, but there are some differences: * It only uses one register area * It only uses one clock * It only uses one reset * Instead of using MID/IRD it uses REQ No * It is connected to the Interrupt Control Unit (ICU) Signed-off-by: Fabrizio Castro Acked-by: Conor Dooley Reviewed-by: Lad Prabhakar --- v4->v5: * Removed ACK No from the specification of the dma cell. * I have kept the tags received as this is a minor change and the structure remains the same as v4. Please let me know if this is not okay. v3->v4: * No change. v2->v3: * No change. v1->v2: * Removed RZ/V2H DMAC example. * Improved the readability of the `if` statement. --- .../bindings/dma/renesas,rz-dmac.yaml | 106 +++++++++++++++--- 1 file changed, 88 insertions(+), 18 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index 82de3b927479..8323da12fa26 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -11,19 +11,23 @@ maintainers: properties: compatible: - items: - - enum: - - renesas,r7s72100-dmac # RZ/A1H - - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five - - renesas,r9a07g044-dmac # RZ/G2{L,LC} - - renesas,r9a07g054-dmac # RZ/V2L - - renesas,r9a08g045-dmac # RZ/G3S - - const: renesas,rz-dmac + oneOf: + - items: + - enum: + - renesas,r7s72100-dmac # RZ/A1H + - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five + - renesas,r9a07g044-dmac # RZ/G2{L,LC} + - renesas,r9a07g054-dmac # RZ/V2L + - renesas,r9a08g045-dmac # RZ/G3S + - const: renesas,rz-dmac + + - const: renesas,r9a09g057-dmac # RZ/V2H(P) reg: items: - description: Control and channel register block - description: DMA extended resource selector block + minItems: 1 interrupts: maxItems: 17 @@ -52,6 +56,7 @@ properties: items: - description: DMA main clock - description: DMA register access clock + minItems: 1 clock-names: items: @@ -61,14 +66,21 @@ properties: '#dma-cells': const: 1 description: - The cell specifies the encoded MID/RID values of the DMAC port - connected to the DMA client and the slave channel configuration - parameters. + For the RZ/A1H, RZ/Five, RZ/G2{L,LC,UL}, RZ/V2L, and RZ/G3S SoCs, the cell + specifies the encoded MID/RID values of the DMAC port connected to the + DMA client and the slave channel configuration parameters. bits[0:9] - Specifies MID/RID value bit[10] - Specifies DMA request high enable (HIEN) bit[11] - Specifies DMA request detection type (LVL) bits[12:14] - Specifies DMAACK output mode (AM) bit[15] - Specifies Transfer Mode (TM) + For the RZ/V2H(P) SoC the cell specifies the DMAC REQ No and the slave channel + configuration parameters. + bits[0:9] - Specifies the DMAC REQ No + bit[10] - Specifies DMA request high enable (HIEN) + bit[11] - Specifies DMA request detection type (LVL) + bits[12:14] - Specifies DMAACK output mode (AM) + bit[15] - Specifies Transfer Mode (TM) dma-channels: const: 16 @@ -80,12 +92,29 @@ properties: items: - description: Reset for DMA ARESETN reset terminal - description: Reset for DMA RST_ASYNC reset terminal + minItems: 1 reset-names: items: - const: arst - const: rst_async + renesas,icu: + description: + On the RZ/V2H(P) SoC configures the ICU to which the DMAC is connected to. + It must contain the phandle to the ICU, and the index of the DMAC as seen + from the ICU (e.g. parameter k from register ICU_DMkSELy). + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the ICU node. + - description: The DMAC index. + 4 for DMAC0 + 0 for DMAC1 + 1 for DMAC2 + 2 for DMAC3 + 3 for DMAC4 + required: - compatible - reg @@ -98,13 +127,25 @@ allOf: - $ref: dma-controller.yaml# - if: - not: - properties: - compatible: - contains: - enum: - - renesas,r7s72100-dmac + properties: + compatible: + contains: + enum: + - renesas,r9a07g043-dmac + - renesas,r9a07g044-dmac + - renesas,r9a07g054-dmac + - renesas,r9a08g045-dmac then: + properties: + reg: + minItems: 2 + clocks: + minItems: 2 + resets: + minItems: 2 + + renesas,icu: false + required: - clocks - clock-names @@ -112,13 +153,42 @@ allOf: - resets - reset-names - else: + - if: + properties: + compatible: + contains: + const: renesas,r7s72100-dmac + then: properties: clocks: false clock-names: false power-domains: false resets: false reset-names: false + renesas,icu: false + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-dmac + then: + properties: + reg: + maxItems: 1 + clocks: + maxItems: 1 + resets: + maxItems: 1 + + clock-names: false + reset-names: false + + required: + - clocks + - power-domains + - renesas,icu + - resets additionalProperties: false From patchwork Wed Mar 5 00:21:10 2025 Content-Type: text/plain; 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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: EyVrHvYITLSlBgWGcav/PQ== X-CSE-MsgGUID: pnv5NGh1SECGRKiH+Cc9DQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 05 Mar 2025 09:21:41 +0900 Received: from mulinux.home (unknown [10.226.92.17]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id E7D28404E421; Wed, 5 Mar 2025 09:21:38 +0900 (JST) From: Fabrizio Castro To: Vinod Koul , Geert Uytterhoeven Cc: Fabrizio Castro , Wolfram Sang , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Lad Prabhakar , linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 4/6] dmaengine: sh: rz-dmac: Allow for multiple DMACs Date: Wed, 5 Mar 2025 00:21:10 +0000 Message-Id: <20250305002112.5289-5-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250305002112.5289-1-fabrizio.castro.jz@renesas.com> References: <20250305002112.5289-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 dma_request_channel() calls into __dma_request_channel() with NULL as value for np, which won't allow for the selection of the correct DMAC when multiple DMACs are available. Switch to using __dma_request_channel() directly so that we can choose the desired DMA for the channel. This is in preparation of adding DMAC support for the Renesas RZ/V2H(P) and similar SoCs. Signed-off-by: Fabrizio Castro Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v4->v5: * Collected tags. v3->v4: * No change. v2->v3: * Added () for calls in changelog. v1->v2: * No change. --- drivers/dma/sh/rz-dmac.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 9235db551026..d7a4ce28040b 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -748,7 +748,8 @@ static struct dma_chan *rz_dmac_of_xlate(struct of_phandle_args *dma_spec, dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); - return dma_request_channel(mask, rz_dmac_chan_filter, dma_spec); + return __dma_request_channel(&mask, rz_dmac_chan_filter, dma_spec, + ofdma->of_node); } /* From patchwork Wed Mar 5 00:21:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 14001688 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4B3611E521; Wed, 5 Mar 2025 00:21:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741134116; cv=none; b=hQg/s7/3SA81YsyY4aIbISX6sQO/EMUjmGjHmB2eDsgDvf4tt689OzUu/6HBbkpt/GEwrPvjjQ4CcBL31FMb4Cmu9L8SZz9HhksMChKY6ittwes920umc7D4TJqKZQ5FG6XW5AVjmAdJNCrIHnVuo3NLGolE+mNDktaJpc+2Xyo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741134116; c=relaxed/simple; bh=kgDBEw7j9SvJ8VpIyO+OgTZnD+6Tpqz2ywQCjuQ7k0A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=me7HthxMx/cc/OukbIymbBSB/i1NL7CPpHZ57gLYP2shr+7CVMz0beDBQ/rS2fuNSoqWVUvpK0GYzPsCn2qFHRgMP47pQn20PX1AE76hszFlAJz9GRWwAeCV7GUOqHcyxRl0rFZQkZaY/jg1ngDyKFCMPPWjwcH/eJwX29GqLZw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: 1iaMKynURxCUYpMiGVajpQ== X-CSE-MsgGUID: WkrqKR1NTLmnKxKFieDtFA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 05 Mar 2025 09:21:45 +0900 Received: from mulinux.home (unknown [10.226.92.17]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 6B0F6404D874; Wed, 5 Mar 2025 09:21:42 +0900 (JST) From: Fabrizio Castro To: Vinod Koul , Geert Uytterhoeven Cc: Fabrizio Castro , Magnus Damm , Biju Das , Wolfram Sang , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?q?=C3=B6nig?= , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Lad Prabhakar Subject: [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support Date: Wed, 5 Mar 2025 00:21:11 +0000 Message-Id: <20250305002112.5289-6-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250305002112.5289-1-fabrizio.castro.jz@renesas.com> References: <20250305002112.5289-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The DMAC IP found on the Renesas RZ/V2H(P) family of SoCs is similar to the version found on the Renesas RZ/G2L family of SoCs, but there are some differences: * It only uses one register area * It only uses one clock * It only uses one reset * Instead of using MID/IRD it uses REQ No * It is connected to the Interrupt Control Unit (ICU) * On the RZ/G2L there is only 1 DMAC, on the RZ/V2H(P) there are 5 Add specific support for the Renesas RZ/V2H(P) family of SoC by tackling the aforementioned differences. Signed-off-by: Fabrizio Castro --- v4->v5: * Reused RZ/G2L cell specification (with REQ No in place of MID/RID). * Dropped ACK No. * Removed mid_rid/req_no/ack_no union and reused mid_rid for REQ No. * Other small improvements. v3->v4: * Fixed an issue with mid_rid/req_no/ack_no initialization v2->v3: * Dropped change to Kconfig. * Replaced rz_dmac_type with has_icu flag. * Put req_no and ack_no in an anonymous struct, nested under an anonymous union with mid_rid. * Dropped data field of_rz_dmac_match[], and added logic to determine value of has_icu flag from DT parsing. v1->v2: * Switched to new macros for minimum values. --- drivers/dma/sh/rz-dmac.c | 81 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 74 insertions(+), 7 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index d7a4ce28040b..1f687b08d6b8 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -89,8 +90,14 @@ struct rz_dmac_chan { #define to_rz_dmac_chan(c) container_of(c, struct rz_dmac_chan, vc.chan) +struct rz_dmac_icu { + struct platform_device *pdev; + u8 dmac_index; +}; + struct rz_dmac { struct dma_device engine; + struct rz_dmac_icu icu; struct device *dev; struct reset_control *rstc; void __iomem *base; @@ -99,6 +106,8 @@ struct rz_dmac { unsigned int n_channels; struct rz_dmac_chan *channels; + bool has_icu; + DECLARE_BITMAP(modules, 1024); }; @@ -167,6 +176,9 @@ struct rz_dmac { #define RZ_DMAC_MAX_CHANNELS 16 #define DMAC_NR_LMDESC 64 +/* RZ/V2H ICU related */ +#define RZV2H_MAX_DMAC_INDEX 4 + /* * ----------------------------------------------------------------------------- * Device access @@ -324,7 +336,13 @@ static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel) lmdesc->chext = 0; lmdesc->header = HEADER_LV; - rz_dmac_set_dmars_register(dmac, channel->index, 0); + if (dmac->has_icu) { + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, + channel->index, + RZV2H_ICU_DMAC_REQ_NO_DEFAULT); + } else { + rz_dmac_set_dmars_register(dmac, channel->index, 0); + } channel->chcfg = chcfg; channel->chctrl = CHCTRL_STG | CHCTRL_SETEN; @@ -375,7 +393,13 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel) channel->lmdesc.tail = lmdesc; - rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid); + if (dmac->has_icu) { + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, + channel->index, channel->mid_rid); + } else { + rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid); + } + channel->chctrl = CHCTRL_SETEN; } @@ -647,7 +671,13 @@ static void rz_dmac_device_synchronize(struct dma_chan *chan) if (ret < 0) dev_warn(dmac->dev, "DMA Timeout"); - rz_dmac_set_dmars_register(dmac, channel->index, 0); + if (dmac->has_icu) { + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, + channel->index, + RZV2H_ICU_DMAC_REQ_NO_DEFAULT); + } else { + rz_dmac_set_dmars_register(dmac, channel->index, 0); + } } /* @@ -824,6 +854,38 @@ static int rz_dmac_chan_probe(struct rz_dmac *dmac, return 0; } +static int rz_dmac_parse_of_icu(struct device *dev, struct rz_dmac *dmac) +{ + struct device_node *np = dev->of_node; + struct of_phandle_args args; + uint32_t dmac_index; + int ret; + + ret = of_parse_phandle_with_fixed_args(np, "renesas,icu", 1, 0, &args); + if (ret == -ENOENT) + return 0; + if (ret) + return ret; + + dmac->has_icu = true; + + dmac->icu.pdev = of_find_device_by_node(args.np); + of_node_put(args.np); + if (!dmac->icu.pdev) { + dev_err(dev, "ICU device not found.\n"); + return -ENODEV; + } + + dmac_index = args.args[0]; + if (dmac_index > RZV2H_MAX_DMAC_INDEX) { + dev_err(dev, "DMAC index %u invalid.\n", dmac_index); + return -EINVAL; + } + dmac->icu.dmac_index = dmac_index; + + return 0; +} + static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac) { struct device_node *np = dev->of_node; @@ -840,7 +902,7 @@ static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac) return -EINVAL; } - return 0; + return rz_dmac_parse_of_icu(dev, dmac); } static int rz_dmac_probe(struct platform_device *pdev) @@ -874,9 +936,11 @@ static int rz_dmac_probe(struct platform_device *pdev) if (IS_ERR(dmac->base)) return PTR_ERR(dmac->base); - dmac->ext_base = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(dmac->ext_base)) - return PTR_ERR(dmac->ext_base); + if (!dmac->has_icu) { + dmac->ext_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(dmac->ext_base)) + return PTR_ERR(dmac->ext_base); + } /* Register interrupt handler for error */ irq = platform_get_irq_byname(pdev, irqname); @@ -991,9 +1055,12 @@ static void rz_dmac_remove(struct platform_device *pdev) reset_control_assert(dmac->rstc); pm_runtime_put(&pdev->dev); pm_runtime_disable(&pdev->dev); + + platform_device_put(dmac->icu.pdev); } static const struct of_device_id of_rz_dmac_match[] = { + { .compatible = "renesas,r9a09g057-dmac", }, { .compatible = "renesas,rz-dmac", }, { /* Sentinel */ } };