From patchwork Wed Mar 5 03:05:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Zong-You Xie X-Patchwork-Id: 14001905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11E05C282D3 for ; Wed, 5 Mar 2025 03:06:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=SLILhunEjmjZtudGVwU0PXXFgDV5fuGJzEBfBh25If0=; b=QxEZmUWJziN/kk Ir1ycTs5yfDZN4VVAJ24WYI/8l4gStkZUj0+yb7BcQ31HIkZfZq/hnTaL8VhNKiMdVyCDDFzXB1Ie uzP8u7XCJKxjuhedc7WWZsEkwRzn0ARuQQaehCvgxN//bdQhmlzX3JuedCFZ9w3r9LUDq4lV3B/m0 d/7kCwfCxcfmicONfxTtj3HPCnkl88imC60lTcbdHsixxv0rDMWPdE+BMFql0jRb1sSQDMy4Q/y9k vNrBj/TICUAOZYmaSXE6rdUMvRBdZQ0LMsk1VMzP6Zq25yLliPP2rAhLaVCGB7lRTjPK5beARqkDQ MtgVpOA4YSImIL6KB9Bg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpf54-00000006rHV-0QcU; Wed, 05 Mar 2025 03:05:58 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpf50-00000006rE5-1Tbk for linux-riscv@lists.infradead.org; Wed, 05 Mar 2025 03:05:56 +0000 Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 52535S3d021717 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 5 Mar 2025 11:05:28 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Wed, 5 Mar 2025 11:05:28 +0800 From: Ben Zong-You Xie To: , CC: , , , , Ben Zong-You Xie Subject: [PATCH] riscv: add Andes SoC family Kconfig support Date: Wed, 5 Mar 2025 11:05:26 +0800 Message-ID: <20250305030526.1986062-1-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 52535S3d021717 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250304_190554_702799_37F76508 X-CRM114-Status: UNSURE ( 9.89 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The first SoC in the Andes series is QiLai. It includes a high-performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. For further information, refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/ Signed-off-by: Ben Zong-You Xie --- arch/riscv/Kconfig.errata | 2 +- arch/riscv/Kconfig.socs | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e318119d570d..be76883704a6 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -12,7 +12,7 @@ config ERRATA_ANDES config ERRATA_ANDES_CMO bool "Apply Andes cache management errata" - depends on ERRATA_ANDES && ARCH_R9A07G043 + depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES) select RISCV_DMA_NONCOHERENT default y help diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1916cf7ba450..b89b6e0d1bc9 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,14 @@ menu "SoC selection" +config ARCH_ANDES + bool "Andes SoCs" + depends on MMU && !XIP_KERNEL + select ERRATA_ANDES + select ERRATA_ANDES_CMO + select AX45MP_L2_CACHE + help + This enables support for Andes SoC platform hardware. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP