From patchwork Wed Mar 5 08:20:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jjian Zhou X-Patchwork-Id: 14002123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B2D9C19F32 for ; Wed, 5 Mar 2025 08:23:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=InaeS8/UkU8eLyrlVZZUnJa6Ghra5rWqfYuQwgP38JU=; b=C8i5NWjTGPi8DkHghmH2w5ldCS dZC0vICVTDnSYMAbIZheKceZr3E6OyWOo4sOQHKKv9sxgJB5kooCK95AaVGNfU1v9zBd4/QQvYKMm OUE/nRRka+F7Vc/ApedkGKpW5l+xap1TyIb0F+r02bGUIk3VG9DQESYxY7ifu8QvJRX6rU+lwy68a NpDxzz5QNC81ymLpfliFDpMmk/3XEEHPZpPZqkTuYCtkC3h+pWUlNhLUkWwLtv3ZUiGRAtC/IYj0J O44D8PPPZN/qsKvqHytYNpTn7GfBwi8F5Yw2WIXaKnsSuJXiF7KiWDg+GdF4wNEKm/P0aS8f3CGW3 m6LOvnxg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpk2c-00000007MIp-1Y0x; Wed, 05 Mar 2025 08:23:46 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpjzw-00000007Lxg-3IlX; Wed, 05 Mar 2025 08:21:01 +0000 X-UUID: c2372e48f99a11ef83f2a1c9db70dae0-20250305 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=InaeS8/UkU8eLyrlVZZUnJa6Ghra5rWqfYuQwgP38JU=; b=uqbtiRlha3/mspW7E3V4bmvKL7LxQ8mQlrESBKYu9kwxiKWZ/PKyEbDtbwYSwASCr8RFXvK7KdApGC/eW4vO3Z4nSYWAuAr0dP1v+/mOwjJJB3Y5PGbz9s+GkAeHXHSsSTGmAnvXyzylthRb0I1+qBPoyMsyHID4Q4NgNRNgQVs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:9547ff49-2b2e-40c5-9845-432a036b9ef2,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f,CLOUDID:6c0cb649-a527-43d8-8af6-bc8b32d9f5e9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c2372e48f99a11ef83f2a1c9db70dae0-20250305 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1164494331; Wed, 05 Mar 2025 01:20:55 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 5 Mar 2025 16:20:51 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Wed, 5 Mar 2025 16:20:51 +0800 From: Jjian Zhou To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Jason-ch Chen , Jjian Zhou Subject: [PATCH RFC 1/3] mailbox: mediatek: Add mtk-vcp-mailbox driver Date: Wed, 5 Mar 2025 16:20:38 +0800 Message-ID: <20250305082047.15746-2-jjian.zhou@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250305082047.15746-1-jjian.zhou@mediatek.com> References: <20250305082047.15746-1-jjian.zhou@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250305_002100_836516_880A3AD2 X-CRM114-Status: GOOD ( 25.04 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add mtk-vcp-mailbox driver to support the communication with VCP remote microprocessor. Signed-off-by: Jjian Zhou --- drivers/mailbox/Kconfig | 9 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mtk-vcp-mailbox.c | 179 ++++++++++++++++++++++++ include/linux/mailbox/mtk-vcp-mailbox.h | 34 +++++ 4 files changed, 224 insertions(+) create mode 100644 drivers/mailbox/mtk-vcp-mailbox.c create mode 100644 include/linux/mailbox/mtk-vcp-mailbox.h -- 2.45.2 diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index ed52db272f4d..ffc4a5491462 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -275,6 +275,15 @@ config MTK_CMDQ_MBOX critical time limitation, such as updating display configuration during the vblank. +config MTK_VCP_MBOX + tristate "MediaTek VCP Mailbox Support" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + Say yes here to add support for the MediaTek VCP mailbox driver. + The mailbox implementation provides access from the application + processor to the MediaTek Video Processing Unit. + If unsure say N. + config ZYNQMP_IPI_MBOX tristate "Xilinx ZynqMP IPI Mailbox" depends on ARCH_ZYNQMP && OF diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 9a1542b55539..75a200a9d2d2 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -59,6 +59,8 @@ obj-$(CONFIG_MTK_ADSP_MBOX) += mtk-adsp-mailbox.o obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o +obj-$(CONFIG_MTK_VCP_MBOX) += mtk-vcp-mailbox.o + obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o obj-$(CONFIG_SUN6I_MSGBOX) += sun6i-msgbox.o diff --git a/drivers/mailbox/mtk-vcp-mailbox.c b/drivers/mailbox/mtk-vcp-mailbox.c new file mode 100644 index 000000000000..fd7a123c71c8 --- /dev/null +++ b/drivers/mailbox/mtk-vcp-mailbox.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Corporation. All rights reserved. + * Author: Jjian Zhou + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mtk_vcp_mbox_priv { + void __iomem *base; + struct device *dev; + struct mbox_controller mbox; + const struct mtk_vcp_mbox_cfg *cfg; + struct mtk_ipi_info ipi_recv; +}; + +struct mtk_vcp_mbox_cfg { + u32 set_in; + u32 clr_out; +}; + +static inline struct mtk_vcp_mbox_priv *get_mtk_vcp_mbox_priv(struct mbox_controller *mbox) +{ + return container_of(mbox, struct mtk_vcp_mbox_priv, mbox); +} + +static irqreturn_t mtk_vcp_mbox_irq_thread(int irq, void *data) +{ + struct mbox_chan *chan = data; + struct mtk_vcp_mbox_priv *priv = get_mtk_vcp_mbox_priv(chan->mbox); + + /* get irq status */ + priv->ipi_recv.irq_status = readl(priv->base + priv->cfg->clr_out); + + __ioread32_copy(priv->ipi_recv.msg, priv->base, MAX_SLOT_NUM); + + mbox_chan_received_data(chan, &priv->ipi_recv); + + /* clear irq status */ + writel(priv->ipi_recv.irq_status, priv->base + priv->cfg->clr_out); + + return IRQ_HANDLED; +} + +static struct mbox_chan *mtk_vcp_mbox_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + if (sp->args_count) + return NULL; + + return mbox->chans; +} + +static int mtk_vcp_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct mtk_vcp_mbox_priv *priv = get_mtk_vcp_mbox_priv(chan->mbox); + struct mtk_ipi_info *ipi_info = data; + u32 status; + + if (!ipi_info->msg) { + dev_err(priv->dev, "msg buffer is NULL.\n"); + return -ENOMEM; + } + + status = readl(priv->base + priv->cfg->set_in) & BIT(ipi_info->index); + if (status) { + dev_err(priv->dev, "mailbox IPI %d is busy.\n", ipi_info->id); + return -EBUSY; + } + + if (ipi_info->slot_ofs + ipi_info->len > MBOX_SLOT_MAX_SIZE) + return -EINVAL; + __iowrite32_copy(priv->base + ipi_info->slot_ofs, ipi_info->msg, + ipi_info->len); + + writel(BIT(ipi_info->index), priv->base + priv->cfg->set_in); + + return 0; +} + +static bool mtk_vcp_mbox_last_tx_done(struct mbox_chan *chan) +{ + struct mtk_ipi_info *ipi_info = chan->active_req; + struct mtk_vcp_mbox_priv *priv = get_mtk_vcp_mbox_priv(chan->mbox); + u32 op; + + op = readl(priv->base + priv->cfg->set_in) & BIT(ipi_info->index); + return !op; +} + +static const struct mbox_chan_ops mtk_vcp_mbox_chan_ops = { + .send_data = mtk_vcp_mbox_send_data, + .last_tx_done = mtk_vcp_mbox_last_tx_done, +}; + +static int mtk_vcp_mbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_vcp_mbox_priv *priv; + struct mbox_controller *mbox; + int ret, irq; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + mbox = &priv->mbox; + mbox->dev = dev; + mbox->ops = &mtk_vcp_mbox_chan_ops; + mbox->txdone_irq = false; + mbox->txdone_poll = true; + mbox->of_xlate = mtk_vcp_mbox_xlate; + mbox->num_chans = 1; + mbox->chans = devm_kzalloc(dev, sizeof(*mbox->chans), GFP_KERNEL); + if (!mbox->chans) + return -ENOMEM; + + priv->ipi_recv.msg = devm_kzalloc(dev, sizeof(u8) * MBOX_SLOT_MAX_SIZE, + GFP_KERNEL); + if (!priv->ipi_recv.msg) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->cfg = of_device_get_match_data(dev); + if (!priv->cfg) + return -EINVAL; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_threaded_irq(dev, irq, NULL, + mtk_vcp_mbox_irq_thread, IRQF_ONESHOT, + dev_name(dev), mbox->chans); + if (ret < 0) + return ret; + + platform_set_drvdata(pdev, priv); + + dev_dbg(dev, "MTK VCP mailbox initialized\n"); + + return devm_mbox_controller_register(dev, &priv->mbox); +} + +static const struct mtk_vcp_mbox_cfg mt8196_cfg = { + .set_in = 0x100, + .clr_out = 0x10C, +}; + +static const struct of_device_id mtk_vcp_mbox_of_match[] = { + { .compatible = "mediatek,mt8196-vcp-mbox", .data = &mt8196_cfg }, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_vcp_mbox_of_match); + +static struct platform_driver mtk_vcp_mbox_driver = { + .probe = mtk_vcp_mbox_probe, + .driver = { + .name = "mtk_vcp_mbox", + .of_match_table = mtk_vcp_mbox_of_match, + }, +}; +module_platform_driver(mtk_vcp_mbox_driver); + +MODULE_AUTHOR("Jjian Zhou "); +MODULE_DESCRIPTION("MTK VCP Mailbox Controller"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mailbox/mtk-vcp-mailbox.h b/include/linux/mailbox/mtk-vcp-mailbox.h new file mode 100644 index 000000000000..953499b7cfeb --- /dev/null +++ b/include/linux/mailbox/mtk-vcp-mailbox.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2024 MediaTek Inc. + */ + +#ifndef __MTK_VCP_MAILBOX_H__ +#define __MTK_VCP_MAILBOX_H__ + +#define MBOX_SLOT_MAX_SIZE 0x100 /* mbox max slot size */ +#define MAX_SLOT_NUM 64 + +/** + * struct mtk_ipi_info - channel table that belong to mtk_ipi_device + * @msg: The share buffer between IPC and mailbox driver + * @len: Message length + * @id: IPI number + * @recv_opt: Recv option, 0:receive ,1: response + * @index: The pin groups number of the mailbox channel + * @slot_ofs: Slot offset of the mailbox channel + * @irq_status: Indicate which pin groups triggered the interrupt + * + * It is used between IPC with mailbox driver. + */ +struct mtk_ipi_info { + void *msg; + u32 len; + u32 id; + u32 recv_opt; + u32 index; + u32 slot_ofs; + u32 irq_status; +}; + +#endif From patchwork Wed Mar 5 08:20:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jjian Zhou X-Patchwork-Id: 14002124 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A89BFC19F32 for ; Wed, 5 Mar 2025 08:25:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=eVHnTPYD1NqFriz6eCLRMpMNlPKKVwGPxqrltINJC1o=; b=CaLAMRJEYxTQG8h646XdC5zUwH XA4AY4CTdjx7xjVqMHarsgOW0IDLuJk19qDRg4D7B7gpcrJJZ7vGvVKVUz+OZJKZRQyOOcqRHTmY2 v+Bcyeaq7/8Ba/9tzvNXGWTxYQgux7Ccbk7W+hRA0Piw54MrbDvMtidf5FoL/5TbX+o4/JP6ayMOF yOZ/3Hag7salnK5WJYNVUQKIJEgVaT746O9Zdcq963+Ase05HdOvP/DkxjXqRn2uulmT3ozfowDS1 Pn0gFOUev5KRSIbCk39RF7XnRuXxWvaBPgXhvnSBjrXA8h38i3tCpKEVgUARB2qpBW1oO75se5qpx JPLU1Fsw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpk47-00000007Mdl-2sD9; Wed, 05 Mar 2025 08:25:19 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpjzx-00000007Lxg-41HM; Wed, 05 Mar 2025 08:21:03 +0000 X-UUID: c38d579af99a11ef83f2a1c9db70dae0-20250305 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=eVHnTPYD1NqFriz6eCLRMpMNlPKKVwGPxqrltINJC1o=; b=oIWMtDBIcIaF+9x/nrQj4TW+Mwos23FXKp0aKTvsvfifDj62+TCO/dmF9m9K3alJ0IYNP2DAL+UVFOPpCjq8YipUsGQgr2LteQziqcST4KTWQS9qETqmzJOD76wyanHjYaPrOVqGXtYFTvk9xgbEZDyo2yAPS11/VjmAtZYf0+0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:ed445abf-5304-4077-9192-8df1ee4886a7,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f,CLOUDID:78caf1c5-16da-468a-87f7-8ca8d6b3b9f7,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c38d579af99a11ef83f2a1c9db70dae0-20250305 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1182256586; Wed, 05 Mar 2025 01:20:57 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 5 Mar 2025 16:20:53 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Wed, 5 Mar 2025 16:20:52 +0800 From: Jjian Zhou To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Jason-ch Chen , Jjian Zhou Subject: [PATCH RFC 2/3] firmware: mediatek: Add VCP IPC protocol interface Date: Wed, 5 Mar 2025 16:20:39 +0800 Message-ID: <20250305082047.15746-3-jjian.zhou@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250305082047.15746-1-jjian.zhou@mediatek.com> References: <20250305082047.15746-1-jjian.zhou@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250305_002102_033129_0E1B8875 X-CRM114-Status: GOOD ( 28.08 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Some of mediatek processors contain the Risc-V coprocessor. The communication between Host CPU and vcp firmware is taking place using a shared memory area for message passing. VCP IPC protocol offers (send/recv) interfaces using mediatek-mailbox APIs. Signed-off-by: Jjian Zhou --- drivers/firmware/Kconfig | 9 + drivers/firmware/Makefile | 1 + drivers/firmware/mtk-vcp-ipc.c | 481 ++++++++++++++++++ include/linux/firmware/mediatek/mtk-vcp-ipc.h | 151 ++++++ 4 files changed, 642 insertions(+) create mode 100644 drivers/firmware/mtk-vcp-ipc.c create mode 100644 include/linux/firmware/mediatek/mtk-vcp-ipc.h diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 37e43f287e78..98c4ff667836 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -179,6 +179,15 @@ config MTK_ADSP_IPC ADSP exists on some mtk processors. Client might use shared memory to exchange information with ADSP. +config MTK_VCP_IPC + tristate "MTK VCP IPC Protocol driver" + depends on MTK_VCP_MBOX + help + Say yes here to add support for the MediaTek VCP IPC + between host AP (Linux) and the firmware running on VCP. + VCP exists on some mtk processors. + Client might use shared memory to exchange information with VCP. + config SYSFB bool select BOOT_VESA_SUPPORT diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 91efcc868a05..2b9894e5169a 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o obj-$(CONFIG_MTK_ADSP_IPC) += mtk-adsp-ipc.o +obj-$(CONFIG_MTK_VCP_IPC) += mtk-vcp-ipc.o obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o obj-$(CONFIG_FW_CFG_SYSFS) += qemu_fw_cfg.o obj-$(CONFIG_SYSFB) += sysfb.o diff --git a/drivers/firmware/mtk-vcp-ipc.c b/drivers/firmware/mtk-vcp-ipc.c new file mode 100644 index 000000000000..744937c56b67 --- /dev/null +++ b/drivers/firmware/mtk-vcp-ipc.c @@ -0,0 +1,481 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2024 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * struct mtk_ipi_chan_table - channel table that belong to mtk_ipi_device + * @mbox: the mbox channel number + * @mbox_pin_cb: callback function + * @holder: keep 1 if there are ipi waiters (to wait the reply) + * @ipi_record: timestamp of each ipi transmission stage + * @pin_buf: buffer point + * @prdata: private data + * @recv_opt: recv option, 0:receive ,1: response + * @notify: completion notify process + * @send_ofs: message offset in the slots of a mbox + * @send_index: bit offset in the mbox + * @msg_zie: slot size of the ipi message + * + * All of these data should be initialized by mtk_ipi_device_register() + */ +struct mtk_ipi_chan_table { + u32 mbox; + mbox_pin_cb_t mbox_pin_cb; + atomic_t holder; + void *pin_buf; + void *prdata; + u32 recv_opt; + struct completion notify; + /* define a mutex for remote response */ + struct mutex mutex_send; + u32 send_ofs; + u32 send_index; + u32 msg_size; +}; + +/** + * mbox information + * + * @mbdev: mbox device + * @mbox_id: mbox id + * @slot: how many slots that mbox used + * @opt: option for tx mode, 0:mbox, 1:share memory 2:queue + * @base: mbox base address + * @mbox_client: mbox client + * @mbox_chan: mbox channel + */ +struct mtk_mbox_info { + struct mtk_vcp_ipc *vcp_ipc; + u32 mbox_id; + u32 slot; + u32 opt; + /* lock of mbox */ + spinlock_t mbox_lock; + struct mbox_client cl; + struct mbox_chan *ch; + struct mtk_ipi_info ipi_info; +}; + +static const char * const mbox_names[VCP_MBOX_NUM] = { + "mbox0", "mbox1", "mbox2", "mbox3", "mbox4" +}; + +/** + * mtk_vcp_ipc_recv - recv callback used by MTK VCP mailbox + * + * @c: mbox client + * @msg: message received + * + * Users of VCP IPC will need to provide handle_reply and handle_request + * callbacks. + */ +static void mtk_vcp_ipc_recv(struct mbox_client *c, void *msg) +{ + struct mtk_mbox_info *minfo = container_of(c, struct mtk_mbox_info, cl); + struct mtk_vcp_ipc *vcp_ipc = minfo->vcp_ipc; + struct mtk_ipi_info *ipi_info = msg; + struct mtk_ipi_device *ipidev = vcp_ipc->ipi_priv; + struct mtk_ipi_chan_table *table; + struct mtk_mbox_recv_table *mbox_recv; + u32 id; + + /* execute all receive pin handler */ + for (id = 0; id < vcp_ipc->mbdev->recv_count; id++) { + mbox_recv = &vcp_ipc->mbdev->recv_table[id]; + if (mbox_recv->mbox_id != minfo->mbox_id) + continue; + + if (!(BIT(mbox_recv->pin_index) & ipi_info->irq_status)) + continue; + + table = &ipidev->table[mbox_recv->ipi_id]; + if (!table->pin_buf) { + dev_err(vcp_ipc->dev, "IPI%d buf is null.\n", + mbox_recv->ipi_id); + continue; + } + + memcpy(table->pin_buf, + ipi_info->msg + mbox_recv->offset * MBOX_SLOT_SIZE, + mbox_recv->msg_size * MBOX_SLOT_SIZE); + + if (!mbox_recv->recv_opt && table->mbox_pin_cb) + table->mbox_pin_cb(mbox_recv->ipi_id, + table->prdata, + table->pin_buf, + mbox_recv->msg_size * MBOX_SLOT_SIZE); + + /* notify task */ + if (table->recv_opt == MBOX_RECV_MESSAGE || + atomic_read(&table->holder)) + complete(&table->notify); + } +} + +/* + * mtk_vcp_ipc_send - send ipc command to MTK VCP + * + * @ipidev: VCP struct mtk_ipi_device handle + * @id: id of the feature IPI + * @data: message address + * @len: message length + * + * Return: Zero for success from mbox_send_message + * negative value for error + */ +int mtk_vcp_ipc_send(struct mtk_ipi_device *ipidev, u32 id, void *data, u32 len) +{ + struct device *dev; + struct mtk_mbox_info *minfo; + struct mtk_ipi_chan_table *table; + struct mtk_vcp_ipc *vcp_ipc; + int ret; + + if (!ipidev || !ipidev->ipi_inited || !data) + return IPI_UNAVAILABLE; + vcp_ipc = ipidev->vcp_ipc; + if (!vcp_ipc) + return IPI_UNAVAILABLE; + + table = ipidev->table; + dev = ipidev->vcp_ipc->dev; + minfo = &ipidev->vcp_ipc->info_table[table[id].mbox]; + if (!minfo) { + dev_err(dev, "%s IPI%d minfo is invalid.\n", ipidev->name, id); + return IPI_UNAVAILABLE; + } + + if (len > table[id].msg_size) + return IPI_MSG_TOO_BIG; + else if (!len) + len = table[id].msg_size; + + mutex_lock(&table[id].mutex_send); + + minfo->ipi_info.msg = data; + minfo->ipi_info.len = len; + minfo->ipi_info.id = id; + minfo->ipi_info.index = table[id].send_index; + minfo->ipi_info.slot_ofs = table[id].send_ofs * MBOX_SLOT_SIZE; + + ret = mbox_send_message(minfo->ch, &minfo->ipi_info); + mutex_unlock(&table[id].mutex_send); + if (ret < 0) { + dev_err(dev, "%s IPI%d send failed.\n", ipidev->name, id); + return IPI_MBOX_ERR; + } + + return IPI_ACTION_DONE; +} +EXPORT_SYMBOL(mtk_vcp_ipc_send); + +/* + * mtk_vcp_ipc_send_compl - send ipc command to MTK VCP + * + * @ipidev: VCP struct mtk_ipi_device handle + * @id: id of the feature IPI + * @data: message address + * @len: message length + * @timeout_ms: + * + * Return: Zero for success from mbox_send_message + * negative value for error + */ +int mtk_vcp_ipc_send_compl(struct mtk_ipi_device *ipidev, u32 id, + void *data, u32 len, u32 timeout_ms) +{ + struct device *dev; + struct mtk_mbox_info *minfo; + struct mtk_ipi_chan_table *table; + struct mtk_vcp_ipc *vcp_ipc; + int ret; + + if (!ipidev || !ipidev->ipi_inited || !data) + return IPI_UNAVAILABLE; + vcp_ipc = ipidev->vcp_ipc; + if (!vcp_ipc) + return IPI_UNAVAILABLE; + + table = ipidev->table; + dev = ipidev->vcp_ipc->dev; + minfo = &ipidev->vcp_ipc->info_table[table[id].mbox]; + if (!minfo) { + dev_err(dev, "%s IPI%d minfo is invalid.\n", ipidev->name, id); + return IPI_UNAVAILABLE; + } + + if (len > table[id].msg_size) + return IPI_MSG_TOO_BIG; + else if (!len) + len = table[id].msg_size; + + mutex_lock(&table[id].mutex_send); + + minfo->ipi_info.msg = data; + minfo->ipi_info.len = len; + minfo->ipi_info.id = id; + minfo->ipi_info.index = table[id].send_index; + minfo->ipi_info.slot_ofs = table[id].send_ofs * MBOX_SLOT_SIZE; + + atomic_inc(&table[id].holder); + + ret = mbox_send_message(minfo->ch, &minfo->ipi_info); + if (ret < 0) { + atomic_set(&table[id].holder, 0); + mutex_unlock(&table[id].mutex_send); + dev_err(dev, "%s IPI%d send failed.\n", ipidev->name, id); + return IPI_MBOX_ERR; + } + + /* wait for completion */ + ret = wait_for_completion_timeout(&table[id].notify, + msecs_to_jiffies(timeout_ms)); + atomic_set(&table[id].holder, 0); + if (ret > 0) + ret = IPI_ACTION_DONE; + + mutex_unlock(&table[id].mutex_send); + + return ret; +} +EXPORT_SYMBOL(mtk_vcp_ipc_send_compl); + +int mtk_vcp_mbox_ipc_register(struct mtk_ipi_device *ipidev, int id, + mbox_pin_cb_t cb, void *prdata, void *msg) +{ + if (!ipidev || !ipidev->ipi_inited) + return IPI_DEV_ILLEGAL; + if (!msg) + return IPI_NO_MSGBUF; + + if (ipidev->table[id].pin_buf) + return IPI_ALREADY_USED; + ipidev->table[id].mbox_pin_cb = cb; + ipidev->table[id].pin_buf = msg; + ipidev->table[id].prdata = prdata; + + return IPI_ACTION_DONE; +} +EXPORT_SYMBOL(mtk_vcp_mbox_ipc_register); + +int mtk_vcp_mbox_ipc_unregister(struct mtk_ipi_device *ipidev, int id) +{ + if (!ipidev || !ipidev->ipi_inited) + return IPI_DEV_ILLEGAL; + + /* Drop the ipi and reset the record */ + complete(&ipidev->table[id].notify); + + ipidev->table[id].mbox_pin_cb = NULL; + ipidev->table[id].pin_buf = NULL; + ipidev->table[id].prdata = NULL; + + return IPI_ACTION_DONE; +} +EXPORT_SYMBOL(mtk_vcp_mbox_ipc_unregister); + +static void mtk_fill_in_entry(struct mtk_ipi_chan_table *entry, const u32 ipi_id, + const struct mtk_mbox_table *mbdev) +{ + const struct mtk_mbox_send_table *mbox_send = mbdev->send_table; + u32 index; + + for (index = 0; index < mbdev->send_count; index++) { + if (ipi_id != mbox_send[index].ipi_id) + continue; + + entry->send_ofs = mbox_send[index].offset; + entry->send_index = mbox_send[index].pin_index; + entry->msg_size = mbox_send[index].msg_size; + entry->mbox = mbox_send[index].mbox_id; + return; + } + + entry->mbox = -ENOENT; +} + +int mtk_vcp_ipc_device_register(struct mtk_ipi_device *ipidev, + u32 ipi_chan_count, struct mtk_vcp_ipc *vcp_ipc) +{ + struct mtk_ipi_chan_table *ipi_chan_table; + struct mtk_mbox_table *mbdev; + u32 index; + + if (!vcp_ipc || !ipidev) + return -EINVAL; + + ipi_chan_table = kcalloc(ipi_chan_count, + sizeof(struct mtk_ipi_chan_table), GFP_KERNEL); + if (!ipi_chan_table) + return -ENOMEM; + + mbdev = vcp_ipc->mbdev; + vcp_ipc->ipi_priv = (void *)ipidev; + ipidev->table = ipi_chan_table; + ipidev->vcp_ipc = vcp_ipc; + + for (index = 0; index < ipi_chan_count; index++) { + atomic_set(&ipi_chan_table[index].holder, 0); + mutex_init(&ipi_chan_table[index].mutex_send); + init_completion(&ipi_chan_table[index].notify); + mtk_fill_in_entry(&ipi_chan_table[index], index, mbdev); + } + + ipidev->ipi_inited = 1; + + dev_dbg(vcp_ipc->dev, "%s (with %d IPI) has registered.\n", + ipidev->name, ipi_chan_count); + + return IPI_ACTION_DONE; +} +EXPORT_SYMBOL(mtk_vcp_ipc_device_register); + +static int setup_mbox_table(struct mtk_mbox_table *mbdev, u32 mbox) +{ + struct mtk_mbox_send_table *mbox_send = &mbdev->send_table[0]; + struct mtk_mbox_recv_table *mbox_recv = &mbdev->recv_table[0]; + u32 i, last_ofs = 0, last_idx = 0, last_slot = 0, last_sz = 0; + + for (i = 0; i < mbdev->send_count; i++) { + if (mbox == mbox_send[i].mbox_id) { + mbox_send[i].offset = last_ofs + last_slot; + mbox_send[i].pin_index = last_idx + last_sz; + last_idx = mbox_send[i].pin_index; + last_sz = DIV_ROUND_UP(mbox_send[i].msg_size, MBOX_SLOT_ALIGN); + last_ofs = last_sz * MBOX_SLOT_ALIGN; + last_slot = last_idx * MBOX_SLOT_ALIGN; + } else if (mbox < mbox_send[i].mbox_id) { + /* no need to search the rest id */ + break; + } + } + + for (i = 0; i < mbdev->recv_count; i++) { + if (mbox == mbox_recv[i].mbox_id) { + mbox_recv[i].offset = last_ofs + last_slot; + mbox_recv[i].pin_index = last_idx + last_sz; + last_idx = mbox_recv[i].pin_index; + last_sz = DIV_ROUND_UP(mbox_recv[i].msg_size, MBOX_SLOT_ALIGN); + last_ofs = last_sz * MBOX_SLOT_ALIGN; + last_slot = last_idx * MBOX_SLOT_ALIGN; + } else if (mbox < mbox_recv[i].mbox_id) { + /* no need to search the rest id */ + break; + } + } + + if (last_idx > MBOX_MAX_PIN || (last_ofs + last_slot) > MAX_SLOT_NUM) + return -EINVAL; + + return 0; +} + +static int mtk_vcp_ipc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_vcp_ipc *vcp_ipc; + struct mbox_client *cl; + struct mtk_mbox_info *minfo; + int ret; + u32 mbox, i; + struct mtk_mbox_table *mbox_data = dev_get_platdata(dev); + + device_set_of_node_from_dev(&pdev->dev, pdev->dev.parent); + + vcp_ipc = devm_kzalloc(dev, sizeof(*vcp_ipc), GFP_KERNEL); + if (!vcp_ipc) + return -ENOMEM; + + if (!mbox_data) { + dev_err(dev, "No platform data available\n"); + return -EINVAL; + } + vcp_ipc->mbdev = mbox_data; + + /* alloc and init mmup_mbox_info */ + vcp_ipc->info_table = vzalloc(sizeof(*vcp_ipc->info_table) * VCP_MBOX_NUM); + if (!vcp_ipc->info_table) + return -ENOMEM; + + /* create mbox dev */ + for (mbox = 0; mbox < VCP_MBOX_NUM; mbox++) { + minfo = &vcp_ipc->info_table[mbox]; + minfo->mbox_id = mbox; + minfo->vcp_ipc = vcp_ipc; + spin_lock_init(&minfo->mbox_lock); + + ret = setup_mbox_table(vcp_ipc->mbdev, mbox); + if (ret) + return ret; + + cl = &minfo->cl; + cl->dev = &pdev->dev; + cl->tx_block = false; + cl->knows_txdone = false; + cl->tx_prepare = NULL; + cl->rx_callback = mtk_vcp_ipc_recv; + minfo->ch = mbox_request_channel_byname(cl, mbox_names[mbox]); + if (IS_ERR(minfo->ch)) { + ret = PTR_ERR(minfo->ch); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to request mbox channel %s ret %d\n", + mbox_names[mbox], ret); + + for (i = 0; i < mbox; i++) { + minfo = &vcp_ipc->info_table[i]; + mbox_free_channel(minfo->ch); + } + + vfree(vcp_ipc->info_table); + return ret; + } + } + + vcp_ipc->dev = dev; + dev_set_drvdata(dev, vcp_ipc); + dev_dbg(dev, "MTK VCP IPC initialized\n"); + + return 0; +} + +static void mtk_vcp_ipc_remove(struct platform_device *pdev) +{ + struct mtk_vcp_ipc *vcp_ipc = dev_get_drvdata(&pdev->dev); + struct mtk_mbox_info *minfo; + int i; + + for (i = 0; i < VCP_MBOX_NUM; i++) { + minfo = &vcp_ipc->info_table[i]; + mbox_free_channel(minfo->ch); + } + + vfree(vcp_ipc->info_table); +} + +static struct platform_driver mtk_vcp_ipc_driver = { + .probe = mtk_vcp_ipc_probe, + .remove = mtk_vcp_ipc_remove, + .driver = { + .name = "mtk-vcp-ipc", + }, +}; +builtin_platform_driver(mtk_vcp_ipc_driver); + +MODULE_AUTHOR("Jjian Zhou "); +MODULE_DESCRIPTION("MediaTek VCP IPC Controller"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/firmware/mediatek/mtk-vcp-ipc.h b/include/linux/firmware/mediatek/mtk-vcp-ipc.h new file mode 100644 index 000000000000..dc34b0ba9dd8 --- /dev/null +++ b/include/linux/firmware/mediatek/mtk-vcp-ipc.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2024 MediaTek Inc. + */ + +#ifndef __MTK_VCP_IPC_H__ +#define __MTK_VCP_IPC_H__ + +#include +#include +#include +#include +#include +#include + +/* IPI result definition */ +#define IPI_ACTION_DONE 0 +#define IPI_DEV_ILLEGAL -1 /* ipi device is not initialized */ +#define IPI_ALREADY_USED -2 /* the ipi has be registered */ +#define IPI_UNAVAILABLE -3 /* the ipi can't be found */ +#define IPI_NO_MSGBUF -4 /* receiver doesn't have message buffer */ +#define IPI_MSG_TOO_BIG -5 /* message length is larger than defined */ +#define IPI_MBOX_ERR -99 /* some error from rpmsg layer */ + +/* mbox recv action definition */ +enum mtk_ipi_recv_opt { + MBOX_RECV_MESSAGE = 0, + MBOX_RECV_ACK = 1, +}; + +/* mbox table item number definition */ +#define send_item_num 3 +#define recv_item_num 4 +#define VCP_MBOX_NUM 5 + +/* mbox slot size definition: 1 slot for 4 bytes */ +#define MBOX_SLOT_SIZE 0x4 +#define MBOX_MAX_PIN 32 +#define VCP_MBOX_NUM 5 +#define MBOX_SLOT_ALIGN 2 + +struct mtk_vcp_ipc; +struct mtk_ipi_chan_table; + +typedef int (*mbox_pin_cb_t)(u32 ipi_id, void *prdata, void *data, u32 len); + +/** + * mbox pin structure, this is for send definition, + * @offset: message offset in the slots of a mbox + * @msg_size: message used slots in the mbox, 4 bytes alignment + * @pin_index: bit offset in the mbox + * @ipi_id: ipi enum number + * @mbox_id: mbox number id + */ +struct mtk_mbox_send_table { + u32 offset; + u32 msg_size; + u32 pin_index; + u32 ipi_id; + u32 mbox_id; +}; + +/** + * mbox pin structure, this is for receive definition, + * @offset: message offset in the slots of a mbox + * @recv_opt: recv option, 0:receive ,1: response + * @msg_size: message used slots in the mbox, 4 bytes alignment + * @pin_index: bit offset in the mbox + * @ipi_id: ipi enum number + * @mbox_id: mbox number id + */ +struct mtk_mbox_recv_table { + u32 offset; + u32 recv_opt; + u32 msg_size; + u32 pin_index; + u32 ipi_id; + u32 mbox_id; +}; + +/** + * struct mtk_ipi_device - device for represent the tinysys using mtk ipi + * @name: name of tinysys device + * @id: device id (used to match between rpmsg drivers and devices) + * @vcp_ipc: vcp ipc structure for tinysys device + * @table: channel table with endpoint & channel_info & mbox_pin info + * @prdata: private data for the callback use + * @ipi_inited: set when vcp_ipi_device_register() done + */ +struct mtk_ipi_device { + const char *name; + struct mtk_vcp_ipc *vcp_ipc; + struct mtk_ipi_chan_table *table; + void *prdata; + int ipi_inited; +}; + +/** + * The mtk_mbox_table is a structure used to record the send + * table and recv table. The send table is used to record + * the feature ID and size of the sent data. The recv table + * is used to record the feature ID and size of the received + * data, and whether a callback needs to be invoked. + * + * Following are platform specific interfacer + * @recv_table: structure mtk_mbox_recv_table + * @send_table: structure mtk_mbox_send_table + * @recv_count: receive feature number in this channel + * @send_count: send feature number in this channel + */ +struct mtk_mbox_table { + struct mtk_mbox_recv_table recv_table[32]; + struct mtk_mbox_send_table send_table[32]; + u32 recv_count; + u32 send_count; +}; + +/** + * Mbox is a dedicate hardware of a tinysys consists of: + * 1) a share memory tightly coupled to the tinysys + * 2) several IRQs + * + * Following are platform specific interface + * @dev: vcp device + * @name: identity of the device + * @info_table: mbox info structure + * @ipi_priv: private data for synchronization layer + * @mbox_id: mbox number + * @mbdev: mtk_mbox_table structure + */ +struct mtk_vcp_ipc { + struct device *dev; + const char *name; + struct mtk_mbox_info *info_table; + void *ipi_priv; + void *mbox_id; + struct mtk_mbox_table *mbdev; +}; + +int mtk_vcp_ipc_device_register(struct mtk_ipi_device *ipidev, + u32 ipi_chan_count, + struct mtk_vcp_ipc *vcp_ipc); +int mtk_vcp_ipc_send(struct mtk_ipi_device *ipidev, u32 ipi_id, + void *data, u32 len); +int mtk_vcp_ipc_send_compl(struct mtk_ipi_device *ipidev, u32 ipi_id, + void *data, u32 len, u32 timeout_ms); +int mtk_vcp_mbox_ipc_register(struct mtk_ipi_device *ipidev, int ipi_id, + mbox_pin_cb_t cb, void *prdata, void *msg); +int mtk_vcp_mbox_ipc_unregister(struct mtk_ipi_device *ipidev, int ipi_id); + +#endif From patchwork Wed Mar 5 08:20:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jjian Zhou X-Patchwork-Id: 14002127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AEEC6C282D3 for ; Wed, 5 Mar 2025 08:26:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=KfxPaWGsAZSYsN3AQgx//cOpK/kMmXrN13zjrXyUlh4=; b=M976eY/EQvcNropxP+Gp+Mz5qy 4yAtWZsz/ryBxc7pqp8AHtNg1Zk0c8vIZwTuhTOWh52Ksc0DSPGhxfJNEGQBgJ2MU2T4kXX23Tdsp 0aNmdKOjdwI++Ksn1ZYyClHEK/s4Japd68cb8OdfrGQao4hF5cMO3nrNcI4gBYAXI43olPO8V9o+x rB5tPTZ/vcwH768Y7GHQIxpdd46T1+isFv7pxP2oCPKMOMh6UkpfMiNUUF/UAV7wo9or42snzv1wC ADykzzoZBP1ghbeyytk51xFxAhB57hRqWqNqlsiWfcc2+4pMNL+g/Zdx61wX+mpRB6p5gDMuD/qfS GxiF6FHA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpk5f-00000007MuW-3By4; Wed, 05 Mar 2025 08:26:55 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpjzx-00000007LyI-49rn; Wed, 05 Mar 2025 08:21:03 +0000 X-UUID: c47a74eef99a11efa1e849db4cc18d44-20250305 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=KfxPaWGsAZSYsN3AQgx//cOpK/kMmXrN13zjrXyUlh4=; b=j6rN1eS+LLPIzBggOPVr9kpH1GMFR6hiDKzaoFWF85jwq6DaJuPikJCMTaZgDxkVwyTUshqB0Hx/bIiCkpDIXlnJLpSv4pMi3e52EA1G+FrVMJST8kSPV82XTO/buIPrURrUhxKqi85XsVw+U+OAp68i0M8GbywiXq5aYKD459g=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:0cc4ad91-32fc-4ffd-8d4f-9382d6248249,IP:0,UR L:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:25 X-CID-META: VersionHash:0ef645f,CLOUDID:8f610bce-23b9-4c94-add0-e827a7999e28,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 ,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: c47a74eef99a11efa1e849db4cc18d44-20250305 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1120176636; Wed, 05 Mar 2025 01:20:58 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 5 Mar 2025 16:20:55 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Wed, 5 Mar 2025 16:20:55 +0800 From: Jjian Zhou To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Jason-ch Chen , Jjian Zhou Subject: [PATCH RFC 3/3] dt-bindings: mailbox: mtk,vcp-mbox: add mtk vcp-mbox document Date: Wed, 5 Mar 2025 16:20:40 +0800 Message-ID: <20250305082047.15746-4-jjian.zhou@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250305082047.15746-1-jjian.zhou@mediatek.com> References: <20250305082047.15746-1-jjian.zhou@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250305_002102_049538_68D47368 X-CRM114-Status: GOOD ( 13.72 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org This patch adds document for mediatek vcp mbox. Signed-off-by: Jjian Zhou --- .../bindings/mailbox/mtk,vcp-mbox.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/mtk,vcp-mbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/mtk,vcp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mtk,vcp-mbox.yaml new file mode 100644 index 000000000000..d5afe295af14 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mtk,vcp-mbox.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mtk,vcp-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Video Companion Processor (VCP) mailbox + +maintainers: + - Jjian Zhou + +description: | + The MTK VCP mailbox enables the SoC to communicate with the VCP by passing + messages through 64 32-bit wide registers. It has 32 interrupt vectors in + either direction for signalling purposes. + +properties: + compatible: + enum: + - mediatek,mt8196-vcp-mbox + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + vcp_mailbox0: mailbox@31b80000 { + compatible = "mediatek,mt8196-vcp-mbox"; + reg = <0x31b80000 0x1000>; + interrupts = ; + #mbox-cells = <0>; + };