From patchwork Thu Mar 6 13:10:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004472 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70F96C282D1 for ; Thu, 6 Mar 2025 13:23:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0452B10E974; Thu, 6 Mar 2025 13:23:08 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FWFHPVV2"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id F354D10E974; Thu, 6 Mar 2025 13:23:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267386; x=1772803386; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=buu1amdupeffLg71up5fXbkAKjtcttX81xfBF6pNmKQ=; b=FWFHPVV23O7TFd5JhfZSrl25mxyrLsb4BD95c+BkqfDgRQPUfK+/Zgz4 TzcZXtcex56K6veg3G9FMldDKNXIsTZWlV8XogQI/22P548bhyUWk0/xw 1LWOjRsKPgBx7MStHufazjVIfwYWZuVFo8KCVJ9DyTV0l+hzr++EAsa4I IrOtAhcwXH+wWBFHn0cXIPOj7/oynPfH1WITON6Vhbgdfoqk96Yy/b4hh hGqpH6m82ynLP2NswsSQ8lYjuONuQvEgPVpiSz8RYREKDgWmC0A7wne2R 3J7EMoC5cvmLhFgBX2qm/MQTyY8W4bF3vt5997alzFKgnfK0F7bsNSIhL Q==; X-CSE-ConnectionGUID: 3pzqbt4GQRCndICLe4DHAg== X-CSE-MsgGUID: cyhrUNqPTbGLcjwBaaJaMQ== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524599" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524599" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:05 -0800 X-CSE-ConnectionGUID: /IEl4HsuQ3aUhlhQRoVYzg== X-CSE-MsgGUID: jSOMKU2zRxuGw2Vn8Yma7Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243102" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:03 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 01/21] drm/i915/vrr: Remove unwanted comment Date: Thu, 6 Mar 2025 18:40:40 +0530 Message-ID: <20250306131100.3989503-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The comment about fixed average vtotal is incorrect. Remove it. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index cac49319026d..106bfaf6649b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -276,11 +276,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, */ crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display); - /* - * When panel is VRR capable and userspace has - * not enabled adaptive sync mode then Fixed Average - * Vtotal mode should be enabled. - */ if (crtc_state->uapi.vrr_enabled) { crtc_state->vrr.enable = true; crtc_state->mode_flags |= I915_MODE_FLAG_VRR; From patchwork Thu Mar 6 13:10:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004473 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0446C28B23 for ; Thu, 6 Mar 2025 13:23:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2840810E98A; Thu, 6 Mar 2025 13:23:09 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="P8ofPuT5"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id C0DA610E972; Thu, 6 Mar 2025 13:23:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267388; x=1772803388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=juqJ0qvFmDilx/F20PaSB7Cd1TJX/eYkO/z+meC5J0I=; b=P8ofPuT55YRlDel43xTn3cJvc/V5CWBEfHr0sxxCjHYLyHGcc0yAx5QU 2U3+QqB3Y/zpvBccOoXaJh+GbK9KbQTRlq03uBu49BP7kwCJd93tU4LII KiHFOJZbrTykp8jiNT9fPDBuiQWp3q0NMdj6ll6WHFNcyhPBfs6uMDMec TYei2bzdsiKvOg0yYOwubzgclg8NbhOj92pmr4JNw0QwpUgSwvupV2tkt orfWKK0tCKIKPFlF4upFmGoFswVM4uy0acPKRz5Hd9CbmBYekcUb4P6h7 wGBbJ1J6qLm/m9fBuepprVmfsEVFruHFkQkZd+hxaDCLA4dNMfqeznuaS w==; X-CSE-ConnectionGUID: 13XpU0lpSjaK8Wj1pUDeeQ== X-CSE-MsgGUID: YWE/jgdSR/uScz0NiI1zpg== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524602" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524602" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:08 -0800 X-CSE-ConnectionGUID: egw4//YNQUqsM6prLwKjSA== X-CSE-MsgGUID: Z3ShnFRkQMOnSnzh+xtFEw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243107" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:05 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 02/21] drm/i915:vrr: Separate out functions to compute vmin and vmax Date: Thu, 6 Mar 2025 18:40:41 +0530 Message-ID: <20250306131100.3989503-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make helpers to compute vmin and vmax. v2: Make the adjusted mode const (Ville) Use reverse xmas tree order of declarations. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 38 +++++++++++++++++++----- 1 file changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 106bfaf6649b..a88b77114867 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -222,6 +222,34 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required) return vtotal; } +static +int intel_vrr_compute_vmin(struct intel_connector *connector, + const struct drm_display_mode *adjusted_mode) +{ + const struct drm_display_info *info = &connector->base.display_info; + int vmin; + + vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, + adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq); + vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal); + + return vmin; +} + +static +int intel_vrr_compute_vmax(struct intel_connector *connector, + const struct drm_display_mode *adjusted_mode) +{ + const struct drm_display_info *info = &connector->base.display_info; + int vmax; + + vmax = adjusted_mode->crtc_clock * 1000 / + (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq); + vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal); + + return vmax; +} + void intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -232,7 +260,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct intel_dp *intel_dp = intel_attached_dp(connector); bool is_edp = intel_dp_is_edp(intel_dp); struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - const struct drm_display_info *info = &connector->base.display_info; int vmin, vmax; /* @@ -253,13 +280,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, if (HAS_LRR(display)) crtc_state->update_lrr = true; - vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, - adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq); - vmax = adjusted_mode->crtc_clock * 1000 / - (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq); - - vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal); - vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal); + vmin = intel_vrr_compute_vmin(connector, adjusted_mode); + vmax = intel_vrr_compute_vmax(connector, adjusted_mode); if (vmin >= vmax) return; From patchwork Thu Mar 6 13:10:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E20BC282D1 for ; Thu, 6 Mar 2025 13:23:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D38910E97C; Thu, 6 Mar 2025 13:23:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="41524608" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524608" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:10 -0800 X-CSE-ConnectionGUID: lx2nIppyROuUp8B32rIHXA== X-CSE-MsgGUID: KkooPFkESzaNuIcwMSvNhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243111" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:08 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 03/21] drm/i915/vrr: Make helpers for cmrr and vrr timings Date: Thu, 6 Mar 2025 18:40:42 +0530 Message-ID: <20250306131100.3989503-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Separate out functions for computing cmrr and vrr timings. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 45 +++++++++++++++--------- 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index a88b77114867..db0ea206e26e 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -222,6 +222,30 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required) return vtotal; } +static +void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state) +{ + crtc_state->vrr.enable = true; + crtc_state->cmrr.enable = true; + /* + * TODO: Compute precise target refresh rate to determine + * if video_mode_required should be true. Currently set to + * false due to uncertainty about the precise target + * refresh Rate. + */ + crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false); + crtc_state->vrr.vmin = crtc_state->vrr.vmax; + crtc_state->vrr.flipline = crtc_state->vrr.vmin; + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; +} + +static +void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state) +{ + crtc_state->vrr.enable = true; + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; +} + static int intel_vrr_compute_vmin(struct intel_connector *connector, const struct drm_display_mode *adjusted_mode) @@ -298,23 +322,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, */ crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display); - if (crtc_state->uapi.vrr_enabled) { - crtc_state->vrr.enable = true; - crtc_state->mode_flags |= I915_MODE_FLAG_VRR; - } else if (is_cmrr_frac_required(crtc_state) && is_edp) { - crtc_state->vrr.enable = true; - crtc_state->cmrr.enable = true; - /* - * TODO: Compute precise target refresh rate to determine - * if video_mode_required should be true. Currently set to - * false due to uncertainty about the precise target - * refresh Rate. - */ - crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false); - crtc_state->vrr.vmin = crtc_state->vrr.vmax; - crtc_state->vrr.flipline = crtc_state->vrr.vmin; - crtc_state->mode_flags |= I915_MODE_FLAG_VRR; - } + if (crtc_state->uapi.vrr_enabled) + intel_vrr_compute_vrr_timings(crtc_state); + else if (is_cmrr_frac_required(crtc_state) && is_edp) + intel_vrr_compute_cmrr_timings(crtc_state); if (HAS_AS_SDP(display)) { crtc_state->vrr.vsync_start = From patchwork Thu Mar 6 13:10:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE95BC282D1 for ; Thu, 6 Mar 2025 13:23:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 61DD410E972; Thu, 6 Mar 2025 13:23:13 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="X+tuYYjT"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1F45B10E972; Thu, 6 Mar 2025 13:23:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267392; x=1772803392; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=73c77X2jtrQLzajo0bb/IL2SbaXrtR99nV38+tucoMI=; b=X+tuYYjTnRhfx7jQMH+PO/Ot8MNPrgW09Ail0nNbh159UKeLL9PsKYdw uU6io7J7eGhJB/RU7StOBKhvXDId9VWX5ZB7YDFNE0ma9KB3KaRSoQ4FQ hAETLRHoDB7L+FtSsisnUT9M3VQEmKIOzqkNCJ6Ae/lLxZjOBmd1HIJ+B H9lcWIwwWTnEdgK8c/AGfRBP+qhGwD0BhtSAOPSMVsS9i/OltO9kDhcqP ndDwzKhBbgYDwLD2x75R2voJpeFf0Oea6cf2Pj5GyPVwVb0ESfyPj5wyG jyPuum6V+IMt0+AgMlHTe8A7gFHXSITa/esWPtVwo2m7+aaY1UHJvj6WW A==; X-CSE-ConnectionGUID: AKmsyKIwRkCbGrtTtJgXfg== X-CSE-MsgGUID: i+D6+Fq8QQ+nrcZMk0lWwg== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524614" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524614" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:12 -0800 X-CSE-ConnectionGUID: OsuN7sBtQNSsAAouoWhHzQ== X-CSE-MsgGUID: RpujWMP2T8OHCX17utdSEQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243114" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:10 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 04/21] drm/i915/vrr: Disable CMRR Date: Thu, 6 Mar 2025 18:40:43 +0530 Message-ID: <20250306131100.3989503-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Switching between variable and fixed timings is possible as for that we just need to flip between VRR timings. However for CMRR along with the timings, few other bits also need to be changed on the fly, which might cause issues. So disable CMRR for now, till we have variable and fixed timings sorted out. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index db0ea206e26e..a57659820f4b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -182,7 +182,8 @@ is_cmrr_frac_required(struct intel_crtc_state *crtc_state) int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line; struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - if (!HAS_CMRR(display)) + /* Avoid CMRR for now till we have VRR with fixed timings working */ + if (!HAS_CMRR(display) || true) return false; actual_refresh_k = From patchwork Thu Mar 6 13:10:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0380DC28B26 for ; Thu, 6 Mar 2025 13:23:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E59E10E978; Thu, 6 Mar 2025 13:23:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="gGSH+iTd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4303710E979; Thu, 6 Mar 2025 13:23:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267394; x=1772803394; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=25AyOOFW8lx/wcVTPeUldmGb7poUa6eMHthPvWuq5aY=; b=gGSH+iTd/Gy1lDJLbcLPnF+DP4w6NaK4UJYThpjmX2mjRllJX6lR0Y/E fyhn98Tn9l7F74rPxlGWSQBCrqEBe23j6dbzDjFTgIGE+7N1QlWP/5iVB j8LWq/JJDX54scUTcBd8TBwZ+BUAxNxswKrhDdvSwILN6l5BW158kIfLL 53vqlvR4A/YZORLL+qpiHgOGtO/vnFrA54QlFPWyvEKNP5ZHSKmcBlOXQ VZ0soHya4N6/Hjn0a/PoIxJh8tRaBhizmlQqmaOPZAogyz5Fln0r0ccqm +H7+i56tj1BKiHdWLuVMX1yvyl9K/PwLZDlDmPJP7jaZRD3tHMAd1hMVs Q==; X-CSE-ConnectionGUID: ckFlEdBuRoWVWWdYoenoJg== X-CSE-MsgGUID: /yQzibGhTDqjR4sg+58ouw== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524616" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524616" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:14 -0800 X-CSE-ConnectionGUID: K7BZqJlUSSqaP4Xag1RTmA== X-CSE-MsgGUID: Kag6OOmqQ4efS+cLpba+0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243118" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:12 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 05/21] drm/i915/vrr: Track vrr.enable only for variable timing Date: Thu, 6 Mar 2025 18:40:44 +0530 Message-ID: <20250306131100.3989503-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Since CMRR is now disabled, use the flag vrr.enable to tracks if vrr timing generator is used with variable timings. Avoid setting vrr.enable for CMRR and adjust readout to not set vrr.enable when vmax == vmin == flipline (fixed refresh rate timing). v2: Use intel_vrr_vmin_flipline() to account for adjustments required for icl/tgl. (Ville) v3: Add a #TODO for handling I915_MODE_FLAG_VRR better for CMRR. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index a57659820f4b..7320eb97991f 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -226,7 +226,6 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required) static void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state) { - crtc_state->vrr.enable = true; crtc_state->cmrr.enable = true; /* * TODO: Compute precise target refresh rate to determine @@ -527,6 +526,14 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); } +static +bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->vrr.flipline && + crtc_state->vrr.flipline == crtc_state->vrr.vmax && + crtc_state->vrr.flipline == intel_vrr_vmin_flipline(crtc_state); +} + void intel_vrr_get_config(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -536,7 +543,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) trans_vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); - crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; if (HAS_CMRR(display)) crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); @@ -576,6 +582,14 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) } } + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE && + !intel_vrr_is_fixed_rr(crtc_state); + + /* + * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags. + * Since CMRR is currently disabled, set this flag for VRR for now. + * Need to keep this in mind while re-enabling CMRR. + */ if (crtc_state->vrr.enable) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } From patchwork Thu Mar 6 13:10:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC07AC282D1 for ; Thu, 6 Mar 2025 13:23:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 46F3610E97E; Thu, 6 Mar 2025 13:23:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cYm0oq6X"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6CE1C10E97E; Thu, 6 Mar 2025 13:23:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267396; x=1772803396; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=twWhrfRdE/T3G4gmXvszKBn+QmKwSaG2Wqh/nLwfsbE=; b=cYm0oq6XoKYXZTLg3swRNe8rrBNB4ML6phdaoR6mOmrDuGmq7Z8F6HVs P7t4nfxlRDRwIPIILw+dhBLXinZIC19cMwoFrd28F9nAeKTjgrEo0cEJ/ DhNmvChl133J7yl/tFgWbo861nmHtubsMqttvSZ8cxeBjEyREZxJscMA/ /0aocZcgw0rNbuJajiSdg+z3SMGVDlXlc0DVA2L0et69r84+Uzvvpci4Z Cw8lOcDxy5ckXgmATVInLFvq/ntVivR9bgr6b9mF4rrZIj9i5YsD6XmOf Dg9QpadUHPNXHLG5bekHv1xrHXaW344VdI3RprGFlN7iYpS8U7NFtFLcz Q==; X-CSE-ConnectionGUID: Gi/oszv4RACekOVgkEGS5A== X-CSE-MsgGUID: nYSpgR/9Rx2c869cIwOpxA== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524628" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524628" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:16 -0800 X-CSE-ConnectionGUID: DwfRFPxlRTmxPPaya2QWtw== X-CSE-MsgGUID: ia/QKP+jT4awPV1M1B6QkQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243123" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:14 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 06/21] drm/i915/vrr: Use crtc_vtotal for vmin Date: Thu, 6 Mar 2025 18:40:45 +0530 Message-ID: <20250306131100.3989503-7-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To have fixed refresh rate with VRR timing generator the guardband/pipeline full can't be programmed on the fly. So we need to ensure that the values satisfy both the fixed and variable refresh rates. Since we compute these value based on vmin, lets set the vmin to crtc_vtotal for both fixed and variable timings instead of using the current refresh rate based approach. This way the guardband remains sufficient for both cases. v2: Avoid using vblank delay while computing vtotal, as this comes into the picture later. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 7320eb97991f..e0573e28014b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -247,17 +247,16 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state) } static -int intel_vrr_compute_vmin(struct intel_connector *connector, - const struct drm_display_mode *adjusted_mode) +int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state) { - const struct drm_display_info *info = &connector->base.display_info; - int vmin; - - vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, - adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq); - vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal); - - return vmin; + /* + * To make fixed rr and vrr work seamless the guardband/pipeline full + * should be set such that it satisfies both the fixed and variable + * timings. + * For this set the vmin as crtc_vtotal. With this we never need to + * change anything to do with the guardband. + */ + return crtc_state->hw.adjusted_mode.crtc_vtotal; } static @@ -304,7 +303,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, if (HAS_LRR(display)) crtc_state->update_lrr = true; - vmin = intel_vrr_compute_vmin(connector, adjusted_mode); + vmin = intel_vrr_compute_vmin(crtc_state); vmax = intel_vrr_compute_vmax(connector, adjusted_mode); if (vmin >= vmax) From patchwork Thu Mar 6 13:10:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004478 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A02DEC28B25 for ; Thu, 6 Mar 2025 13:23:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3955E10E97F; Thu, 6 Mar 2025 13:23:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nCD1N1eJ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9A46910E97F; Thu, 6 Mar 2025 13:23:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267399; x=1772803399; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=x1wLjvXb1MarPI0GiaBIc2T4/JKfJO+Te9F1cFWo0BA=; b=nCD1N1eJGpxkRzUHQMah9aYB6HXxC3ywsb590PSRcizOI4PMsesHZRwJ Kek7NBBISNZjNxYIWCUxlbfIU73iH4taUoBH4AksbnGOX4H1wlV41XpfU nSCcuK5UhMiIYWN0FplrJSz32N1zgRkvp57U/htvkmE1DnTMJDAB6SpiE IPCrX919gA+DHvD0st68xtHCz++UGPVf6KbPTK/4b4/hqdFjdFu/jv+NU jt7vSrOm0Lnh0vl+pW/J/hI/GCrj6P4WcEM7XjBoL4dbkfkF8sZ9aTzsL Me+NQHskH/sfBHvJ2bl3Ufyde5PacDs+7WfZINaWxbu0dl8Bq+jBvahGy A==; X-CSE-ConnectionGUID: U8Qj9XG3RO2uZAlfc7PnDg== X-CSE-MsgGUID: d9EiwwmfQui/AgrxakrVcQ== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524634" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524634" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:18 -0800 X-CSE-ConnectionGUID: n7vQth2jSze3lkKJzfY/NA== X-CSE-MsgGUID: KsjJ+W/JS/2/Zuo74UffhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243127" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:16 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 07/21] drm/i915/vrr: Prepare for fixed refresh rate timings Date: Thu, 6 Mar 2025 18:40:46 +0530 Message-ID: <20250306131100.3989503-8-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we always compute the timings as if vrr is enabled. With this approach the state checker becomes complicated when we introduce fixed refresh rate mode with vrr timing generator. To avoid the complications, instead of always computing vrr timings, we compute vrr timings based on uapi.vrr_enable knob. So when the knob is disabled we always compute vmin=flipline=vmax. v2: Use actual timings without any adjustments while preparing for fixed timings in compute_config. (Ville) v3: Avoid setting fixed timings if !vrr_possible(). v4: Move vmin adjustement after all other timings are complete. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä (#v2) --- drivers/gpu/drm/i915/display/intel_vrr.c | 87 ++++++++++++++++++++++-- 1 file changed, 82 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index e0573e28014b..622a70e21737 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -246,6 +246,72 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } +/* + * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to + * Vtotal value. + */ +static +int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal; + + if (DISPLAY_VER(display) >= 13) + return crtc_vtotal; + else + return crtc_vtotal - + intel_vrr_real_vblank_delay(crtc_state); +} + +static +int intel_vrr_fixed_rr_vmax(const struct intel_crtc_state *crtc_state) +{ + return intel_vrr_fixed_rr_vtotal(crtc_state); +} + +static +int intel_vrr_fixed_rr_vmin(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + + return intel_vrr_fixed_rr_vtotal(crtc_state) - + intel_vrr_flipline_offset(display); +} + +static +int intel_vrr_fixed_rr_flipline(const struct intel_crtc_state *crtc_state) +{ + return intel_vrr_fixed_rr_vtotal(crtc_state); +} + +static +void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (!intel_vrr_possible(crtc_state)) + return; + + intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), + intel_vrr_fixed_rr_vmin(crtc_state) - 1); + intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), + intel_vrr_fixed_rr_vmax(crtc_state) - 1); + intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), + intel_vrr_fixed_rr_flipline(crtc_state) - 1); +} + +static +void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state) +{ + /* + * For fixed rr, vmin = vmax = flipline. + * vmin is already set to crtc_vtotal set vmax and flipline the same. + */ + crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal; + crtc_state->vrr.flipline = crtc_state->hw.adjusted_mode.crtc_vtotal; +} + static int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state) { @@ -314,6 +380,13 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->vrr.flipline = crtc_state->vrr.vmin; + if (crtc_state->uapi.vrr_enabled) + intel_vrr_compute_vrr_timings(crtc_state); + else if (is_cmrr_frac_required(crtc_state) && is_edp) + intel_vrr_compute_cmrr_timings(crtc_state); + else + intel_vrr_compute_fixed_rr_timings(crtc_state); + /* * flipline determines the min vblank length the hardware will * generate, and on ICL/TGL flipline>=vmin+1, hence we reduce @@ -321,11 +394,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, */ crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display); - if (crtc_state->uapi.vrr_enabled) - intel_vrr_compute_vrr_timings(crtc_state); - else if (is_cmrr_frac_required(crtc_state) && is_edp) - intel_vrr_compute_cmrr_timings(crtc_state); - if (HAS_AS_SDP(display)) { crtc_state->vrr.vsync_start = (crtc_state->hw.adjusted_mode.crtc_vtotal - @@ -496,6 +564,13 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) if (!crtc_state->vrr.enable) return; + intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), + crtc_state->vrr.vmin - 1); + intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), + crtc_state->vrr.vmax - 1); + intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), + crtc_state->vrr.flipline - 1); + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN); @@ -523,6 +598,8 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) TRANS_VRR_STATUS(display, cpu_transcoder), VRR_STATUS_VRR_EN_LIVE, 1000); intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); + + intel_vrr_set_fixed_rr_timings(old_crtc_state); } static From patchwork Thu Mar 6 13:10:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004479 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C6C0C28B26 for ; Thu, 6 Mar 2025 13:23:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D921E10E980; Thu, 6 Mar 2025 13:23:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fkS4djEn"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id B9A9910E984; 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06 Mar 2025 05:23:20 -0800 X-CSE-ConnectionGUID: bZzNYkhBSQ+t7vKdCFjbdQ== X-CSE-MsgGUID: l2L0zUpHSb+sJIyObfTrPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243130" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:18 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 08/21] drm/i915/display: Enable MSA Ignore Timing PAR only when in not fixed_rr mode Date: Thu, 6 Mar 2025 18:40:47 +0530 Message-ID: <20250306131100.3989503-9-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" MSA Ignore Timing PAR enable is set in the DP sink when we enable variable refresh rate. Currently for link training we depend on flipline to decide whether we want to ignore the msa timings. With fixed refresh rate we will still fill the flipline in all cases whether panel supports VRR or not. Change the condition for link training to ignore the msa timings if vrr.in_range. v2: Add more documentation and a #TODO for readout of vrr.in_range. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 2966f5b39392..ea225496a96e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -711,8 +711,21 @@ void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, b static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { + /* + * Currently, we set the MSA ignore bit based on vrr.in_range. + * We can't really read that out during driver load since we don't have + * the connector information read in yet. So if we do end up doing a + * modeset during initial_commit() we'll clear the MSA ignore bit. + * GOP likely wouldn't have set this bit so after the initial commit, + * if there are no modesets and we enable VRR mode seamlessly + * (without a full modeset), the MSA ignore bit might never get set. + * + * #TODO: Implement readout of vrr.in_range. + * We need fastset support for setting the MSA ignore bit in DPCD, + * especially on the first real commit when clearing the inherited flag. + */ intel_dp_link_training_set_mode(intel_dp, - crtc_state->port_clock, crtc_state->vrr.flipline); + crtc_state->port_clock, crtc_state->vrr.in_range); } void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, From patchwork Thu Mar 6 13:10:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004480 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D1EDC28B27 for ; Thu, 6 Mar 2025 13:23:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 23EBE10E975; Thu, 6 Mar 2025 13:23:24 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SOvSNguN"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id E702C10E986; Thu, 6 Mar 2025 13:23:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267403; x=1772803403; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wTrBq0rmVsGk9LwWbSeVbEPwVwTPlUS/aQDJWPq0ILA=; b=SOvSNguNRjrBpJEgK78SZRhDHkDvz8uu8rvNqw2qQ0g9KX3+huk2F+3V fcCSIZNMIJo5Sd9Lt+JmeFJewxSLKC7IiDUtQwfItL3soA341br9uL4xE ZfRInCGfhc1VBg+92US2GBMxWG9tYRHkFrYkR6YVHgzCFQWPlIHZwIIbl NNZlSvLiQQ/MCoGpVJbaIcQ1Sr3JQxNAjw3FbKiBb60D4piIg/Pdle/hs ADR6KrfuweMlhl2MFFytDFludXPf1XKQHc4pZuxVT9IZ51g/omgHNaT3Z ukFyVCww74Tqp2lqlClRulTpERxDGksLn3bM4D33EwTRZevF6c70y6W/y A==; X-CSE-ConnectionGUID: 84pKoeauRg6dNIsprqVd0g== X-CSE-MsgGUID: Kva9WJHjQWORmzvfgPBaJA== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524654" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524654" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:23 -0800 X-CSE-ConnectionGUID: lhlPQ8ZxTaS1JyfFCWADAA== X-CSE-MsgGUID: saNLS2DhSCSWNmTC2xwReA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243137" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:21 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 09/21] drm/i915/hdmi: Use VRR Timing generator for HDMI for fixed_rr Date: Thu, 6 Mar 2025 18:40:48 +0530 Message-ID: <20250306131100.3989503-10-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently VRR is not supported with HDMI, but we can still leverage the VRR Timing Generator to achieve a fixed refresh rate. Call intel_vrr_compute_config() for HDMI which will handle the vrr timings to have fixed refresh rate with VRR Timing Generator. v2: Improve commit message. (Ville). Signed-off-by: Ankit Nautiyal Reviewed-by: Mitul Golani (#v1) --- drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 33b8d5229db0..f9fa17e1f584 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -64,6 +64,7 @@ #include "intel_panel.h" #include "intel_pfit.h" #include "intel_snps_phy.h" +#include "intel_vrr.h" static void assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) @@ -2384,6 +2385,8 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, } } + intel_vrr_compute_config(pipe_config, conn_state); + intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); From patchwork Thu Mar 6 13:10:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02D30C282D1 for ; Thu, 6 Mar 2025 13:23:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8233B10E986; Thu, 6 Mar 2025 13:23:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nUTxgGpO"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1B79910E986; Thu, 6 Mar 2025 13:23:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267405; x=1772803405; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tmvCnc9s58wM8BwoeBBwcUB3y48arWkHN/04vZDKAEQ=; b=nUTxgGpOe3lqZuWTjXj6+dhdMmWDeC+a7Vo74fGjP1uUYVSz1hWa+EIz SOP6LAiVwfYQo6KjpgwM/ycqyY+ICuojNHLQFbqVLp38JW0T/Y/n14Zs7 mkwwkPte2EkjXWzcWrDyEixxFccC7v8CVrF0WuQj+M4gsOlqyyFGNuth+ LYEE+CtRZ/lrZ1g5K6AuDqk7fbAIZ43rTvcaPB5QfB65x+QPPFwnltBwc 1QLTZTZzstmBXQOexE9RjEeQKQZ/X0GLZTHBNfJuOL09/Ksrvmd4+ADIO b7zwOdJnQjwZSGqNTLQf+adfNbw+aIgji+Pa3yJd/Dq8udsTU3qClu+yF A==; X-CSE-ConnectionGUID: YbvQRISkRdmA8zjNWsr3Rg== X-CSE-MsgGUID: 0HfhKNm+SYacR+GJe1lF5Q== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524658" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524658" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:25 -0800 X-CSE-ConnectionGUID: phmFoZSeQ3Wz08SlLOMu4w== X-CSE-MsgGUID: 79KSVf8zQ56w8vNh3VhNww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243146" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:23 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 10/21] drm/i915/dp_mst: Use VRR Timing generator for DP MST for fixed_rr Date: Thu, 6 Mar 2025 18:40:49 +0530 Message-ID: <20250306131100.3989503-11-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently the variable timings are supported only for DP and eDP and not for DP MST. Call intel_vrr_compute_config() for MST which will configure fixed refresh rate timings irrespective of whether VRR is supported or not. Since vrr_capable still doesn't have support for DP MST this will be just treated as non VRR case and vrr.vmin/vmax/flipline will be all set to adjusted_mode->crtc_vtotal. This will help to move away from the legacy timing generator and always use VRR timing generator by default. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 02f95108c637..bd47cf127b4c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -52,6 +52,7 @@ #include "intel_pfit.h" #include "intel_psr.h" #include "intel_vdsc.h" +#include "intel_vrr.h" #include "skl_scaler.h" /* @@ -710,6 +711,8 @@ static int mst_stream_compute_config(struct intel_encoder *encoder, pipe_config->lane_lat_optim_mask = bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); + intel_vrr_compute_config(pipe_config, conn_state); + intel_dp_audio_compute_config(encoder, pipe_config, conn_state); intel_ddi_compute_min_voltage_level(pipe_config); From patchwork Thu Mar 6 13:10:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004482 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59693C28B25 for ; Thu, 6 Mar 2025 13:23:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DC86A10E98C; Thu, 6 Mar 2025 13:23:27 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Beg1UY3I"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4692010E988; Thu, 6 Mar 2025 13:23:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267407; x=1772803407; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TpaEVX86w0S7RmBFIyWzNrWBNn8o+AxcxgN0Dtq7Bpg=; b=Beg1UY3IYP437ZsFxCd3swszF6TpYyq4SQWfBSqGDcct5NCv5acj8nDT npb8KwIxzAhGna0OchWlWcXid5g0YDCIMHKMdGoOps+mINpDbyA8f4xNm u99tAEq+wucugS6YpU0IfuHkZsxwYE5+N+KXCLcG2wmJxboPGkHA5DgBB op42USe1RfWCBd2gVxCf0QZ5nF6/wYYvKTSPuDNZaMYpci3qU6MyFv7h0 hgrPLZFJNKU8Yb9N19MXDpMUQPWHejYlRJnBOdkfBPt1Ehyl/oC+xDYmC M1Jj0o0WHtcukJqOY40Sj8vnK6PwipOZk/6EkAQYJnYcGaNc07gYVlkRh Q==; X-CSE-ConnectionGUID: r8oz1U5dSOin5bKpm6fHKQ== X-CSE-MsgGUID: qO94nMVEQHuLiFIEjEc/sg== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524667" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524667" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:27 -0800 X-CSE-ConnectionGUID: 2l7OHV4RS0qCN43ANTbhqw== X-CSE-MsgGUID: 3palNo8lSpCnIBiuoFoPvw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243151" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:25 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 11/21] drm/i915/display: Disable PSR before disabling VRR Date: Thu, 6 Mar 2025 18:40:50 +0530 Message-ID: <20250306131100.3989503-12-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" As per bspec 49268: Disable PSR before disabling VRR. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f7cb38145e9d..e72c6024f33e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1175,6 +1175,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; + intel_psr_pre_plane_update(state, crtc); + if (intel_crtc_vrr_disabling(state, crtc)) { intel_vrr_disable(old_crtc_state); intel_crtc_update_active_timings(old_crtc_state, false); @@ -1185,8 +1187,6 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_drrs_deactivate(old_crtc_state); - intel_psr_pre_plane_update(state, crtc); - if (hsw_ips_pre_update(state, crtc)) intel_crtc_wait_for_next_vblank(crtc); From patchwork Thu Mar 6 13:10:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60BFAC282EC for ; Thu, 6 Mar 2025 13:23:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0128410E988; Thu, 6 Mar 2025 13:23:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="VZBoxotU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6B20210E988; Thu, 6 Mar 2025 13:23:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267409; x=1772803409; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PcVnZOtLMok+IXO0IhpwgO1A7qLrv1m4NunO+MGhUo8=; b=VZBoxotU3Rw7lEBsOYLBRC+0pyDJ5wLUOWcrDZaSYSzosLjPAUSuWoRv 8jUeTipMt9YtVge1a951GK4x7rMO5LsEsAvNiaAKpd9a6bvcY4YaAftz2 ZolQp0iz8xRfjWVPTo2OWqXxDQDNImM+SPAPfuiJcWJeyFVd0u7EHFu5O LSWD5s5ujyPLDSH6RWPctXYiE2iNO22lwsgybPWHwEThtwCxloQMd5ID/ UBqlln7kqf5JmQfnP9LIRB1g4CTug4F4iRFLJLuj9T1L2ydmPtVGD7myV T19hxJguj36Epad/fuy3ct4pPtyc9iKnMmUMmm2PMrrB7kfcYj/b4Eh+/ g==; X-CSE-ConnectionGUID: q7qqWPT8QRO9KDMicIEUUw== X-CSE-MsgGUID: dFAfD+DBQl6I6GWEyGgPbA== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524672" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524672" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:29 -0800 X-CSE-ConnectionGUID: 9ND2tiG1QHOGjZjZ3G5y7g== X-CSE-MsgGUID: oUGNFSyzSeuw2uCMyZZMhw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243168" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:27 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 12/21] drm/i915/display: Move intel_psr_post_plane_update() at the later Date: Thu, 6 Mar 2025 18:40:51 +0530 Message-ID: <20250306131100.3989503-13-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In intel_post_plane_update() there are things which might need to do vblank waits, so enabling PSR as early as we do now is simply counter-productive. Therefore move intel_psr_post_plane_update() at the last of intel_post_plane_update(). Signed-off-by: Ankit Nautiyal Suggested-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e72c6024f33e..322a05648f58 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1050,8 +1050,6 @@ static void intel_post_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - intel_psr_post_plane_update(state, crtc); - intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) @@ -1080,6 +1078,8 @@ static void intel_post_plane_update(struct intel_atomic_state *state, if (audio_enabling(old_crtc_state, new_crtc_state)) intel_encoders_audio_enable(state, crtc); + + intel_psr_post_plane_update(state, crtc); } static void intel_post_plane_update_after_readout(struct intel_atomic_state *state, From patchwork Thu Mar 6 13:10:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A270C28B23 for ; Thu, 6 Mar 2025 13:23:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2D22110E98E; Thu, 6 Mar 2025 13:23:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="HZPG4xG0"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 91A0310E98B; Thu, 6 Mar 2025 13:23:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267411; x=1772803411; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AzuUBmK/yl+VlOHOYo9pYYnI1Fltt6Carfn6zie+KsM=; b=HZPG4xG0Q9MWmSuDrkVADkjyPjJlJoKMg+cuLigAP/mQf3qmItHZf9hM KhtTkx7rNj9tSQCWijH9eW8cOMaZI/T4oHaJM+ScD9MbpN0qixM2TLx05 xF++W+dw65jI+RIJJbRHarA9fOSXt9TuyI8J2atS1aN7Z61qbFG3nyjit aVa3slTMNWFenUSRvaU6NuktghXzbIiKGitWLI+1s+1oM0GMgNWp8dbvz HpzzeVoNC8px9lyn/gbavrnsa9UplHZmc6RppZ5C4ltREeMsA5r5zDsSj zIwnNLyPgrc5cY5ntKjfNgMOyYHCSmcPlfn5snSfJgjdlJ5L17sLEad3k w==; X-CSE-ConnectionGUID: 9cnDd1MhQh2ABDNBq0yTtw== X-CSE-MsgGUID: SHd7IMGyQDKRjiaoYGGANw== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524675" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524675" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:31 -0800 X-CSE-ConnectionGUID: /gyaHbWBT96zpNnMngYdww== X-CSE-MsgGUID: 1GUmYT+tTjyjGGz/tN1z8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243173" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:29 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 13/21] drm/i915/vrr: Refactor condition for computing vmax and LRR Date: Thu, 6 Mar 2025 18:40:52 +0530 Message-ID: <20250306131100.3989503-14-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" LRR and Vmax can be computed only if VRR is supported and vrr.in_range is set. Currently we proceed with vrr timings only for VRR supporting panels and return otherwise. For using VRR TG with fix timings, need to continue even for panels that do not support VRR. To achieve this, refactor the condition for computing vmax and update_lrr so that we can continue for fixed timings for panels that do not support VRR. v2: Set vmax = vmin for non VRR panels. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 622a70e21737..310add32781f 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -363,14 +363,16 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->vrr.in_range = intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)); - if (!crtc_state->vrr.in_range) - return; - - if (HAS_LRR(display)) - crtc_state->update_lrr = true; vmin = intel_vrr_compute_vmin(crtc_state); - vmax = intel_vrr_compute_vmax(connector, adjusted_mode); + + if (crtc_state->vrr.in_range) { + if (HAS_LRR(display)) + crtc_state->update_lrr = true; + vmax = intel_vrr_compute_vmax(connector, adjusted_mode); + } else { + vmax = vmin; + } if (vmin >= vmax) return; From patchwork Thu Mar 6 13:10:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F916C282D1 for ; Thu, 6 Mar 2025 13:23:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B0FB10E98D; Thu, 6 Mar 2025 13:23:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ljEl+qlc"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id BF6C510E985; Thu, 6 Mar 2025 13:23:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267414; x=1772803414; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=glvrblSzXlkC+/LGqIEyhdsLr8G4H/cR3yClTXGoBgY=; b=ljEl+qlcjdKuR109U/cNNz9+QpB0Qa7Jc6/4kusNRGrOI28/eH7esM7T hZflmsUk7Vvc6ISKli86mFjhx9H8IaYCttz4f9rYIjS5XIoFUtC7Brlnd 9jI/DVE1jr1+hgO7jr7CebEuzT6PSTB/zSfmFK9ow5w11+5Nhj8I9TATe 5x9OHQgESOApJMkuxBp4G4XU9Q0hkUXPp2ECMe9WTpFAIJ1TbvBM+20Lb h47hglAdduLSfvbI4lu2XIAgpJc7ZE7/ncnaio+S1X1A0mOTlpgJSuOX+ ULFyoykOCWjSBy+emNylUK6tXlV2Vlc6aArKOdYIuv42sPBr2h52Ln8en Q==; X-CSE-ConnectionGUID: ybKmCrbsTFy0/Am97H2y3A== X-CSE-MsgGUID: R8FgnEQXSPqRTZNDgM7Wqg== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524680" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524680" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:34 -0800 X-CSE-ConnectionGUID: OGKSK16KQ3W96cKIEQUviA== X-CSE-MsgGUID: TIqbjwhMT5ughFhl4qGXNw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243179" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:31 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 14/21] drm/i915/vrr: Always set vrr vmax/vmin/flipline in vrr_{enable/disable} Date: Thu, 6 Mar 2025 18:40:53 +0530 Message-ID: <20250306131100.3989503-15-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For platforms for which vrr timing generator is always set, VRR_CTL enable bit does not need to toggle, so modify the vrr_{enable/disable} for this. At the moment the helper intel_vrr_always_use_vrr_tg() return false for all cases. This will be set later when all other bits are in place. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 40 ++++++++++++++++-------- 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 310add32781f..f523a48e6186 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -558,6 +558,16 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; } +static +bool intel_vrr_always_use_vrr_tg(struct intel_display *display) +{ + if (!HAS_VRR(display)) + return false; + + /* #TODO return true for platforms supporting fixed_rr */ + return false; +} + void intel_vrr_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -576,13 +586,15 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN); - if (crtc_state->cmrr.enable) { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | - trans_vrr_ctl(crtc_state)); - } else { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (!intel_vrr_always_use_vrr_tg(display)) { + if (crtc_state->cmrr.enable) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } else { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } } } @@ -594,12 +606,14 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) if (!old_crtc_state->vrr.enable) return; - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - trans_vrr_ctl(old_crtc_state)); - intel_de_wait_for_clear(display, - TRANS_VRR_STATUS(display, cpu_transcoder), - VRR_STATUS_VRR_EN_LIVE, 1000); - intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); + if (!intel_vrr_always_use_vrr_tg(display)) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(old_crtc_state)); + intel_de_wait_for_clear(display, + TRANS_VRR_STATUS(display, cpu_transcoder), + VRR_STATUS_VRR_EN_LIVE, 1000); + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); + } intel_vrr_set_fixed_rr_timings(old_crtc_state); } From patchwork Thu Mar 6 13:10:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E12DEC282EC for ; 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X-CSE-ConnectionGUID: n172utYjR4KsGNcERTqaZw== X-CSE-MsgGUID: K/fDMg0IQNysQUN5rS8Rhw== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524683" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524683" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:36 -0800 X-CSE-ConnectionGUID: wfQjWN64RnePRSahYc396w== X-CSE-MsgGUID: GbflYuHITlOO9gE2AbaDWw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243185" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:34 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 15/21] drm/i915/display: Use fixed_rr timings in modeset sequence Date: Thu, 6 Mar 2025 18:40:54 +0530 Message-ID: <20250306131100.3989503-16-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During modeset enable sequence, program the fixed timings, and turn on the VRR Timing Generator (VRR TG) for platforms that always use VRR TG. For this intel_vrr_set_transcoder now always programs fixed timings. Later if vrr timings are required, vrr_enable() will switch to the real VRR timings. For platforms that will always use VRR TG, the VRR_CTL Enable bit is set and reset in the transcoder enable/disable path. v2: Update intel_vrr_set_transcoder_timings for fixed_rr. v3: Update intel_set_transcoder_timings_lrr for fixed_rr. (Ville) v4: Have separate functions to enable/disable VRR CTL v5: -For platforms that do not always have VRRTG on, do write bits other than enable bit and also use write the TRANS_VRR_PUSH register. (Ville) -Avoid writing trans_ctl_vrr if !vrr_possible(). v6: -Disable VRR just before intel_ddi_disable_transcoder_func(). (Ville) -Correct the sequence of configuring PUSH and VRR Enable/Disable. (Ville) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++ drivers/gpu/drm/i915/display/intel_vrr.c | 63 ++++++++++++++++----- drivers/gpu/drm/i915/display/intel_vrr.h | 2 + 4 files changed, 60 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 676c1826f15c..6d89a87b3419 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -78,6 +78,7 @@ #include "intel_tc.h" #include "intel_vdsc.h" #include "intel_vdsc_regs.h" +#include "intel_vrr.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -3248,6 +3249,8 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); } + intel_vrr_transcoder_disable(old_crtc_state); + intel_ddi_disable_transcoder_func(old_crtc_state); for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { @@ -3521,6 +3524,8 @@ static void intel_ddi_enable(struct intel_atomic_state *state, intel_ddi_enable_transcoder_func(encoder, crtc_state); + intel_vrr_transcoder_enable(crtc_state); + /* Enable/Disable DP2.0 SDP split config before transcoder */ intel_audio_sdp_split_update(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index bd47cf127b4c..d2988b9a6e7b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1065,6 +1065,8 @@ static void mst_stream_post_disable(struct intel_atomic_state *state, drm_dp_remove_payload_part2(&intel_dp->mst.mgr, new_mst_state, old_payload, new_payload); + intel_vrr_transcoder_disable(old_crtc_state); + intel_ddi_disable_transcoder_func(old_crtc_state); for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { @@ -1326,6 +1328,8 @@ static void mst_stream_enable(struct intel_atomic_state *state, intel_ddi_enable_transcoder_func(encoder, pipe_config); + intel_vrr_transcoder_enable(pipe_config); + intel_ddi_clear_act_sent(encoder, pipe_config); intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, trans), 0, diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index f523a48e6186..d7580b6e4e37 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -460,12 +460,6 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0, PIPE_VBLANK_WITH_DELAY); - if (!intel_vrr_possible(crtc_state)) { - intel_de_write(display, - TRANS_VRR_CTL(display, cpu_transcoder), 0); - return; - } - if (crtc_state->cmrr.enable) { intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), upper_32_bits(crtc_state->cmrr.cmrr_m)); @@ -477,14 +471,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) lower_32_bits(crtc_state->cmrr.cmrr_n)); } - intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), - crtc_state->vrr.vmin - 1); - intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), - crtc_state->vrr.vmax - 1); - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - trans_vrr_ctl(crtc_state)); - intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), - crtc_state->vrr.flipline - 1); + intel_vrr_set_fixed_rr_timings(crtc_state); if (HAS_AS_SDP(display)) intel_de_write(display, @@ -618,6 +605,54 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) intel_vrr_set_fixed_rr_timings(old_crtc_state); } +void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (!HAS_VRR(display)) + return; + + if (!intel_vrr_possible(crtc_state)) + return; + + if (!intel_vrr_always_use_vrr_tg(display)) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(crtc_state)); + return; + } + + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), + TRANS_PUSH_EN); + + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); +} + +void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (!HAS_VRR(display)) + return; + + if (!intel_vrr_possible(crtc_state)) + return; + + if (!intel_vrr_always_use_vrr_tg(display)) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(crtc_state)); + return; + } + + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 0); + + intel_de_wait_for_clear(display, TRANS_VRR_STATUS(display, cpu_transcoder), + VRR_STATUS_VRR_EN_LIVE, 1000); + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); +} + static bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state) { diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 514822577e8a..c4ee8a758e19 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -35,5 +35,7 @@ int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state); int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state); int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state); int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state); +void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); +void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ From patchwork Thu Mar 6 13:10:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F786C28B23 for ; Thu, 6 Mar 2025 13:23:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 040D110E993; Thu, 6 Mar 2025 13:23:40 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Axm3rSw4"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 199AA10E991; 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06 Mar 2025 05:23:38 -0800 X-CSE-ConnectionGUID: MACxD/HBTw+m6mbENuGNzQ== X-CSE-MsgGUID: Ib49HGvfQACT37FazRGL0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243193" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:36 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 16/21] drm/i915/vrr: Use fixed timings for platforms that support VRR Date: Thu, 6 Mar 2025 18:40:55 +0530 Message-ID: <20250306131100.3989503-17-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For fixed refresh rate use fixed timings for all platforms that support VRR. For this add checks to avoid computing and reading VRR for platforms that do not support VRR. v2: Avoid touching check for VRR_CTL_FLIP_LINE_EN. (Ville) v3: Avoid redundant statements in vrr_{compute/get}_config. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index d7580b6e4e37..efa26a39b86a 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -351,6 +351,9 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int vmin, vmax; + if (!HAS_VRR(display)) + return; + /* * FIXME all joined pipes share the same transcoder. * Need to account for that during VRR toggle/push/etc. @@ -374,15 +377,12 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, vmax = vmin; } - if (vmin >= vmax) - return; - crtc_state->vrr.vmin = vmin; crtc_state->vrr.vmax = vmax; crtc_state->vrr.flipline = crtc_state->vrr.vmin; - if (crtc_state->uapi.vrr_enabled) + if (crtc_state->uapi.vrr_enabled && vmin < vmax) intel_vrr_compute_vrr_timings(crtc_state); else if (is_cmrr_frac_required(crtc_state) && is_edp) intel_vrr_compute_cmrr_timings(crtc_state); From patchwork Thu Mar 6 13:10:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004488 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 158EBC282D1 for ; Thu, 6 Mar 2025 13:23:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A679210E995; Thu, 6 Mar 2025 13:23:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="DMOPz0QR"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 418B010E991; Thu, 6 Mar 2025 13:23:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267420; x=1772803420; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GJio0x512rJ8swjCRHUE4B+AeIu0fIllFNeoAao+yL0=; b=DMOPz0QR+G4AbUpR62M8fYf2PvVaFmInqLtkR4MWH1+l1SC10LWBOzy3 OmW99VGkpwqCp02un8ZiCEtPZtYVZ/t+8/kZOPzt8PTRKutfCtd/aw8I6 iP1rQUpQGGmg9fv2mg3TkdrXFuR/aEGc6BA5BXj5FDnobj8mPGsps75rq vyLjZcUiJB192pq+IoRHwm2u957LvHBhM9M5oNqzfPObHwGcWSH8V3CDB wbdEC3uCw+sXCWlZczoR6lwKzXEQWrqWpsLmfEpKskE9yw74Xcurao08I VkHiIc4zot8VvUZmken4kX1eg0mIYs2t58IxK3w557MV5VTYtR60U94Ok g==; X-CSE-ConnectionGUID: NNNHYK+SRlCl5VnODrSC5A== X-CSE-MsgGUID: Jh47+epqTPaQr7zRK9ZtPw== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524691" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524691" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:40 -0800 X-CSE-ConnectionGUID: 0Wm2ZqO1SDWdLndulk9F1g== X-CSE-MsgGUID: 0n6aoKYaRBmc60IStTLq3A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243198" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:38 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 17/21] drm/i915/display: Move vrr.guardband/pipeline_full out of !fastset block Date: Thu, 6 Mar 2025 18:40:56 +0530 Message-ID: <20250306131100.3989503-18-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The vrr.guardband/pipeline_full depend on the vrr.vmin. Since we have set vrr.vmin to adjusted_mode->crtc_vtotal, this shouldn't change on the fly. With this we can move vrr.guardband/pipeline_full out from !fastset block. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 322a05648f58..a642496e366c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5393,8 +5393,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.vmin); PIPE_CONF_CHECK_I(vrr.vmax); PIPE_CONF_CHECK_I(vrr.flipline); - PIPE_CONF_CHECK_I(vrr.pipeline_full); - PIPE_CONF_CHECK_I(vrr.guardband); PIPE_CONF_CHECK_I(vrr.vsync_start); PIPE_CONF_CHECK_I(vrr.vsync_end); PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); @@ -5402,6 +5400,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(cmrr.enable); } + PIPE_CONF_CHECK_I(vrr.pipeline_full); + PIPE_CONF_CHECK_I(vrr.guardband); + #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_LLI From patchwork Thu Mar 6 13:10:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004489 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4ADBC28B23 for ; Thu, 6 Mar 2025 13:23:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 840A710E996; Thu, 6 Mar 2025 13:23:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CwOjaXcJ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6F44F10E997; Thu, 6 Mar 2025 13:23:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267422; x=1772803422; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mcNOxfblrK8v82A92JD1BR5Qubo/b6WSD0Hs0SsG0MM=; b=CwOjaXcJDpTImaTKirx2gi6QeN/Vul+0LLfU8DExLMLlRj9s5UlS9rtn deeB/iG+2XhpHTZJUYBYlkVFs6FplZhp8uybmpWX8RXhTZfmTzaD4VPlk xiTlGs2+yRALCJ+5E2tjzXz3LwNo2scdb4cRa8at8KSjJfFNBeZ+GyDb4 lFqLzbJBpgQ4mLJUtCwQRNK4eoeOx9A12EHC4FBSlIv6YAB3RzKfGnDeX oHN+urYYW4WcSv5EUfAvPrZz8q/ijzcZ/ExSA7dsjBdYPpn0pDJAdu2vo /I0GpXsx4BHN6GlZRfJ/DvJh+cVI0y9JPoU2PL6S3wQkHfLM5+kA/H95+ A==; X-CSE-ConnectionGUID: 9nWyBb/mSfSHxpOUKQ/AhQ== X-CSE-MsgGUID: v08xAq+hQhWzhDPPqSRywg== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524692" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524692" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:42 -0800 X-CSE-ConnectionGUID: v2Z60iaWR7aLED001hNo3A== X-CSE-MsgGUID: guDf0sLVQyG5guoXGhKYNQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243204" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:40 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 18/21] drm/i915/display: Use fixed rr timings in intel_set_transcoder_timings_lrr() Date: Thu, 6 Mar 2025 18:40:57 +0530 Message-ID: <20250306131100.3989503-19-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To have Guardband/Pipeline_full reconfigured seamlessly, move the guardband and pipeline_full from intel_pipe_config_compare() to fastboot exception. Update the intel_set_transcoder_timings_lrr() function to use fixed refresh rate timings for platforms which always use VRR timing generator. v2: Fix typo in check for fastboot exception. (Ville) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++-- drivers/gpu/drm/i915/display/intel_vrr.c | 1 - drivers/gpu/drm/i915/display/intel_vrr.h | 1 + 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a642496e366c..b46987b46be8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2770,6 +2770,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); + + intel_vrr_set_fixed_rr_timings(crtc_state); + intel_vrr_transcoder_enable(crtc_state); } static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) @@ -5400,8 +5403,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(cmrr.enable); } - PIPE_CONF_CHECK_I(vrr.pipeline_full); - PIPE_CONF_CHECK_I(vrr.guardband); + if (!fastset || !allow_vblank_delay_fastset(current_config)) { + PIPE_CONF_CHECK_I(vrr.pipeline_full); + PIPE_CONF_CHECK_I(vrr.guardband); + } #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index efa26a39b86a..58cc86c32239 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -284,7 +284,6 @@ int intel_vrr_fixed_rr_flipline(const struct intel_crtc_state *crtc_state) return intel_vrr_fixed_rr_vtotal(crtc_state); } -static void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index c4ee8a758e19..d857633bc02c 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -37,5 +37,6 @@ int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state); int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); +void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ From patchwork Thu Mar 6 13:10:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004490 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D869C282D1 for ; Thu, 6 Mar 2025 13:23:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B71E910E999; Thu, 6 Mar 2025 13:23:45 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CHsmS0Cx"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 98E9C10E998; Thu, 6 Mar 2025 13:23:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267425; x=1772803425; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nhP02N/m0zthQJh66owGWX0HweL1uI3ABYo/+PSneY4=; b=CHsmS0Cx0Ou6wpeI7Y3W6HtRrdAbr6RgdntAW1k5BvuCOSrV8FOq/KBe H/HXL8crP/erhEzYnj/CGqT5Goajb9XhvOfQyWZjy/zzo8OTGNZKVjWb/ XLrkovUtWUK5l9a5KEW9hu4xLBJR9GIXkh3StA5iYWmKuPv1XudPXhfEQ NDEErPgu2KkXkR8plsaEJPWsCyI9YN+7cU9RVw1odC95eLat9YJJCF2IG NDJsyejZF/1ySLYxeqL07nMhO/+IZb/YMaFQKj34qj0Wo99rou1qL7axz twLrJl0IOyRC/l/1O0zic13UBgGDwGLuuR3k5w6e/TwEqUFMwc/dcFhld A==; X-CSE-ConnectionGUID: Aoy+0AOrRnalLsYtv2RCpA== X-CSE-MsgGUID: jQE1DI6tQhyzIuKyxuZnBA== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524694" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524694" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:44 -0800 X-CSE-ConnectionGUID: yDcl1fHWQwCxP6RD5owypw== X-CSE-MsgGUID: HpfnAxRYQFGQvx6syiSQtQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243209" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:42 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 19/21] drm/i915/vrr: Allow fixed_rr with pipe joiner Date: Thu, 6 Mar 2025 18:40:58 +0530 Message-ID: <20250306131100.3989503-20-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" VRR with joiner is currently disabled as it still needs some work to correctly sequence the primary and secondary transcoders. However, we can still use VRR Timing generator in fixed refresh rate for joiner and since it just need to program vrr timings once and does not involve changing timings on the fly. We still need to skip the VRR and LRR for joiner. To achieve this set vrr.in_range to 0 for joiner case, so that we do not try VRR and LRR for the joiner case. v2: Avoid checks for secondary pipes, where not required. (Ville) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_vrr.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 58cc86c32239..3329d60afa45 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -353,19 +353,23 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, if (!HAS_VRR(display)) return; - /* - * FIXME all joined pipes share the same transcoder. - * Need to account for that during VRR toggle/push/etc. - */ - if (crtc_state->joiner_pipes) - return; - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) return; crtc_state->vrr.in_range = intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)); + /* + * Allow fixed refresh rate with VRR Timing Generator. + * For now set the vrr.in_range to 0, to allow fixed_rr but skip actual + * VRR and LRR. + * #TODO For actual VRR with joiner, we need to figure out how to + * correctly sequence transcoder level stuff vs. pipe level stuff + * in the commit. + */ + if (crtc_state->joiner_pipes) + crtc_state->vrr.in_range = 0; + vmin = intel_vrr_compute_vmin(crtc_state); if (crtc_state->vrr.in_range) { @@ -488,6 +492,9 @@ void intel_vrr_send_push(struct intel_dsb *dsb, if (!crtc_state->vrr.enable) return; + if (intel_crtc_is_joiner_secondary(crtc_state)) + return; + if (dsb) intel_dsb_nonpost_start(dsb); From patchwork Thu Mar 6 13:10:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8E88C28B25 for ; Thu, 6 Mar 2025 13:23:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 613B610E99A; Thu, 6 Mar 2025 13:23:47 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mpsDIsGS"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id BC5FD10E99B; Thu, 6 Mar 2025 13:23:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267427; x=1772803427; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=//1q3UpLIslAw9/InzE7/mfBu8qMkMXhX7OT2BNY7E8=; b=mpsDIsGSB1Oc8pj/xRLm3/QnKM2/35CIAh+ghD/SZgcFHgDQOeswYq0w VH+PFhqb1neUV5ezWosNjmbo9ojf0e2Gb6ainwy3AmSX87hWzl7tePHo0 FLe4TpUxetmBdPgC+SBbWq+lz2+iTT96L2uHj4yuFVTMd1zj+8xlTYmA2 Wcb2RYOTQZKpBK0YEKQaiZETL868bNf3msJb+/xoB2GgGa5xmy09oDijN u5FsvnZJYlP7J33pfx+a5bhf6banU3/XYVZgHD+BUOksf+fB1HaeP2u2v lR4oyNGg6vMXc9bIJG590yk8fwM9tRBSELaLLyVjvW+eEwybPIC0uW2nY A==; X-CSE-ConnectionGUID: E1if+ziQT8yFVilIxoGdNw== X-CSE-MsgGUID: ketEOlPxQeqvaqKtki88JQ== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524697" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524697" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:47 -0800 X-CSE-ConnectionGUID: 5lSZfCAdRIesYlVHlnBiSA== X-CSE-MsgGUID: Ihd90KpSTaOweNJOTBEosQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243214" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:44 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 20/21] drm/i915/vrr: Always use VRR timing generator for MTL+ Date: Thu, 6 Mar 2025 18:40:59 +0530 Message-ID: <20250306131100.3989503-21-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently VRR timing generator is used only when VRR is enabled by userspace for sinks that support VRR. From MTL+ gradually move away from the older timing generator and use VRR timing generator for both variable and fixed timings. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_vrr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 3329d60afa45..a1ad9432bc28 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -557,7 +557,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display) if (!HAS_VRR(display)) return false; - /* #TODO return true for platforms supporting fixed_rr */ + if (DISPLAY_VER(display) >= 14) + return true; + return false; } From patchwork Thu Mar 6 13:11:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14004492 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6EDBDC28B23 for ; Thu, 6 Mar 2025 13:23:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 14B9A10E99F; Thu, 6 Mar 2025 13:23:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="P4uvoz5h"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5FA3810E99B; Thu, 6 Mar 2025 13:23:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741267429; x=1772803429; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mK57pJrtD3MmVVdGqQAkIMiM2QjY6GnL2mqV+OQsEwc=; b=P4uvoz5hGD2KS1fxPEmnsrImGh/5VaWobJH6EMk4ybIwASC1JXM6VSOz Qiv7nifOO2xu062a8/cl04Bz2X5TDV6APQuKikOqlbtiWUx97EN/04j1u L4iXsCu4uV9ZZoAQnefFL1dOVXBmSlfXsqg1nXec0IfLF7MjAtMLlz3wN mU6E9C+M9WhXC6UiWbOP6yHOxWAOzPR5u5XByNWKV8LiR0qJLfMmowvHL GLP0C2o1nh0mMTAm3DuIQgZ8FGw/hVJhvHWF/qWg2+D/c9cG42WFfsJvg QNgIoE1jCR9uvIpbIFy+LcJ4nkeRbdjky+dlqfI9vj4ot17VKhuQR4lwk Q==; X-CSE-ConnectionGUID: cH3lsT6MSgSi2+YH/ya67A== X-CSE-MsgGUID: Dj51EnZIR8aYpX53wmFFgg== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="41524698" X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="41524698" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:49 -0800 X-CSE-ConnectionGUID: ZWfUyXCwQamtOKQDLH6Zww== X-CSE-MsgGUID: K/+LmimoRhq7RTsMAcZVqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,226,1736841600"; d="scan'208";a="142243219" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 05:23:47 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 21/21] drm/i915/display: Add fixed_rr to crtc_state dump Date: Thu, 6 Mar 2025 18:41:00 +0530 Message-ID: <20250306131100.3989503-22-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> References: <20250306131100.3989503-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add fixed refresh rate mode in crtc_state dump. VRR Timing Generator is running in fixed refresh rate mode when vrr.enable is unset and vrr.vmin = vrr.vmax = vrr.flipline. v2: Add check for vrr.enable. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 ++- drivers/gpu/drm/i915/display/intel_vrr.c | 1 - drivers/gpu/drm/i915/display/intel_vrr.h | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 599ddce96371..974598e29bff 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -294,8 +294,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, pipe_config->hw.adjusted_mode.crtc_vdisplay, pipe_config->framestart_delay, pipe_config->msa_timing_delay); - drm_printf(&p, "vrr: %s, vmin: %d, vmax: %d, flipline: %d, pipeline full: %d, guardband: %d vsync start: %d, vsync end: %d\n", + drm_printf(&p, "vrr: %s, fixed_rr: %s, vmin: %d, vmax: %d, flipline: %d, pipeline full: %d, guardband: %d vsync start: %d, vsync end: %d\n", str_yes_no(pipe_config->vrr.enable), + str_yes_no(intel_vrr_is_fixed_rr(pipe_config) && !pipe_config->vrr.enable), pipe_config->vrr.vmin, pipe_config->vrr.vmax, pipe_config->vrr.flipline, pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, pipe_config->vrr.vsync_start, pipe_config->vrr.vsync_end); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index a1ad9432bc28..fe589092ce53 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -661,7 +661,6 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state) intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); } -static bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state) { return crtc_state->vrr.flipline && diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index d857633bc02c..14a372204a54 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -38,5 +38,6 @@ int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state); +bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */