From patchwork Fri Mar 7 10:52:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 14006222 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3828BC28B25 for ; Fri, 7 Mar 2025 10:52:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C38C810EB4C; Fri, 7 Mar 2025 10:52:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="a9pU3lvN"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6B7C410EB42; Fri, 7 Mar 2025 10:52:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741344772; x=1772880772; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8waxI/5JIzWsk046EX6aOG4dJvetZPgN++69nSPy0bU=; b=a9pU3lvNjLv2qKqaU81TFnd9UNwKJOqaY01U5iqLCWM27BldSMQm8I69 le5Iwh+Kx7LHlhb0LzU1l2o5HlmQxhhXELaOY4h/qocCTp8evIap6GF7R 5CqwJib304Djx/DHcChFBjuRy4hrFqjFCM2QgjfXAWB99q6iCJ3Fjknkl q+PdhyZunru4CUpOnKCSxHc4K1d8Ci2gH8exy6FAW3KyyMLJR/HsrrFS+ xKuFr2UoKTBS59aWl1FXlokEwKhWGWtdi+fNr7JCskaOz5q8QeLEU2S2n Dp5d6tuSsGh3NnHZS1ExfA39rP9Sswf/Nwu+GQtIP+kffXnoevxHq9UDl Q==; X-CSE-ConnectionGUID: K9cB/OseQe+XlHPqItmc8g== X-CSE-MsgGUID: 4Sa+n3aiRw+9BaVqvaCWPg== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="42301646" X-IronPort-AV: E=Sophos;i="6.14,229,1736841600"; d="scan'208";a="42301646" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:52 -0800 X-CSE-ConnectionGUID: +4Sc99ZjT+WuULAGFuo/kQ== X-CSE-MsgGUID: wKu5r0N1R2OEapesZO1rTA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123481556" Received: from mlehtone-mobl.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.100]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:48 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [RFC PATCH 01/11] drm/i915/display: Add new interface for getting dc_state Date: Fri, 7 Mar 2025 12:52:27 +0200 Message-ID: <20250307105237.2909849-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307105237.2909849-1-jouni.hogander@intel.com> References: <20250307105237.2909849-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To implement workaround for underrun on idle PSR HW issue (Wa_16025596647) we need to have current configured DC state available. Add new interface for this purpose. Signed-off-by: Jouni Högander --- .../drm/i915/display/intel_display_power.c | 29 +++++++++++++++++++ .../drm/i915/display/intel_display_power.h | 1 + 2 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index f7171e6932dc..6dfe85a5528f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -322,6 +322,35 @@ void intel_display_power_set_target_dc_state(struct intel_display *display, mutex_unlock(&power_domains->lock); } +/** + * intel_display_power_get_current_dc_state - Set target dc state. + * @display: display device + * + * This function set the "DC off" power well target_dc_state, + * based upon this target_dc_stste, "DC off" power well will + * enable desired DC state. + */ +u32 intel_display_power_get_current_dc_state(struct intel_display *display) +{ + struct i915_power_well *power_well; + struct i915_power_domains *power_domains = &display->power.domains; + u32 current_dc_state = DC_STATE_DISABLE; + + mutex_lock(&power_domains->lock); + power_well = lookup_power_well(display, SKL_DISP_DC_OFF); + + if (drm_WARN_ON(display->drm, !power_well)) + goto unlock; + + current_dc_state = intel_power_well_is_enabled(display, power_well) ? + DC_STATE_DISABLE : power_domains->target_dc_state; + +unlock: + mutex_unlock(&power_domains->lock); + + return current_dc_state; +} + static void __async_put_domains_mask(struct i915_power_domains *power_domains, struct intel_power_domain_mask *mask) { diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 1b53d67f9b60..f8813b0e16df 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -183,6 +183,7 @@ void intel_display_power_suspend(struct intel_display *display); void intel_display_power_resume(struct intel_display *display); void intel_display_power_set_target_dc_state(struct intel_display *display, u32 state); +u32 intel_display_power_get_current_dc_state(struct intel_display *display); bool intel_display_power_is_enabled(struct intel_display *display, enum intel_display_power_domain domain); From patchwork Fri Mar 7 10:52:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 14006221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B39EC28B23 for ; Fri, 7 Mar 2025 10:52:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CBB3B10EB47; Fri, 7 Mar 2025 10:52:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Cb89nzuC"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9057810EB3F; Fri, 7 Mar 2025 10:52:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741344772; x=1772880772; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LbLwEor69CZi/xrghUL5G93RROsWfYjjPsYz+hTnXAE=; b=Cb89nzuCBabPzGeEOgCeoMGdtrhG5UYlczdYViWUvc4bpwko9mFv26et SD0xd0MlCig0ghM3nXNo+mZp4YnXPZAuDANxduN0mBRjOIEdXUudjhdzx Ea9auE7GTHPSLwHv/f2rZJXNtqilbobywpTgbotCcjqwokplfdvsHHFP0 K5/baPX8fDjUPLyYP2zinYZHBsNctDM6O1fKi28z28RAXcs/Je3QhH6Sj O9xyOe2KGXne3tFtuX1AYtOU6Qn2juJYb37qgkrOIUBhMFjdh75aCNwJq jL2iglOnEqSjQMlichw9e1t80UW05NgZj1fjPfxGCaNCHRgwbjPgNCqtg g==; X-CSE-ConnectionGUID: b/yyLXLCQr6Kbl4OIFvLew== X-CSE-MsgGUID: JEBh+gedT2OzlkQsHcdjYQ== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="42301647" X-IronPort-AV: E=Sophos;i="6.14,229,1736841600"; d="scan'208";a="42301647" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:52 -0800 X-CSE-ConnectionGUID: ZR84WESrTICiJE6/LouM0A== X-CSE-MsgGUID: UO2TDz6VRXeRPpq1YntLug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123481563" Received: from mlehtone-mobl.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.100]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:51 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [RFC PATCH 02/11] drm/i915/psr: Store enabled non-psr pipes into intel_crtc_state Date: Fri, 7 Mar 2025 12:52:28 +0200 Message-ID: <20250307105237.2909849-3-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307105237.2909849-1-jouni.hogander@intel.com> References: <20250307105237.2909849-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To implement workaround for underrun on idle PSR HW issue (Wa_16025596647) we need to know enabled. Figure out which non-PSR pipes we will have active and store it into intel_crtc_state->active_non_psr_pipes. This is currently assuming only one eDP on a time. I.e. possible secondary eDP with PSR capable panel is not considered. Bspec: 74151 Signed-off-by: Jouni Högander --- .../drm/i915/display/intel_display_types.h | 3 +++ drivers/gpu/drm/i915/display/intel_psr.c | 23 +++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 99a6fd2900b9..3d203a2003f1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1114,6 +1114,7 @@ struct intel_crtc_state { bool wm_level_disabled; u32 dc3co_exitline; u16 su_y_granularity; + u8 active_non_psr_pipes; /* * Frequency the dpll for the port should run at. Differs from the @@ -1650,6 +1651,8 @@ struct intel_psr { u8 entry_setup_frames; bool link_ok; + + u8 active_non_psr_pipes; }; struct intel_dp { diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4e938bad808c..1415e1e7aaf2 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1658,6 +1658,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, { struct intel_display *display = to_intel_display(intel_dp); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); + struct intel_crtc *crtc; + u8 active_pipes = 0; if (!psr_global_enabled(intel_dp)) { drm_dbg_kms(display->drm, "PSR disabled by flag\n"); @@ -1711,6 +1714,24 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, drm_dbg_kms(display->drm, "PSR disabled to workaround PSR FSM hang issue\n"); } + + /* Rest is for Wa_16025596647 */ + if (DISPLAY_VER(display) != 20 && + !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) + return; + + /* Not needed by Panel Replay */ + if (crtc_state->has_panel_replay) + return; + + /* We ignore possible secondary PSR/Panel Replay capable eDP */ + for_each_intel_crtc(display->drm, crtc) + active_pipes |= crtc->active ? BIT(crtc->pipe) : 0; + + active_pipes = intel_calc_active_pipes(state, active_pipes); + + crtc_state->active_non_psr_pipes = active_pipes & + ~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe); } void intel_psr_get_config(struct intel_encoder *encoder, @@ -1995,6 +2016,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, intel_dp->psr.psr2_sel_fetch_cff_enabled = false; intel_dp->psr.req_psr2_sdp_prior_scanline = crtc_state->req_psr2_sdp_prior_scanline; + intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes; if (!psr_interrupt_error_check(intel_dp)) return; @@ -2170,6 +2192,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_dp->psr.psr2_sel_fetch_enabled = false; intel_dp->psr.su_region_et_enabled = false; intel_dp->psr.psr2_sel_fetch_cff_enabled = false; + intel_dp->psr.active_non_psr_pipes = 0; } /** From patchwork Fri Mar 7 10:52:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 14006223 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C52AC19F32 for ; Fri, 7 Mar 2025 10:52:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3483F10EB3F; Fri, 7 Mar 2025 10:52:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="X6K3A58+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1D1CF10EB49; Fri, 7 Mar 2025 10:52:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741344774; x=1772880774; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VEuzruUgAHJn4jpTWHJ15d6soITmSTRigC0gYYcd8As=; b=X6K3A58+ZamyOTbMWZK6HNk4BejhMp3RLt1gJsgpOEvzx/xgnDaAIP8x ey3S+tSdPBoaI6VbhfYFVpc7I+yMngb0vNnOzrpK742RGuOnPTaM9rvN4 zjswir6FesOsytgxRZXbIgIWpQyEaTDV26jftpdvssNu+8POkd8cCyc0L mF/Dzhvz8p3WT7m71tlVUSomkIlwUECZalmNz3sKUFlO/f/lVFeVBqo2/ /h5PgLYfYNh9C2CQcXNJy2hqbfwMIV3TvTsq/LbOLBBy/oSBA3ibW+kP7 Nu8kirg+TLVOxKaiIE/mNV0HVcvSX3U54wCcsd+wABenIpo8wHFSd2giK w==; X-CSE-ConnectionGUID: tjpCZH2yR9azfmvnyjVzEw== X-CSE-MsgGUID: v727+RQlScmQTW2w1aMMIA== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="42301648" X-IronPort-AV: E=Sophos;i="6.14,229,1736841600"; d="scan'208";a="42301648" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:53 -0800 X-CSE-ConnectionGUID: 1bBo56gFS7mpezxIlpjIDg== X-CSE-MsgGUID: uyLCMbxnR9SP3oo1Sw0wtg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123481572" Received: from mlehtone-mobl.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.100]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:52 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [RFC PATCH 03/11] drm/i915/dmc: Add PIPEDMC_EVT_CTL register definition Date: Fri, 7 Mar 2025 12:52:29 +0200 Message-ID: <20250307105237.2909849-4-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307105237.2909849-1-jouni.hogander@intel.com> References: <20250307105237.2909849-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To implement workaround for underrun on idle PSR HW issue (Wa_16025596647) we need PIPEDMC_EVT_CTL_4 register. Add PIPEDMC_EVT_CTL_4 register definitions. Bspec: 67576 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_dmc_regs.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h index 1bf446f96a10..2f1e3cb1a247 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h @@ -21,6 +21,12 @@ #define MTL_PIPEDMC_CONTROL _MMIO(0x45250) #define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4) +#define _MTL_PIPEDMC_EVT_CTL_4_A 0x5f044 +#define _MTL_PIPEDMC_EVT_CTL_4_B 0x5f444 +#define MTL_PIPEDMC_EVT_CTL_4(pipe) _MMIO_PIPE(pipe, \ + _MTL_PIPEDMC_EVT_CTL_4_A, \ + _MTL_PIPEDMC_EVT_CTL_4_B) + #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000 #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000 From patchwork Fri Mar 7 10:52:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 14006224 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00B5DC28B23 for ; Fri, 7 Mar 2025 10:52:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7523710EB4D; Fri, 7 Mar 2025 10:52:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AIY7GEC4"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6443F10EB52; Fri, 7 Mar 2025 10:52:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741344775; x=1772880775; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R07NatXvhtjELYeQFieH/tA0zob43xYkjUsLbMlBDN0=; b=AIY7GEC4p77sdZPKvkWawAmd6TST6u+8WPjMBr/ZOFyDfeSKuZwyPbQO hZgXaacjMXgBzluIPQujmWFDjSKxQbLncK2DPMXeYZpx0hMpj4YB9UZM7 JOKx4OCeOo+UtvVkqiyonKf5wLCB8Fr0R9idUo0jrUOnTE8P4WIC1zvm0 GNNVEa+JVErP3UaVdwBWYP8DAs/lCXfSyIBSTkEUXe6St/7Ux6j/Jew0p YxsX5fJ9rx/zcRHiyxfOF20fvOM/5QZZfbc2oFG3liImevnOxUUhnsvvo HFEJ5TzDrCvcb/LEcorH3Hde8A65X0TzlauWziSZN/NFUpb2j4aDYgcdn g==; X-CSE-ConnectionGUID: VcskwHIMTCytuFyKf78ekQ== X-CSE-MsgGUID: R682Sh9dQTCSLBOGhVtiJg== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="42301649" X-IronPort-AV: E=Sophos;i="6.14,229,1736841600"; d="scan'208";a="42301649" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:55 -0800 X-CSE-ConnectionGUID: mwas2cDkSfKvPcH1pL1nww== X-CSE-MsgGUID: j6IijIrwSvWW6KN99OPFxQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123481579" Received: from mlehtone-mobl.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.100]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:54 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [RFC PATCH 04/11] drm/i915/dmc: Add PIPEDMC_BLOCK_PKGC_SW definitions Date: Fri, 7 Mar 2025 12:52:30 +0200 Message-ID: <20250307105237.2909849-5-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307105237.2909849-1-jouni.hogander@intel.com> References: <20250307105237.2909849-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We need PIPEDMC_BLOCK_PKGC_SW definitions to implement workaround for underrun on idle PSR HW issue (Wa_16025596647). Add PIPEDMC_BLOCK_PKGC_SW register definitions. Bspec: 71265 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_dmc_regs.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h index 2f1e3cb1a247..e16ea3f16ed8 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h @@ -27,6 +27,14 @@ _MTL_PIPEDMC_EVT_CTL_4_A, \ _MTL_PIPEDMC_EVT_CTL_4_B) +#define PIPEDMC_BLOCK_PKGC_SW_A 0x5f1d0 +#define PIPEDMC_BLOCK_PKGC_SW_B 0x5F5d0 +#define PIPEDMC_BLOCK_PKGC_SW(pipe) _MMIO_PIPE(pipe, \ + PIPEDMC_BLOCK_PKGC_SW_A, \ + PIPEDMC_BLOCK_PKGC_SW_B) +#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS BIT(31) +#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_UNTIL_NEXT_FRAMESTART BIT(15) + #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000 #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000 From patchwork Fri Mar 7 10:52:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 14006225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80786C282DE for ; Fri, 7 Mar 2025 10:52:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F304810EB55; Fri, 7 Mar 2025 10:52:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="aqs1Nyqf"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id D6EA710EB4F; Fri, 7 Mar 2025 10:52:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741344776; x=1772880776; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2BC5w8fax8/sRN3SXg7xVNiJG0r4bv3wvx/1T8E6fcU=; b=aqs1NyqfBR5OU5qd5ZJn6tL3smBmwIYG0IoFDVSCegWEfbtfnt9ENZmI hcdHKBKjJK2qW3taUsq6BRp4WyQE1nqVB0B6xDOCoXWeFbIGqmYaJOohi IJpF1k/F69ebbAjP/VQ92sQUhaPmCnS8lOxAn/PggwZqUzHqdu7DMhiX3 zDPS236Tuy7GJd7mG1qz71VUSa22DKdoqUrUyOQBr+1th0bYtIVik9R75 L9NxzSFyxyOGmzHVG9CAOjLe6HygE9HP5RgZ2jG7Y0Qab2+sGtC0OZVt2 PBud01AvCH0zdRlARDKUoeJyhhi5Zkagg31w6kwCZj7NtNBBjnRiP3oaX g==; X-CSE-ConnectionGUID: gaKgottrTyOLRISRu2SQCg== X-CSE-MsgGUID: gJGZVTG5RbmZYN284XKH9w== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="42301651" X-IronPort-AV: E=Sophos;i="6.14,229,1736841600"; d="scan'208";a="42301651" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:56 -0800 X-CSE-ConnectionGUID: tqDkxyU6QyOxB/q0zYD8qw== X-CSE-MsgGUID: 3gpJW2tBT0KhkhGHZekiWA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123481588" Received: from mlehtone-mobl.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.100]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:55 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [RFC PATCH 05/11] drm/i915/psr: Write PIPEDMC_BLOCK_PKGC_SW when enabling PSR Date: Fri, 7 Mar 2025 12:52:31 +0200 Message-ID: <20250307105237.2909849-6-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307105237.2909849-1-jouni.hogander@intel.com> References: <20250307105237.2909849-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Write PIPEDMC_BLOCK_PKGC_SW when enabling PSR as described in workaround for underrun on idle PSR HW issue (Wa_16025596647). Bspec: 74151 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1415e1e7aaf2..a3946eef44f0 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -37,6 +37,7 @@ #include "intel_de.h" #include "intel_display_irq.h" #include "intel_display_types.h" +#include "intel_dmc_regs.h" #include "intel_dp.h" #include "intel_dp_aux.h" #include "intel_frontbuffer.h" @@ -1961,6 +1962,13 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, intel_de_rmw(display, CLKGATE_DIS_MISC, 0, CLKGATE_DIS_MISC_DMASC_GATING_DIS); } + + /* Wa_16025596647 */ + if ((DISPLAY_VER(display) == 20 || + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + !intel_dp->psr.panel_replay_enabled) + intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(intel_dp->psr.pipe), 0, + PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS); } static bool psr_interrupt_error_check(struct intel_dp *intel_dp) @@ -2186,6 +2194,13 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) DP_RECEIVER_ALPM_CONFIG, 0); } + /* Wa_16025596647 */ + if ((DISPLAY_VER(display) == 20 || + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + !intel_dp->psr.panel_replay_enabled) + intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(intel_dp->psr.pipe), + PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, 0); + intel_dp->psr.enabled = false; intel_dp->psr.panel_replay_enabled = false; intel_dp->psr.sel_update_enabled = false; From patchwork Fri Mar 7 10:52:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 14006226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D628DC282DE for ; Fri, 7 Mar 2025 10:53:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D96A10EB52; Fri, 7 Mar 2025 10:53:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cm/XTcUQ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 526E410EB56; Fri, 7 Mar 2025 10:52:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741344778; x=1772880778; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Bu1meTdequdvbrd89fvfK1Ayb0CstBKrpv/ibeqVMuY=; b=cm/XTcUQSfmbQ4ULReRkrZThlLXPqViSeKjwbB6hXc9q/f8jabntft70 sKPuvfpMRxEsvq71ZiNINF7DMvJ9mK94HapYHnklvu8dWD1sQnx5/gJvE LDlCEgLnHJ3INW3VXGVi05MJejquUQRZMXWhoJXyGBs1qVjPiZM1BLjkS 1Que224hw3ysg7OC0+KCf3tdQr3enhrD0mCz+psRNOJUAGSQrggv6ihT2 bh5BTrVpLdw3WG48bfwAZ1PuyB6LsCYPOpg+0FlpLBj3JjvojYDB01LLr BZ6DqkgZ0AoNH736CkrFi+lrBwKFV2CGCq+twewUYVWtzP++OijlJnaPI Q==; X-CSE-ConnectionGUID: MIQLtqKtR6K1TyWI39ou+g== X-CSE-MsgGUID: HuNgGvXMR9yyOhoW78YqUg== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="42301654" X-IronPort-AV: E=Sophos;i="6.14,229,1736841600"; d="scan'208";a="42301654" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:58 -0800 X-CSE-ConnectionGUID: aXX0sBuHRW6UIxlT/yBaxQ== X-CSE-MsgGUID: UoyqUC4kSFOL5bWx/5u2Ew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123481595" Received: from mlehtone-mobl.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.100]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:57 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [RFC PATCH 06/11] drm/i915/psr: Add mechanism to notify PSR of pipe enable/disable Date: Fri, 7 Mar 2025 12:52:32 +0200 Message-ID: <20250307105237.2909849-7-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307105237.2909849-1-jouni.hogander@intel.com> References: <20250307105237.2909849-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We need to apply/remove workaround for underrun on idle PSR HW issue (Wa_16025596647) when new pipe is enabled or pipe is getting disabled. This patch implements mechanism to notify PSR about pipe enable/disable and applies/removes the workaround using this notification. Bspec: 74151 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 106 +++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 2 + 2 files changed, 108 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a3946eef44f0..4b62d5832cbf 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "i915_drv.h" #include "i915_reg.h" @@ -3664,6 +3665,111 @@ void intel_psr_unlock(const struct intel_crtc_state *crtc_state) } } +/* Wa_16025596647 */ +static void psr1_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp, + bool dc5_dc6_blocked) +{ + struct intel_display *display = to_intel_display(intel_dp); + u32 val; + + if (dc5_dc6_blocked) + val = DMC_EVT_CTL_ENABLE | DMC_EVT_CTL_RECURRING | + REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, + DMC_EVT_CTL_TYPE_EDGE_0_1) | + REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, + DMC_EVT_CTL_EVENT_ID_VBLANK_A); + else + val = REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, + DMC_EVT_CTL_EVENT_ID_FALSE) | + REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, + DMC_EVT_CTL_TYPE_EDGE_0_1); + + intel_de_write(display, MTL_PIPEDMC_EVT_CTL_4(intel_dp->psr.pipe), + val); +} + +/* Wa_16025596647 */ +static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + u32 current_dc_state = intel_display_power_get_current_dc_state(display); + struct drm_vblank_crtc *vblank = &display->drm->vblank[intel_dp->psr.pipe]; + + return (current_dc_state != DC_STATE_EN_UPTO_DC5 && + current_dc_state != DC_STATE_EN_UPTO_DC6) || + intel_dp->psr.active_non_psr_pipes || + READ_ONCE(vblank->enabled); +} + +/* Wa_16025596647 */ +static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp) +{ + bool dc5_dc6_blocked; + + if (!intel_dp->psr.active) + return; + + dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp); + + if (intel_dp->psr.sel_update_enabled) + psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 : + psr_compute_idle_frames(intel_dp)); + else + psr1_apply_underrun_on_idle_wa_locked(intel_dp, dc5_dc6_blocked); +} + +/** + * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe + * @state: intel atomic state + * @crtc: intel crtc + * @enable: enable/disable + * + * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply + * remove the workaround when pipe is getting enabled/disabled + */ +void intel_psr_notify_pipe_change(struct intel_atomic_state *state, + struct intel_crtc *crtc, bool enable) +{ + struct intel_display *display = to_intel_display(state); + struct intel_encoder *encoder; + + if (DISPLAY_VER(display) != 20 && + !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) + return; + + for_each_intel_encoder_with_psr(display->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + u8 active_non_psr_pipes; + + mutex_lock(&intel_dp->psr.lock); + + if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) + goto unlock; + + active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes; + + if (enable) + active_non_psr_pipes |= BIT(crtc->pipe); + else + active_non_psr_pipes &= ~BIT(crtc->pipe); + + if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes) + goto unlock; + + if ((enable && intel_dp->psr.active_non_psr_pipes) || + (!enable && !intel_dp->psr.active_non_psr_pipes)) { + intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; + goto unlock; + } + + intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; + + intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); +unlock: + mutex_unlock(&intel_dp->psr.lock); + } +} + static void psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) { diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index a43a374cff55..273e70a50915 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -60,6 +60,8 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, void intel_psr_pause(struct intel_dp *intel_dp); void intel_psr_resume(struct intel_dp *intel_dp); bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state); +void intel_psr_notify_pipe_change(struct intel_atomic_state *state, + struct intel_crtc *crtc, bool enable); bool intel_psr_link_ok(struct intel_dp *intel_dp); void intel_psr_lock(const struct intel_crtc_state *crtc_state); From patchwork Fri Mar 7 10:52:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 14006228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E9D6C28B23 for ; Fri, 7 Mar 2025 10:53:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 086FB10EB5E; Fri, 7 Mar 2025 10:53:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ITI+Lk++"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id C426310EB5B; Fri, 7 Mar 2025 10:52:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741344779; x=1772880779; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bObsQ6aAFY8gkvRFg8ZyWy1zT1LYek6LWQVfSlCn94c=; b=ITI+Lk++znFIj4nnFnJQn4QXF6c514jwRTMIa9fWUQg+xQcqCdbabFa+ /nP0cfJ2ZDzL6DXS8UqAjP/R9tRij3xwHfC93WcHPd+TLQZEof184ky1d hZSJdeeR4uXtXGNYLNlXbPhQ8LKA9MpIhjIeB4v2T7vk71uFW498dQYTO SR096xhhPRX25cGjpAYyqLuSDC58ywc4wXUrN+8U3N5fFquRdGMr7g5M9 tTszrSaDzxLvjW2jeGinTd3wTc+dfBdWYGltBBwQAZ2EjlXGhWWlvQcl/ q73esIWNKMHTOykG911wFWgNR5MlFhYvCg9r8wm8NWIMuiYUn4nCXEMkl w==; X-CSE-ConnectionGUID: Zc0a77aSQdmwRIeqKrUF2Q== X-CSE-MsgGUID: h4pBBWCnQM64A4212V5u1g== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="42301655" X-IronPort-AV: E=Sophos;i="6.14,229,1736841600"; d="scan'208";a="42301655" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:59 -0800 X-CSE-ConnectionGUID: aPcgOHDRR6qFNVi9YLpUuQ== X-CSE-MsgGUID: UnjWfQEGT2mOpY22VMpcyQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123481601" Received: from mlehtone-mobl.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.100]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:52:58 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [RFC PATCH 07/11] drm/i915/psr: Add mechanism to notify PSR of DC5/6 enable disable Date: Fri, 7 Mar 2025 12:52:33 +0200 Message-ID: <20250307105237.2909849-8-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307105237.2909849-1-jouni.hogander@intel.com> References: <20250307105237.2909849-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We need to apply/remove workaround for underrun on idle PSR HW issue (Wa_16025596647) when DC5/6 is enabled/disabled. This patch implements mechanism to notify PSR about DC5/6 enable/disable and applies/removes the workaround using this notification. Bspec: 74115 Signed-off-by: Jouni Högander --- .../gpu/drm/i915/display/intel_display_core.h | 2 + drivers/gpu/drm/i915/display/intel_psr.c | 50 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 2 + 3 files changed, 54 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 7360ad39b1cc..b765a2ef9a6c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -573,6 +573,8 @@ struct intel_display { struct intel_vbt_data vbt; struct intel_dmc_wl wl; struct intel_wm wm; + + struct work_struct psr_dc5_dc6_wa_work; }; #endif /* __INTEL_DISPLAY_CORE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4b62d5832cbf..baf6a7110a55 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3718,6 +3718,56 @@ static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp psr1_apply_underrun_on_idle_wa_locked(intel_dp, dc5_dc6_blocked); } +static void psr_dc5_dc6_wa_work(struct work_struct *work) +{ + struct intel_display *display = container_of(work, typeof(*display), + psr_dc5_dc6_wa_work); + struct intel_encoder *encoder; + + for_each_intel_encoder_with_psr(display->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + mutex_lock(&intel_dp->psr.lock); + + if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled) + intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); + + mutex_unlock(&intel_dp->psr.lock); + } +} + +/** + * intel_psr_notify_dc5_dc6 - Notify PSR about enable/disable dc5/dc6 + * @display: intel atomic state + * + * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule + * psr_dc5_dc6_wa_work used for applying/removing the workaround. + */ +void intel_psr_notify_dc5_dc6(struct intel_display *display) +{ + if (DISPLAY_VER(display) != 20 && + !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) + return; + + schedule_work(&display->psr_dc5_dc6_wa_work); +} + +/** + * intel_psr_dc5_dc6_wa_init - Init work for underrun on idle PSR HW bug wa + * @display: intel atomic state + * + * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init + * psr_dc5_dc6_wa_work used for applying the workaround. + */ +void intel_psr_dc5_dc6_wa_init(struct intel_display *display) +{ + if (DISPLAY_VER(display) != 20 && + !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) + return; + + INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work); +} + /** * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe * @state: intel atomic state diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 273e70a50915..bfe368239bc2 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -62,6 +62,8 @@ void intel_psr_resume(struct intel_dp *intel_dp); bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state); void intel_psr_notify_pipe_change(struct intel_atomic_state *state, struct intel_crtc *crtc, bool enable); +void intel_psr_notify_dc5_dc6(struct intel_display *display); +void intel_psr_dc5_dc6_wa_init(struct intel_display *display); bool intel_psr_link_ok(struct intel_dp *intel_dp); void intel_psr_lock(const struct intel_crtc_state *crtc_state); From patchwork Fri Mar 7 10:52:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 14006227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55ECAC19F32 for ; Fri, 7 Mar 2025 10:53:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DCA4710EB5B; Fri, 7 Mar 2025 10:53:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="UbjpNfia"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5D61910EB58; Fri, 7 Mar 2025 10:53:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741344781; x=1772880781; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gAsKhk+4DnwMf8zLYpxWUeRJ+ncQ2N83ZUBfk+j8E5o=; b=UbjpNfiaKGL0jOJ2MEGfmkcn5IErhVElA0TS4hb+9R1ZEhtW/O/BPprB VTSbhsw0+dEfgb4EAAaYd9A0Hub7ce9s9wiTJ0OfWjmWyB4o3BwZ9ybrq TkLhrQ0R5xcNQ25TZl3vhQ1/1dEA9COi6EeD/jb4358ef6rw92ApfWFLF xa0X9lfNENr3UD8viwtGbdJ16F9mHyuzo3KglLN+3INSSMZs7+zxVhX6j q6ouL2RAog6drsiZ0FRTDOxUWuQwaXx9zhz16/oNrlMLdTc3U7qki8ynx KyqQIX+0/hKleDBrey3mkKrS8i5GlO0FTnO0AAAK1zvnPjSLIGAx91HJy Q==; X-CSE-ConnectionGUID: bNqDHVCcSUyvEt5ET1Dtkg== X-CSE-MsgGUID: oVwLVwTaTPO3GSZhltDvdQ== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="42301658" X-IronPort-AV: E=Sophos;i="6.14,229,1736841600"; d="scan'208";a="42301658" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:53:01 -0800 X-CSE-ConnectionGUID: HG5vFPrYQOKJI0A8i5Q8+A== X-CSE-MsgGUID: BKZPVF60SoK8eEvKr+kP5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123481609" Received: from mlehtone-mobl.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.100]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:53:00 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [RFC PATCH 08/11] drm/i915/psr: Add interface to notify PSR of vblank enable/disable Date: Fri, 7 Mar 2025 12:52:34 +0200 Message-ID: <20250307105237.2909849-9-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307105237.2909849-1-jouni.hogander@intel.com> References: <20250307105237.2909849-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To implement Wa_16025596647 we need to get notification of vblank interrupt enable/disable. Add new interface to PSR code for this notification. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 40 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 2 ++ 2 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index baf6a7110a55..afb9faed7784 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3820,6 +3820,46 @@ void intel_psr_notify_pipe_change(struct intel_atomic_state *state, } } +/** + * intel_psr_notify_vblank_enable_disable - Notify PSR about enable/disable of vblank + * @display: intel display struct + * @enable: enable/disable + * + * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply + * remove the workaround when vblank is getting enabled/disabled + */ +void intel_psr_notify_vblank_enable_disable(struct intel_display *display, + bool enable) +{ + struct intel_encoder *encoder; + + for_each_intel_encoder_with_psr(display->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + mutex_lock(&intel_dp->psr.lock); + if (intel_dp->psr.panel_replay_enabled) { + mutex_unlock(&intel_dp->psr.lock); + break; + } + + if (intel_dp->psr.enabled) + intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); + + mutex_unlock(&intel_dp->psr.lock); + return; + } + + /* + * NOTE: intel_display_power_set_target_dc_state is used + * only by PSR * code for DC3CO handling. DC3CO target + * state is currently disabled in * PSR code. If DC3CO + * is taken into use we need take that into account here + * as well. + */ + intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE : + DC_STATE_EN_UPTO_DC6); +} + static void psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) { diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index bfe368239bc2..a914b7ee3756 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -64,6 +64,8 @@ void intel_psr_notify_pipe_change(struct intel_atomic_state *state, struct intel_crtc *crtc, bool enable); void intel_psr_notify_dc5_dc6(struct intel_display *display); void intel_psr_dc5_dc6_wa_init(struct intel_display *display); +void intel_psr_notify_vblank_enable_disable(struct intel_display *display, + bool enable); bool intel_psr_link_ok(struct intel_dp *intel_dp); void intel_psr_lock(const struct intel_crtc_state *crtc_state); From patchwork Fri Mar 7 10:52:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 14006229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9685CC19F32 for ; Fri, 7 Mar 2025 10:53:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 324C710EB5D; Fri, 7 Mar 2025 10:53:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="BEUp9KUF"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id F417510EB5D; Fri, 7 Mar 2025 10:53:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741344782; x=1772880782; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UzZODJcMF0F3R0AdBILaYwLWWeSwbRbv4NR6zE2TEpM=; b=BEUp9KUFB5yny3vIswm79WB/e5eHeYU7gPnxQuBCvbGL33ktsRidRw3Z oWyJ5IvcqWdx+fmcn06LbBxiQ7A8pcgW+3zwDyLulMkjBGDFMXrXrUvnz d0iFah+HNwoc4FvcJ7aBFg8bWRju1yg13M3PopZjCqIZv6MjSJym+XDj5 235ejrX5xv/8MAT530Qhy/kd8CabIfeGmt8pk71KU7F7Sfmqu8QCdDzet 4pLzqDc/R3+3qpd0FQGSIwIzT3NhGZh1u45LIds+/+3+DwRdwtfjCTkg8 49Cu8zcn46n74a5Gt4VWsM21ECi3ypEfpwjMVUgDAwTfDhcTX0OnHFkKO w==; X-CSE-ConnectionGUID: plIvvuleQI2+PChuQYnnxQ== X-CSE-MsgGUID: PCUtpIJUSaeg/VVdH30pyA== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="42301659" X-IronPort-AV: E=Sophos;i="6.14,229,1736841600"; d="scan'208";a="42301659" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:53:02 -0800 X-CSE-ConnectionGUID: KbX3TEkpQv+yLRoYqE9ewA== X-CSE-MsgGUID: IrkzrBYlRv2i6wJMyaRtGw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123481622" Received: from mlehtone-mobl.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.100]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:53:01 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [RFC PATCH 09/11] drm/i915/psr: Apply underrun on PSR idle workaround Date: Fri, 7 Mar 2025 12:52:35 +0200 Message-ID: <20250307105237.2909849-10-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307105237.2909849-1-jouni.hogander@intel.com> References: <20250307105237.2909849-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This patch is applying workaround for underrun on idle PSR HW issue (Wa_16025596647) when PSR is getting enabled. It uses vblank enable/disable status, DC5/6 enabled disabled and enabled pipes count information made available. This patch is also adding calls to dc5/dc6, vblank enable/disable and pipe enable/disable notification functions as needed. intel_psr_needs_block_dc_vblank is modified to get vblank enable/disable notification on PSR capable system. Bspec: 74151 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_display.c | 4 + .../drm/i915/display/intel_display_driver.c | 3 + .../gpu/drm/i915/display/intel_display_irq.c | 9 +- .../i915/display/intel_display_power_well.c | 4 + drivers/gpu/drm/i915/display/intel_psr.c | 101 +++++++++++------- 5 files changed, 74 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f7cb38145e9d..109907d93cf8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6656,6 +6656,8 @@ static void intel_enable_crtc(struct intel_atomic_state *state, intel_crtc_update_active_timings(pipe_crtc_state, false); } + intel_psr_notify_pipe_change(state, crtc, true); + display->funcs.display->crtc_enable(state, crtc); /* vblanks work again, re-enable pipe CRC. */ @@ -6775,6 +6777,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state, intel_crtc_joined_pipe_mask(old_crtc_state)) intel_crtc_disable_pipe_crc(pipe_crtc); + intel_psr_notify_pipe_change(state, crtc, false); + display->funcs.display->crtc_disable(state, crtc); for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 31740a677dd8..b4c989bbac93 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -54,6 +54,7 @@ #include "intel_plane_initial.h" #include "intel_pmdemand.h" #include "intel_pps.h" +#include "intel_psr.h" #include "intel_quirks.h" #include "intel_vga.h" #include "intel_wm.h" @@ -226,6 +227,8 @@ int intel_display_driver_probe_noirq(struct intel_display *display) if (ret) goto cleanup_bios; + intel_psr_dc5_dc6_wa_init(display); + /* FIXME: completely on the wrong abstraction layer */ ret = intel_power_domains_init(display); if (ret < 0) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index aa23bb817805..62fbdcbb4a12 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1728,14 +1728,7 @@ static void intel_display_vblank_dc_work(struct work_struct *work) container_of(work, typeof(*display), irq.vblank_dc_work); int vblank_wa_num_pipes = READ_ONCE(display->irq.vblank_wa_num_pipes); - /* - * NOTE: intel_display_power_set_target_dc_state is used only by PSR - * code for DC3CO handling. DC3CO target state is currently disabled in - * PSR code. If DC3CO is taken into use we need take that into account - * here as well. - */ - intel_display_power_set_target_dc_state(display, vblank_wa_num_pipes ? DC_STATE_DISABLE : - DC_STATE_EN_UPTO_DC6); + intel_psr_notify_vblank_enable_disable(display, vblank_wa_num_pipes); } int bdw_enable_vblank(struct drm_crtc *_crtc) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 8ec87ffd87d2..510f97341893 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -24,6 +24,7 @@ #include "intel_hotplug.h" #include "intel_pcode.h" #include "intel_pps.h" +#include "intel_psr.h" #include "intel_tc.h" #include "intel_vga.h" #include "skl_watermark.h" @@ -762,6 +763,9 @@ void gen9_set_dc_state(struct intel_display *display, u32 state) state & ~power_domains->allowed_dc_mask)) state &= power_domains->allowed_dc_mask; + if (!power_domains->initializing) + intel_psr_notify_dc5_dc6(display); + val = intel_de_read(display, DC_STATE_EN); mask = gen9_dc_mask(display); drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index afb9faed7784..2782b84b0d12 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -908,6 +908,41 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) return idle_frames; } +/* Wa_16025596647 */ +static void psr1_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp, + bool dc5_dc6_blocked) +{ + struct intel_display *display = to_intel_display(intel_dp); + u32 val; + + if (dc5_dc6_blocked) + val = DMC_EVT_CTL_ENABLE | DMC_EVT_CTL_RECURRING | + REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, + DMC_EVT_CTL_TYPE_EDGE_0_1) | + REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, + DMC_EVT_CTL_EVENT_ID_VBLANK_A); + else + val = REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, + DMC_EVT_CTL_EVENT_ID_FALSE) | + REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, + DMC_EVT_CTL_TYPE_EDGE_0_1); + + intel_de_write(display, MTL_PIPEDMC_EVT_CTL_4(intel_dp->psr.pipe), + val); +} + +static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + u32 current_dc_state = intel_display_power_get_current_dc_state(display); + struct drm_vblank_crtc *vblank = &display->drm->vblank[intel_dp->psr.pipe]; + + return (current_dc_state != DC_STATE_EN_UPTO_DC5 && + current_dc_state != DC_STATE_EN_UPTO_DC6) || + intel_dp->psr.active_non_psr_pipes || + READ_ONCE(vblank->enabled); +} + static void hsw_activate_psr1(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); @@ -937,6 +972,12 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); + + /* Wa_16025596647 */ + if ((DISPLAY_VER(display) == 20 || + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + is_dc5_dc6_blocked(intel_dp)) + psr1_apply_underrun_on_idle_wa_locked(intel_dp, true); } static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) @@ -1019,8 +1060,16 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) enum transcoder cpu_transcoder = intel_dp->psr.transcoder; u32 val = EDP_PSR2_ENABLE; u32 psr_val = 0; + u8 idle_frames; - val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); + /* Wa_16025596647 */ + if ((DISPLAY_VER(display) == 20 || + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + is_dc5_dc6_blocked(intel_dp)) + idle_frames = 0; + else + idle_frames = psr_compute_idle_frames(intel_dp); + val |= EDP_PSR2_IDLE_FRAMES(idle_frames); if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv)) val |= EDP_SU_TRACK_ENABLE; @@ -2101,6 +2150,8 @@ static void intel_psr_exit(struct intel_dp *intel_dp) drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE)); } else { + psr1_apply_underrun_on_idle_wa_locked(intel_dp, false); + val = intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), EDP_PSR_ENABLE, 0); @@ -2312,6 +2363,7 @@ void intel_psr_resume(struct intel_dp *intel_dp) bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_display *display = to_intel_display(crtc_state); struct intel_encoder *encoder; for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) { @@ -2322,8 +2374,15 @@ bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state) intel_dp = enc_to_intel_dp(encoder); - if (intel_dp_is_edp(intel_dp) && - CAN_PANEL_REPLAY(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) + continue; + + if (CAN_PANEL_REPLAY(intel_dp)) + return true; + + if ((DISPLAY_VER(display) == 20 || + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + CAN_PSR(intel_dp)) return true; } @@ -3665,42 +3724,6 @@ void intel_psr_unlock(const struct intel_crtc_state *crtc_state) } } -/* Wa_16025596647 */ -static void psr1_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp, - bool dc5_dc6_blocked) -{ - struct intel_display *display = to_intel_display(intel_dp); - u32 val; - - if (dc5_dc6_blocked) - val = DMC_EVT_CTL_ENABLE | DMC_EVT_CTL_RECURRING | - REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, - DMC_EVT_CTL_TYPE_EDGE_0_1) | - REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, - DMC_EVT_CTL_EVENT_ID_VBLANK_A); - else - val = REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, - DMC_EVT_CTL_EVENT_ID_FALSE) | - REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, - DMC_EVT_CTL_TYPE_EDGE_0_1); - - intel_de_write(display, MTL_PIPEDMC_EVT_CTL_4(intel_dp->psr.pipe), - val); -} - -/* Wa_16025596647 */ -static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp) -{ - struct intel_display *display = to_intel_display(intel_dp); - u32 current_dc_state = intel_display_power_get_current_dc_state(display); - struct drm_vblank_crtc *vblank = &display->drm->vblank[intel_dp->psr.pipe]; - - return (current_dc_state != DC_STATE_EN_UPTO_DC5 && - current_dc_state != DC_STATE_EN_UPTO_DC6) || - intel_dp->psr.active_non_psr_pipes || - READ_ONCE(vblank->enabled); -} - /* Wa_16025596647 */ static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp) { From patchwork Fri Mar 7 10:52:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 14006230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EA3FC28B23 for ; Fri, 7 Mar 2025 10:53:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DE2DA10EB58; Fri, 7 Mar 2025 10:53:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MCOTaicd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 88F7410EB5F; Fri, 7 Mar 2025 10:53:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741344784; x=1772880784; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gt+xl1iyRAaHoSJ+W2dy/uvvWiEhefMaEUNHxo6BEFI=; b=MCOTaicdZtNZnTyhLBLGPqxjV0x6XduJWjgyEXpIQc2yHm3oNRpLurS/ JCTMWCvDo4Re10WtPoW3qzGw2177PmUBp1FC78OYXPeii2fNDv9P+8jct J04KuD4FL5o3VATjthraBNq7wf4KDsfb2Qhde4gtZ7t4X4vbUCc1q1lcW sg0lE5cmfkE/lEZZaWZi3fGF9AMHBfNBBdcuQJt7WeceriHczp6Cv7erj uZFvzwvcXIhyVgQOz2j18S5kFi53L6kPIvJ4ywf5RcoAgIUwRawdJAmVG uz55jSG34aZS2FxcRM0Ysw94nsYv9Gg6lUOwnNerSM2gTgHFRvEDmJgP/ g==; X-CSE-ConnectionGUID: JdBSdO3zRAa296FiAzWIeA== X-CSE-MsgGUID: /Wi1xgUeQTO/VqaZOdmWCw== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="42301660" X-IronPort-AV: E=Sophos;i="6.14,229,1736841600"; d="scan'208";a="42301660" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:53:04 -0800 X-CSE-ConnectionGUID: 9736kw6YRWO1Q/DWuuz3sA== X-CSE-MsgGUID: ComR16AKSPiuqwakGFW/+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123481636" Received: from mlehtone-mobl.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.100]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:53:03 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [RFC PATCH 10/11] drm/i915/display: Rename intel_psr_needs_block_dc_vblank Date: Fri, 7 Mar 2025 12:52:36 +0200 Message-ID: <20250307105237.2909849-11-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307105237.2909849-1-jouni.hogander@intel.com> References: <20250307105237.2909849-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Scope of intel_psr_needs_block_dc_vblank has changed now. Rename it as intel_psr_needs_vblank_notification. Also rename intel_crtc::block_dc_for_vblank as intel_crtc:vblank_psr_notify Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_crtc.c | 4 ++-- drivers/gpu/drm/i915/display/intel_display_irq.c | 4 ++-- drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 8 +++++--- drivers/gpu/drm/i915/display/intel_psr.h | 2 +- 5 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 5b2603ef2ff7..bdf30ab96396 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -124,7 +124,7 @@ void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - crtc->block_dc_for_vblank = intel_psr_needs_block_dc_vblank(crtc_state); + crtc->vblank_psr_notify = intel_psr_needs_vblank_notification(crtc_state); assert_vblank_disabled(&crtc->base); drm_crtc_set_max_vblank_count(&crtc->base, @@ -154,7 +154,7 @@ void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state) drm_crtc_vblank_off(&crtc->base); assert_vblank_disabled(&crtc->base); - crtc->block_dc_for_vblank = false; + crtc->vblank_psr_notify = false; flush_work(&display->irq.vblank_dc_work); } diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 62fbdcbb4a12..833f8227da80 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1742,7 +1742,7 @@ int bdw_enable_vblank(struct drm_crtc *_crtc) if (gen11_dsi_configure_te(crtc, true)) return 0; - if (crtc->block_dc_for_vblank && display->irq.vblank_wa_num_pipes++ == 0) + if (crtc->vblank_psr_notify && display->irq.vblank_wa_num_pipes++ == 0) schedule_work(&display->irq.vblank_dc_work); spin_lock_irqsave(&dev_priv->irq_lock, irqflags); @@ -1773,7 +1773,7 @@ void bdw_disable_vblank(struct drm_crtc *_crtc) bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); - if (crtc->block_dc_for_vblank && --display->irq.vblank_wa_num_pipes == 0) + if (crtc->vblank_psr_notify && --display->irq.vblank_wa_num_pipes == 0) schedule_work(&display->irq.vblank_dc_work); } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 3d203a2003f1..4f3fdfacbc1b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1440,7 +1440,7 @@ struct intel_crtc { struct intel_pipe_crc pipe_crc; #endif - bool block_dc_for_vblank; + bool vblank_psr_notify; }; struct intel_plane_error { diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 2782b84b0d12..74aa7ba34fda 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2352,15 +2352,17 @@ void intel_psr_resume(struct intel_dp *intel_dp) } /** - * intel_psr_needs_block_dc_vblank - Check if block dc entry is needed + * intel_psr_needs_vblank_notification - Check if PSR need vblank enable/disable + * notification. * @crtc_state: CRTC status * * We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't * prevent it in case of Panel Replay. Panel Replay switches main link off on * DC entry. This means vblank interrupts are not fired and is a problem if - * user-space is polling for vblank events. + * user-space is polling for vblank events. Also Wa_16025596647 needs + * information when vblank is enabled/disabled. */ -bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state) +bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_display *display = to_intel_display(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index a914b7ee3756..c61384bb7382 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -59,7 +59,7 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state); void intel_psr_pause(struct intel_dp *intel_dp); void intel_psr_resume(struct intel_dp *intel_dp); -bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state); +bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state); void intel_psr_notify_pipe_change(struct intel_atomic_state *state, struct intel_crtc *crtc, bool enable); void intel_psr_notify_dc5_dc6(struct intel_display *display); From patchwork Fri Mar 7 10:52:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 14006231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A9243C19F32 for ; Fri, 7 Mar 2025 10:53:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3CFEE10EB64; Fri, 7 Mar 2025 10:53:08 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="J9KygYWQ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 23C8010EB63; Fri, 7 Mar 2025 10:53:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741344786; x=1772880786; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9A5zwa0ltRtuvzmmkeCiQGSHh72bO1vRCvu3xlIxjcQ=; b=J9KygYWQIcle6flAp4mpP0IV6mtZr624rLVlsk7dtsb9hLiMS1Bn47nS nRIlGpyK7ETq3wYaZ/7mHsAVEdm+5MXdB8bdfy2fgF1hpt+SDB1LAN+zt gKsXx9UJKsU0NDRVlqphwZdqCA+0/t7tHCA2UQxm8CF2kUjIIUq5hlYn1 zIAezFEdIdmsToOAKri1EwA7hT853XQrSquKqJ6JM+6+VKEg9LV6uHWhs 6tOIp7FEllvCdC1bOEMLjaDoTICDqoosBQ68Y32fVzgupDslf4IGNFTGp F04Imb0QWBZuAhWbD59HDOdDWKGX2UoX4H1l4NvwNpff7Rf/xOt/GQSET g==; X-CSE-ConnectionGUID: drBXPyoiR62hdctPSZ9fnQ== X-CSE-MsgGUID: sQ/Kvb55Tdq0SPFpOWqFLQ== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="42301662" X-IronPort-AV: E=Sophos;i="6.14,229,1736841600"; d="scan'208";a="42301662" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:53:05 -0800 X-CSE-ConnectionGUID: 6u3mnE7KTAqUyi3c+AggAg== X-CSE-MsgGUID: e07CnaLMQ66j1JA/mCKsgw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123481649" Received: from mlehtone-mobl.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.100]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2025 02:53:04 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [RFC PATCH 11/11] drm/i915/display: Rename vblank DC workaround functions and variables Date: Fri, 7 Mar 2025 12:52:37 +0200 Message-ID: <20250307105237.2909849-12-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307105237.2909849-1-jouni.hogander@intel.com> References: <20250307105237.2909849-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We have extended using vblank DC workaround mechanism for Wa_16025596647. Rename related functions and variables: vblank_wa_num_pipes -> vblank_enable_count vblank_dc_work -> vblank_notify_work intel_display_vblank_dc_work -> intel_display_vblank_notify_work Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_crtc.c | 2 +- .../gpu/drm/i915/display/intel_display_core.h | 4 ++-- .../gpu/drm/i915/display/intel_display_irq.c | 20 +++++++++---------- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index bdf30ab96396..537859630363 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -156,7 +156,7 @@ void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state) crtc->vblank_psr_notify = false; - flush_work(&display->irq.vblank_dc_work); + flush_work(&display->irq.vblank_notify_work); } struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc) diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index b765a2ef9a6c..c93cab1266c5 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -464,9 +464,9 @@ struct intel_display { /* For i915gm/i945gm vblank irq workaround */ u8 vblank_enabled; - int vblank_wa_num_pipes; + int vblank_enable_count; - struct work_struct vblank_dc_work; + struct work_struct vblank_notify_work; u32 de_irq_mask[I915_MAX_PIPES]; u32 pipestat_irq_mask[I915_MAX_PIPES]; diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 833f8227da80..22942edf5ff0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1722,13 +1722,13 @@ static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, return true; } -static void intel_display_vblank_dc_work(struct work_struct *work) +static void intel_display_vblank_notify_work(struct work_struct *work) { struct intel_display *display = - container_of(work, typeof(*display), irq.vblank_dc_work); - int vblank_wa_num_pipes = READ_ONCE(display->irq.vblank_wa_num_pipes); + container_of(work, typeof(*display), irq.vblank_notify_work); + int vblank_enable_count = READ_ONCE(display->irq.vblank_enable_count); - intel_psr_notify_vblank_enable_disable(display, vblank_wa_num_pipes); + intel_psr_notify_vblank_enable_disable(display, vblank_enable_count); } int bdw_enable_vblank(struct drm_crtc *_crtc) @@ -1742,8 +1742,8 @@ int bdw_enable_vblank(struct drm_crtc *_crtc) if (gen11_dsi_configure_te(crtc, true)) return 0; - if (crtc->vblank_psr_notify && display->irq.vblank_wa_num_pipes++ == 0) - schedule_work(&display->irq.vblank_dc_work); + if (crtc->vblank_psr_notify && display->irq.vblank_enable_count++ == 0) + schedule_work(&display->irq.vblank_notify_work); spin_lock_irqsave(&dev_priv->irq_lock, irqflags); bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); @@ -1773,8 +1773,8 @@ void bdw_disable_vblank(struct drm_crtc *_crtc) bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); - if (crtc->vblank_psr_notify && --display->irq.vblank_wa_num_pipes == 0) - schedule_work(&display->irq.vblank_dc_work); + if (crtc->vblank_psr_notify && --display->irq.vblank_enable_count == 0) + schedule_work(&display->irq.vblank_notify_work); } static u32 vlv_dpinvgtt_pipe_fault_mask(enum pipe pipe) @@ -2345,6 +2345,6 @@ void intel_display_irq_init(struct drm_i915_private *i915) intel_hotplug_irq_init(i915); - INIT_WORK(&i915->display.irq.vblank_dc_work, - intel_display_vblank_dc_work); + INIT_WORK(&i915->display.irq.vblank_notify_work, + intel_display_vblank_notify_work); }