From patchwork Fri Mar 7 23:37:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 14007282 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A433B212D8D; Fri, 7 Mar 2025 23:37:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741390674; cv=none; b=qTTiLaCf8aIFotJkxZHMBJfdQZuMSk33d9DKKPAPOphm0U0flVz/zfLhfpG3GC7DxlNP7z60BvsY0g3nOzahcLF5Hxhf+DDzLNlZOoHQnaNXrci7zXiS+TFKIl1/w76QAHqIvrrKC003iRIfZNsyL+35lN4E1k5rXSp2ez+X7/k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741390674; c=relaxed/simple; bh=ua0QgEy0dtgEEi4JLJEBT5g3dBO7iHT7Cgd7aa1B+Bg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PdPPKOFj0ykGB68CsjLcD6brmfTDbTP+hCI44O/dzRNJwhFD7CoF7htEhBRNuImVsS2fNFer44W9mVeVIo3fvJZFA86yNJloFRcUtw08nd8vx2ZACcTUE4HdwCN/TEFkstnOKGnznnCXAg7NBosrIRmZqbDkhrImHvoml3pcBPI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Xa4liii3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Xa4liii3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C2E4DC4CED1; Fri, 7 Mar 2025 23:37:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741390674; bh=ua0QgEy0dtgEEi4JLJEBT5g3dBO7iHT7Cgd7aa1B+Bg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Xa4liii3Xc5XxFFQL/XL0QZzGnmQmkhiGfhADFOcOCnT1EjvZ1UHgXBePJR6QYXV3 vRSyXotvvUma0enW3P3Hz5UchElelf+MHveAv49uy8ZtnWSa7B2pTGGtQufFMNwOhu S7JMWx9w41is4jaJncM6XbSpZHKDQHIRFNU/i3pmhHyAyEjFuh/ZXoyq5qzZALLoSF 2DKkZ24v6T2wlcVkoQeFyeHPdaq+MeUc8kAlwNRs/WpRBskBiUBzhyzGjRa8yJHX+2 VbAmbRdLKNgDsWHmQ1fDIwPNcxqQY1vUplr99mv3a4Q26RKQBzX8gpZ1jxKEs7stBY 2ld1PzjsN/poQ== From: Bjorn Helgaas To: Frank Li Cc: Rob Herring , Saravana Kannan , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Niklas Cassel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Bjorn Helgaas Subject: [PATCH 1/4] PCI: dwc: Move cfg0 setup to dw_pcie_cfg0_setup() Date: Fri, 7 Mar 2025 17:37:41 -0600 Message-Id: <20250307233744.440476-2-helgaas@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250307233744.440476-1-helgaas@kernel.org> References: <20250307233744.440476-1-helgaas@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bjorn Helgaas Move pp->cfg0 setup to dw_pcie_cfg0_setup(). No functional change intended. --- .../pci/controller/dwc/pcie-designware-host.c | 34 +++++++++++++------ 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 1206b26bff3f..de2f2dcf5c40 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -418,22 +418,12 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) } } -int dw_pcie_host_init(struct dw_pcie_rp *pp) +static int dw_pcie_cfg0_setup(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct device *dev = pci->dev; - struct device_node *np = dev->of_node; struct platform_device *pdev = to_platform_device(dev); - struct resource_entry *win; - struct pci_host_bridge *bridge; struct resource *res; - int ret; - - raw_spin_lock_init(&pp->lock); - - ret = dw_pcie_get_resources(pci); - if (ret) - return ret; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); if (!res) { @@ -448,6 +438,28 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (IS_ERR(pp->va_cfg0_base)) return PTR_ERR(pp->va_cfg0_base); + return 0; +} + +int dw_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + struct device_node *np = dev->of_node; + struct resource_entry *win; + struct pci_host_bridge *bridge; + int ret; + + raw_spin_lock_init(&pp->lock); + + ret = dw_pcie_get_resources(pci); + if (ret) + return ret; + + ret = dw_pcie_cfg0_setup(pp); + if (ret) + return ret; + bridge = devm_pci_alloc_host_bridge(dev, 0); if (!bridge) return -ENOMEM; From patchwork Fri Mar 7 23:37:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 14007283 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 909561925AC; Fri, 7 Mar 2025 23:37:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741390679; cv=none; b=IZva8KIiVWbaxbvpEq1OGo0riAFkDMUEh4I29h92FXZtruKDjnNXfMnyp7eVTrJsblm0G0h+JKZNtaM2fobeDI+vYMe1IBbfemP0FlC4x6YgUWXEuIQBPCPL3hETLnpPhDZOzPfixjkZ/C339jbxkAY50zRs+/q/iGzS6ZOU0aA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741390679; c=relaxed/simple; bh=/Vd5KWvSiGu6/wCPX+6AfloWDVGSa9tpnOhgexIbXEQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pxy7EWaWbZB5Yxw8oBd7Lw5/gxBrVAqEQL8XUjDfS3VUAEEOplJMm+JUkX7/q4cafu/q6/q4hZRZPDJ8yJemfAON4UHLdB6l5J6I/9WsUHA/OmX4s5KAD00TzwsrMdo8lcW0GOUm6SfcGqTY4riekX2g3z3+KtcWzG89p0p63qU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Acw2g1gV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Acw2g1gV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E84F2C4CED1; Fri, 7 Mar 2025 23:37:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741390678; bh=/Vd5KWvSiGu6/wCPX+6AfloWDVGSa9tpnOhgexIbXEQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Acw2g1gVGlLFYF0SltDeaIZQ9KwE6vcOMVM6luvqFnf40847eeFswIpbIcKP7nYmK kLfy9MxLzQTzSH6s3Z89HAKeYyAkRWntv/8ABqAaA448ttme/dLea5kZsaYAmqFFP6 ewMoOpEu5OkfDAbLuh5EASyV3tIAxSSUSiaBKwXNsmbTY+PqEmSmd/X16B+bxvRwXa 9F/AJYwbCjcu98r6x2PN4GM8JR6ll0mddTmGzUA4jduF9Jzp4gcmcMbI/9IvFdElM6 jH8I65HYqEKV1VKtGUdzKPSm++TdZHO7sRTdZkbXMfSAhq3YKLvpUe7U34881mIz0B r8S0mvulLLNqA== From: Bjorn Helgaas To: Frank Li Cc: Rob Herring , Saravana Kannan , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Niklas Cassel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Bjorn Helgaas Subject: [PATCH 2/4] PCI: dwc: Delay cfg0 setup until after discovering bridge windows Date: Fri, 7 Mar 2025 17:37:42 -0600 Message-Id: <20250307233744.440476-3-helgaas@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250307233744.440476-1-helgaas@kernel.org> References: <20250307233744.440476-1-helgaas@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bjorn Helgaas devm_pci_alloc_host_bridge() reads host bridge windows and any translation offsets. Some .cpu_addr_fixup() implementations depend on the window offset, e.g., imx_pcie_cpu_addr_fixup() uses the offset of the first bridge window. --- drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index de2f2dcf5c40..b9eaba157dae 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -456,14 +456,14 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (ret) return ret; - ret = dw_pcie_cfg0_setup(pp); - if (ret) - return ret; - bridge = devm_pci_alloc_host_bridge(dev, 0); if (!bridge) return -ENOMEM; + ret = dw_pcie_cfg0_setup(pp); + if (ret) + return ret; + pp->bridge = bridge; /* Get the I/O range from DT */ From patchwork Fri Mar 7 23:37:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 14007284 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A2A62147EB; Fri, 7 Mar 2025 23:38:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741390683; cv=none; b=vA+iMho3czxiV0lRROUpYUUyXCmqVI/1aluRjQFmAfnHU6J3Cfog8aBoGvM+oPs5BeU6akhis+3T42vYxAedAOmVKkqc6MW3O95Z+w25FSkQl9zCv1b6pNd2jfYEzAnUY0BNziy9mTIFrQdxYyIYqDJUerZ2M3q5usatf7qXD8M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741390683; c=relaxed/simple; bh=9huYHohH+gOJUkoeThHaODlEFocAowbh3DJVYqegdA4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ijtJhUII+wIsFobmwHAtr75jtN//UiKtqTF0yiUlwA0A6Z3+1l9Cq3A/W8UWggNdllaNuHn7HEznZ9cb4kf0z4Xvyi0q5VNUrtncFKyWGz1VTM2UzT8vVxHl77CrhwonZtbnF0fAfaBEmyE6FYyI3sR69Zfl7oC7CeRarPlzDC0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=exc99kmd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="exc99kmd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A0311C4CEEE; Fri, 7 Mar 2025 23:38:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741390682; bh=9huYHohH+gOJUkoeThHaODlEFocAowbh3DJVYqegdA4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=exc99kmdGHpYV6kL6OhjqqdbMWYSyTNNn80GYi2Uc+VGV55ZsasQb1TE6cGi5R6to 38jeJdJmaoQrR9WMNt9kfO/wzRwJ8vSP1XRtHW22eTs9DdavO/Ye5cXvtEY5hYsMXZ PbTWPMGSCekt20ls3uamd0Xi2PLFd/LjElBtXUnHmepsGBFqztBbEDGcurcL+6iGUM 0PG9WS0ohUvDp11N5TeD1pnusirSM1jZiMfVNEqF41rVNMqttdhmHsv5IT8DusD+Vs gm9ePcCelLJErYpjQlWNp8P3gqtxbqrVukcyKMtvW5n9Rur+rjzM8YTbUUq51t0R6p lxFlFr0Tfm6ag== From: Bjorn Helgaas To: Frank Li Cc: Rob Herring , Saravana Kannan , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Niklas Cassel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Bjorn Helgaas Subject: [PATCH 3/4] PCI: dwc: Look up 'config' address Date: Fri, 7 Mar 2025 17:37:43 -0600 Message-Id: <20250307233744.440476-4-helgaas@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250307233744.440476-1-helgaas@kernel.org> References: <20250307233744.440476-1-helgaas@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bjorn Helgaas Set pp->parent_bus_offset based on the parent bus address from the "config" reg entry if it exists. .cpu_addr_fixup(res->start) (if implemented) should return the parent bus address corresponding to res->start. Sets pp->parent_bus_offset, but doesn't use it, so no functional change intended yet. --- .../pci/controller/dwc/pcie-designware-host.c | 42 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 43 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index b9eaba157dae..e22f650ada5a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -423,7 +423,11 @@ static int dw_pcie_cfg0_setup(struct dw_pcie_rp *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct device *dev = pci->dev; struct platform_device *pdev = to_platform_device(dev); + struct device_node *np = dev->of_node; struct resource *res; + int index; + u64 reg_addr, fixup_addr; + u64 (*fixup)(struct dw_pcie *pcie, u64 cpu_addr); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); if (!res) { @@ -434,6 +438,44 @@ static int dw_pcie_cfg0_setup(struct dw_pcie_rp *pp) pp->cfg0_size = resource_size(res); pp->cfg0_base = res->start; + /* [mem 0x7ff00000-] in example */ + dev_info(dev, "%pR config CPU physical\n", res); + + /* Look up "config" address on parent bus */ + reg_addr = 0; + index = of_property_match_string(np, "reg-names", "config"); + if (index >= 0) { + of_property_read_reg(np, index, ®_addr, NULL); + /* [ia 0x8ff00000-] in example */ + dev_info(dev, "%#010llx config reg[%d] parent bus addr\n", + reg_addr, index); + } else { + reg_addr = res->start; + dev_warn(dev, "%#010llx assumed parent bus addr (no config reg-names entry)\n", + reg_addr); + } + + fixup = pci->ops->cpu_addr_fixup; + if (fixup) { + fixup_addr = fixup(pci, res->start); + dev_info(dev, "%#010llx result of %ps(%#010llx)\n", + fixup_addr, fixup, res->start); + if (reg_addr == fixup_addr) { + dev_info(dev, "%#010llx config reg[%d] == %#010llx; %ps is redundant\n", + reg_addr, index, fixup_addr, fixup); + } else { + dev_warn(dev, "%#010llx config reg[%d] != %#010llx fixed up addr; DT is broken\n", + reg_addr, index, fixup_addr); + reg_addr = fixup_addr; + } + } + + /* 0x7ff00000 - 0x8ff00000 == 0xf0000000 */ + pp->parent_bus_offset = res->start - reg_addr; + dev_info(dev, "%#010llx config parent bus offset\n", + pp->parent_bus_offset); + + pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pp->va_cfg0_base)) return PTR_ERR(pp->va_cfg0_base); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ac23604c829f..eeca38ec3a2b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -362,6 +362,7 @@ struct dw_pcie_rp { u64 cfg0_base; void __iomem *va_cfg0_base; u32 cfg0_size; + u64 parent_bus_offset; resource_size_t io_base; phys_addr_t io_bus_addr; u32 io_size; From patchwork Fri Mar 7 23:37:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 14007285 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AEDE21504D; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CTVoSv90" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 57CD0C4CEE9; Fri, 7 Mar 2025 23:38:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741390684; bh=awyxVGLYLrPGk2ph0vC9xWww4UwkrrLl5cXRfJqJlA0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CTVoSv901qPSH0kq0SRi45h38A2I+kzNId6N7kN8mUDSfb6d97vw8m4klIvm5tqeU GAAPZ5h8bTAR47cLw04L8I7NjH5O/CDqd25IsGFixaVCi5ZEhO4yXYmreSFZzmYMrK XaHNENqH+Q/S6PlDJq0DxFh0/6b+0WoOEf2ZXcZhM2du4yDrJASDBW4+8oX8QNwjdN p54qwFQwhzKPPTNYZw6cjZYMCH1dPSzf3d1OomHr3NmfONYvc+Yfozq1yDf9csiFzw uL8QR7UnDcubB4ogUeQwavpsm9bsM3+0DxVajnJXq4IXlJIuaAT4Ry1NxjECm27jxA wcuiivr40Jl9w== From: Bjorn Helgaas To: Frank Li Cc: Rob Herring , Saravana Kannan , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Niklas Cassel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Bjorn Helgaas Subject: [PATCH 4/4] PCI: dwc: Use parent_bus_offset Date: Fri, 7 Mar 2025 17:37:44 -0600 Message-Id: <20250307233744.440476-5-helgaas@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250307233744.440476-1-helgaas@kernel.org> References: <20250307233744.440476-1-helgaas@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bjorn Helgaas We know the parent_bus_offset, either computed from a DT reg property (the offset is the CPU physical addr - the 'config' address on the parent bus) or from a .cpu_addr_fixup() (which may have used a host bridge window offset). Apply that parent_bus_offset instead of calling .cpu_addr_fixup() again. This assumes that all intermediate addresses are at the same offset from the CPU physical addresses. --- drivers/pci/controller/dwc/pcie-designware-host.c | 12 ++++++------ drivers/pci/controller/dwc/pcie-designware.c | 3 --- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index e22f650ada5a..3378f905b3bd 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -670,7 +670,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, type = PCIE_ATU_TYPE_CFG1; atu.type = type; - atu.parent_bus_addr = pp->cfg0_base; + atu.parent_bus_addr = pp->cfg0_base - pp->parent_bus_offset; atu.pci_addr = busdev; atu.size = pp->cfg0_size; @@ -695,7 +695,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, if (pp->cfg0_io_shared) { atu.type = PCIE_ATU_TYPE_IO; - atu.parent_bus_addr = pp->io_base; + atu.parent_bus_addr = pp->io_base - pp->parent_bus_offset; atu.pci_addr = pp->io_bus_addr; atu.size = pp->io_size; @@ -721,7 +721,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, if (pp->cfg0_io_shared) { atu.type = PCIE_ATU_TYPE_IO; - atu.parent_bus_addr = pp->io_base; + atu.parent_bus_addr = pp->io_base - pp->parent_bus_offset; atu.pci_addr = pp->io_bus_addr; atu.size = pp->io_size; @@ -790,7 +790,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) atu.index = i; atu.type = PCIE_ATU_TYPE_MEM; - atu.parent_bus_addr = entry->res->start; + atu.parent_bus_addr = entry->res->start - pp->parent_bus_offset; atu.pci_addr = entry->res->start - entry->offset; /* Adjust iATU size if MSG TLP region was allocated before */ @@ -812,7 +812,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) if (pci->num_ob_windows > ++i) { atu.index = i; atu.type = PCIE_ATU_TYPE_IO; - atu.parent_bus_addr = pp->io_base; + atu.parent_bus_addr = pp->io_base - pp->parent_bus_offset; atu.pci_addr = pp->io_bus_addr; atu.size = pp->io_size; @@ -956,7 +956,7 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) atu.size = resource_size(pci->pp.msg_res); atu.index = pci->pp.msg_atu_index; - atu.parent_bus_addr = pci->pp.msg_res->start; + atu.parent_bus_addr = pci->pp.msg_res->start - pci->pp.parent_bus_offset; ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 9d0a5f75effc..640caf4a084f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -474,9 +474,6 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u32 retries, val; u64 limit_addr; - if (pci->ops && pci->ops->cpu_addr_fixup) - parent_bus_addr = pci->ops->cpu_addr_fixup(pci, parent_bus_addr); - limit_addr = parent_bus_addr + atu->size - 1; if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) ||