From patchwork Sat Mar 8 22:58:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61698C282EC for ; Sat, 8 Mar 2025 22:59:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr38Q-0004WS-IT; Sat, 08 Mar 2025 17:59:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38N-0004TZ-78 for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:07 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tr38L-0005K2-Dr for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:06 -0500 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-223fb0f619dso59273975ad.1 for ; Sat, 08 Mar 2025 14:59:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741474744; x=1742079544; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=flAxIFy+Ab6eUm0+9WbxQUDS52odshsIOHS0bGzzjls=; b=P56rkARZZdEBEDwzRA2WuJc4phTPiBnx8nNL8R3xom6duamJJNIw/lA4UNRmqC0hWX NxT/zwYyVbhFByeHLbAYjqQnxQXviRLEjQSF7UDgfK8Ow3WB2xPBvb7WZ3b6Sk+UxEcC sYwfgnSC7uRu6/GzJrVZgSa22lfPjw3ReIJqES6nyYnNhdhJFZo+NIBgLk9TVPsKiL68 Jdl5UfAf9Kt4Hfp+v/0DuEYVfGm7b5rw1ThIbf6yKfVG0ztJKlfVCKKKIHURa0+wAtJb K8VgGIyw3fq1PFINXHr+YKHk3CZ1hamzM//ukdVmV36E5wXlJ8NQOU9OtruBrbKqnPNC cdaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741474744; x=1742079544; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=flAxIFy+Ab6eUm0+9WbxQUDS52odshsIOHS0bGzzjls=; b=fwEIud0yy4p/jGf7WnYUdL/379rRBoKg2WOy3zCAZM3hMjpQUAIsQP+zEYiHYiVKL/ tei7K2Z/X6561/xJzpC45qNQ1eEBXEu27u3qMrr3iA8iRIRRopo84xe4XT2AJe+9+ZFt C533qBFenIOdGOzamwja0hL85ozx98J6ZlozMuAZhIT+1/dF4uMgX4mnWZvD8fSDoAMI gt1CgOJ4ynkHHuFvjTOCiJcn2ggMx64aXjU3uLBtv9GCcY3VUa3yD7vXYhqtjxHo9cyH DR9Y9a17/l5V0PqHSgFobZHmyKa9g2gMk6ruuTJjHauOSv1twZ5n2BcZtu1BQcDPb25o 4Pog== X-Gm-Message-State: AOJu0YzpVBnFTaDUoJirVFADhBoO/T5IdiC34ULonPQ+m9Gl2mlY0HlT IblZieXy75NmnegSuAlYJ4xzuw9HQknDXX/q73tc/1k8Ios8B39YPDbKCn1rOCIIOpOUAQ2TWgX g X-Gm-Gg: ASbGncvyeDBNSGLFaTUfAFUmLYf/ofa0Co1IxHe+lJsoyqgCimR9fZujGP+5C3mH7xE Joj2ogPWu4SXt/N7ZxsiChUyLkBEeFxuf1EVHxO1k0YL6bRI7DnrMpLRGr+7ms7Jq4Z1pOq7hc6 urnD/KKm5MO7c21BhT0p7vsEZAQhBGOFaVXjkHFvcFBecdtH1PlH50WisiIpUbbXnmREA3HyZtB yTP6gToJ0vc4lHYEWmq1SaSWDelzMVhknKdW07hok2ift5T0bIJe8ucJTkcGNreyTDs9EQdRzX5 1bqkwkTCER8rXSjFe32mmQnrTOPOJjzfUy5xFJ3BLldo8Cg15PXLjBHEh20lFbLf8k+ipoo5Tn+ O X-Google-Smtp-Source: AGHT+IEEatxEcUKp1sk+eEQQ67IOIf6RotYkw8LxaYavtdWhEsYb8Hk8bJITF11MBSJaRuPn3e0akQ== X-Received: by 2002:a17:903:40cb:b0:224:24d3:60f4 with SMTP id d9443c01a7336-224288940admr133018685ad.15.1741474743967; Sat, 08 Mar 2025 14:59:03 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 01/23] linux-user/main: Allow setting tb-size Date: Sat, 8 Mar 2025 14:58:39 -0800 Message-ID: <20250308225902.1208237-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Ilya Leoshkevich While qemu-system can set tb-size using -accel tcg,tb-size=n, there is no similar knob for qemu-user. Add one in a way similar to how one-insn-per-tb is already handled. Signed-off-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-ID: <20240730215532.1442-1-iii@linux.ibm.com> --- linux-user/main.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/linux-user/main.c b/linux-user/main.c index 5c74c52cc5..e2ec5970be 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -72,6 +72,7 @@ char *exec_path; char real_exec_path[PATH_MAX]; static bool opt_one_insn_per_tb; +static unsigned long opt_tb_size; static const char *argv0; static const char *gdbstub; static envlist_t *envlist; @@ -425,6 +426,13 @@ static void handle_arg_one_insn_per_tb(const char *arg) opt_one_insn_per_tb = true; } +static void handle_arg_tb_size(const char *arg) +{ + if (qemu_strtoul(arg, NULL, 0, &opt_tb_size)) { + usage(EXIT_FAILURE); + } +} + static void handle_arg_strace(const char *arg) { enable_strace = true; @@ -517,6 +525,8 @@ static const struct qemu_argument arg_table[] = { {"one-insn-per-tb", "QEMU_ONE_INSN_PER_TB", false, handle_arg_one_insn_per_tb, "", "run with one guest instruction per emulated TB"}, + {"tb-size", "QEMU_TB_SIZE", true, handle_arg_tb_size, + "size", "TCG translation block cache size"}, {"strace", "QEMU_STRACE", false, handle_arg_strace, "", "log system calls"}, {"seed", "QEMU_RAND_SEED", true, handle_arg_seed, @@ -808,6 +818,8 @@ int main(int argc, char **argv, char **envp) accel_init_interfaces(ac); object_property_set_bool(OBJECT(accel), "one-insn-per-tb", opt_one_insn_per_tb, &error_abort); + object_property_set_int(OBJECT(accel), "tb-size", + opt_tb_size, &error_abort); ac->init_machine(NULL); } From patchwork Sat Mar 8 22:58:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41CA9C282EC for ; Sat, 8 Mar 2025 23:00:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr38q-0004ip-Hv; Sat, 08 Mar 2025 17:59:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38O-0004WD-NU for qemu-devel@nongnu.org; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 02/23] accel/tcg: Restrict CPU_TLB_DYN_*_BITS definitions to accel/tcg/ Date: Sat, 8 Mar 2025 14:58:41 -0800 Message-ID: <20250308225902.1208237-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé CPU_TLB_DYN_*_BITS definitions are only used by accel/tcg/cputlb.c and accel/tcg/translate-all.c. Move them to accel/tcg/tb-internal.h. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Reviewed-by: Richard Henderson Message-ID: <20250305191859.71608-1-philmd@linaro.org> --- accel/tcg/tb-internal.h | 27 +++++++++++++++++++++++++++ include/exec/cpu-defs.h | 26 -------------------------- 2 files changed, 27 insertions(+), 26 deletions(-) diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index 90be61f296..abd423fcf5 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -13,6 +13,33 @@ #include "exec/exec-all.h" #include "exec/translation-block.h" +#ifdef CONFIG_SOFTMMU + +#define CPU_TLB_DYN_MIN_BITS 6 +#define CPU_TLB_DYN_DEFAULT_BITS 8 + +# if HOST_LONG_BITS == 32 +/* Make sure we do not require a double-word shift for the TLB load */ +# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) +# else /* HOST_LONG_BITS == 64 */ +/* + * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == + * 2**34 == 16G of address space. This is roughly what one would expect a + * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel + * Skylake's Level-2 STLB has 16 1G entries. + * Also, make sure we do not size the TLB past the guest's address space. + */ +# ifdef TARGET_PAGE_BITS_VARY +# define CPU_TLB_DYN_MAX_BITS \ + MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) +# else +# define CPU_TLB_DYN_MAX_BITS \ + MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) +# endif +# endif + +#endif /* CONFIG_SOFTMMU */ + #ifdef CONFIG_USER_ONLY #include "user/page-protection.h" /* diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ae18398fa9..9f955f53fd 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -46,30 +46,4 @@ #include "exec/target_long.h" -#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG) -#define CPU_TLB_DYN_MIN_BITS 6 -#define CPU_TLB_DYN_DEFAULT_BITS 8 - -# if HOST_LONG_BITS == 32 -/* Make sure we do not require a double-word shift for the TLB load */ -# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) -# else /* HOST_LONG_BITS == 64 */ -/* - * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == - * 2**34 == 16G of address space. This is roughly what one would expect a - * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel - * Skylake's Level-2 STLB has 16 1G entries. - * Also, make sure we do not size the TLB past the guest's address space. - */ -# ifdef TARGET_PAGE_BITS_VARY -# define CPU_TLB_DYN_MAX_BITS \ - MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) -# else -# define CPU_TLB_DYN_MAX_BITS \ - MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) -# endif -# endif - -#endif /* CONFIG_SOFTMMU && CONFIG_TCG */ - #endif From patchwork Sat Mar 8 22:58:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007946 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCDCEC282EC for ; Sat, 8 Mar 2025 23:00:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr38Y-0004bf-GZ; Sat, 08 Mar 2025 17:59:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38P-0004WW-HV for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:09 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tr38N-0005KL-Gl for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:08 -0500 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-224100e9a5cso56104295ad.2 for ; Sat, 08 Mar 2025 14:59:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741474746; x=1742079546; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AwmVXBfhomA9Bq+qJ9rthBcoWLqoBCovvXeLZWVVOjU=; b=QsOQKGtQroJWcgWUQ8UPo++0WWUmX8J4kKOhmBYjvY9OI9euJ6Xsp2E8KyBhP/5ffZ xteY/xqL80byLcE4uCeHs365omRaYYRtaB99LvMFhAqioOQ96QOTuSzWOck/bgHilqUe qb+0ByiJEMPGRVNNJ1ikkj9yI6ZxRBSERvfKwA63pSK84NCFP9/QEqnyEzmiG88b3WTC GWixZIY1tkVAYc766ZyRg2m881Kjx44bHrWCGFU9nUAhr7k0j+H9/VSFu3wn3B0ZhC9n xCRbdqKw46EDFIXPwUDBL2oZlaIcOWoju0ZJFr9qrPsLESkCARsfMsQI1RpD3/RPpoAE AmEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741474746; x=1742079546; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AwmVXBfhomA9Bq+qJ9rthBcoWLqoBCovvXeLZWVVOjU=; b=ehOiFesCBAMn4cIfV0m1CZYsKgOW2Ki4jMWcG0wfmMm1Vu9Z/r/q6ZqDWhlX2K51s0 ib9xPDrLpJ2T7L32S0ZzQcq1b9yaQN42y684w3QEq1G/0YMN6ewUXSyfaZzfTK4kFgK4 JIQB9SH0k9A5CFpnz9Z2EbdRzLtq+5LkFaaz7uS5YO07NQWKEgQhnStv8M3demt2Fr0G 6C6HzgDPtkZ1UGBqMnxwDjIma1vmDG63BGjh+EroE2pJ9ic8xutw/hDvNI9uH/pxMEwb +Ib1faQ9qlR3osVAv7rY3Yn8rHRxg9ymt75wsy+MzZ0AR9EN+21jLYlpfLih1SE5aAut Kc4A== X-Gm-Message-State: AOJu0YxQm10pF+XM19RacIBUdEXr+/2buWotxfn1fIiByTwTTNwUXnTQ 1cXeW2m6yqA3GDNCR4/OBAQXGGHApfokHQoUBLEyeyEV5c7sQOR4z+t8oyu6xBSdOPHQm+1O7Nk Z X-Gm-Gg: ASbGncso/HG+N0sM0f7tNefVOOuCiZvHeeKTla3f2NGffqEqdBnlHpRyNcPshqrqOLH ulo4gOJLgRPYf7Ro0cJEH1LK0WsN0fN8KFl5g41Emyp85YhbI5q3x3qaCAsppmvO9semgak6RaK kT/yvbBnWkl2Suh3XmdVA75YMAb9iImVqvF5BRWQv/tbSphyYl01wMndxVmTD52ZHNimk2eaMms jMnTDiC4Hqh+29eUdvU8gfPA9tXA6TriiTffPPPYIS6ymkdqB3J2swE3u/J1X64uBZqSuR/TVCA pWaL0In+4oeOtVW0Lelzqb3u0p2gelUlVl0GZfkl+DVjq5xl+S87lOVOnZtn63Sv2mg+Ts71nqe HDfDKWVYz8iI= X-Google-Smtp-Source: AGHT+IGUfE4iEHmKdp+TEktXEdFDHwGoBoy6uot/g+/cXiQ8MzXB30jI9wtZv2Y2dtYjODMhLUlECg== X-Received: by 2002:a17:902:f648:b0:220:d601:a704 with SMTP id d9443c01a7336-22428a967a4mr124452505ad.18.1741474746000; Sat, 08 Mar 2025 14:59:06 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 03/23] include/exec: Move TARGET_PAGE_{SIZE, MASK, BITS} to target_page.h Date: Sat, 8 Mar 2025 14:58:42 -0800 Message-ID: <20250308225902.1208237-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Re-use the TARGET_PAGE_BITS_VARY mechanism to define TARGET_PAGE_SIZE and friends when not compiling per-target. Inline qemu_target_page_{size,mask,bits} as they are now trivial. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 21 +------------- include/exec/poison.h | 4 --- include/exec/target_page.h | 58 ++++++++++++++++++++++++++++++++++---- page-target.c | 18 ------------ page-vary-target.c | 2 -- 5 files changed, 53 insertions(+), 50 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 09f537d06f..8f7aebb088 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -105,26 +105,7 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val /* page related stuff */ #include "exec/cpu-defs.h" -#ifdef TARGET_PAGE_BITS_VARY -# include "exec/page-vary.h" -extern const TargetPageBits target_page; -# ifdef CONFIG_DEBUG_TCG -# define TARGET_PAGE_BITS ({ assert(target_page.decided); \ - target_page.bits; }) -# define TARGET_PAGE_MASK ({ assert(target_page.decided); \ - (target_long)target_page.mask; }) -# else -# define TARGET_PAGE_BITS target_page.bits -# define TARGET_PAGE_MASK ((target_long)target_page.mask) -# endif -# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) -#else -# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS -# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) -# define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) -#endif - -#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) +#include "exec/target_page.h" CPUArchState *cpu_copy(CPUArchState *env); diff --git a/include/exec/poison.h b/include/exec/poison.h index d6d4832854..35721366d7 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -44,10 +44,6 @@ #pragma GCC poison TARGET_FMT_ld #pragma GCC poison TARGET_FMT_lu -#pragma GCC poison TARGET_PAGE_SIZE -#pragma GCC poison TARGET_PAGE_MASK -#pragma GCC poison TARGET_PAGE_BITS -#pragma GCC poison TARGET_PAGE_ALIGN #pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS #pragma GCC poison CPU_INTERRUPT_HARD diff --git a/include/exec/target_page.h b/include/exec/target_page.h index 98ffbb5c23..8e89e5cbe6 100644 --- a/include/exec/target_page.h +++ b/include/exec/target_page.h @@ -14,10 +14,56 @@ #ifndef EXEC_TARGET_PAGE_H #define EXEC_TARGET_PAGE_H -size_t qemu_target_page_size(void); -int qemu_target_page_mask(void); -int qemu_target_page_bits(void); -int qemu_target_page_bits_min(void); - -size_t qemu_target_pages_to_MiB(size_t pages); +/* + * If compiling per-target, get the real values. + * For generic code, reuse the mechanism for variable page size. + */ +#ifdef COMPILING_PER_TARGET +#include "cpu-param.h" +#include "exec/target_long.h" +#define TARGET_PAGE_TYPE target_long +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_TYPE int +#endif + +#ifdef TARGET_PAGE_BITS_VARY +# include "exec/page-vary.h" +extern const TargetPageBits target_page; +# ifdef CONFIG_DEBUG_TCG +# define TARGET_PAGE_BITS ({ assert(target_page.decided); \ + target_page.bits; }) +# define TARGET_PAGE_MASK ({ assert(target_page.decided); \ + (TARGET_PAGE_TYPE)target_page.mask; }) +# else +# define TARGET_PAGE_BITS target_page.bits +# define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)target_page.mask) +# endif +# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) +#else +# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS +# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) +# define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)-1 << TARGET_PAGE_BITS) +#endif + +#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) + +static inline size_t qemu_target_page_size(void) +{ + return TARGET_PAGE_SIZE; +} + +static inline int qemu_target_page_mask(void) +{ + return TARGET_PAGE_MASK; +} + +static inline int qemu_target_page_bits(void) +{ + return TARGET_PAGE_BITS; +} + +int qemu_target_page_bits_min(void); +size_t qemu_target_pages_to_MiB(size_t pages); + #endif diff --git a/page-target.c b/page-target.c index 82211c8593..321e43d06f 100644 --- a/page-target.c +++ b/page-target.c @@ -8,24 +8,6 @@ #include "qemu/osdep.h" #include "exec/target_page.h" -#include "exec/cpu-defs.h" -#include "cpu.h" -#include "exec/cpu-all.h" - -size_t qemu_target_page_size(void) -{ - return TARGET_PAGE_SIZE; -} - -int qemu_target_page_mask(void) -{ - return TARGET_PAGE_MASK; -} - -int qemu_target_page_bits(void) -{ - return TARGET_PAGE_BITS; -} int qemu_target_page_bits_min(void) { diff --git a/page-vary-target.c b/page-vary-target.c index 343b4adb95..3f81144cda 100644 --- a/page-vary-target.c +++ b/page-vary-target.c @@ -35,7 +35,5 @@ bool set_preferred_target_page_bits(int bits) void finalize_target_page_bits(void) { -#ifdef TARGET_PAGE_BITS_VARY finalize_target_page_bits_common(TARGET_PAGE_BITS_MIN); -#endif } From patchwork Sat Mar 8 22:58:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02BE5C28B25 for ; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 04/23] include/exec: Split out exec/cpu-interrupt.h Date: Sat, 8 Mar 2025 14:58:43 -0800 Message-ID: <20250308225902.1208237-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Some of these bits are actually common to all cpus; while the reset have common reservations for target-specific usage. While generic code cannot know what the target-specific usage is, common code can know what to do with the bits, e.g. single-step. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 53 +-------------------------- include/exec/cpu-interrupt.h | 70 ++++++++++++++++++++++++++++++++++++ include/exec/poison.h | 13 ------- 3 files changed, 71 insertions(+), 65 deletions(-) create mode 100644 include/exec/cpu-interrupt.h diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8f7aebb088..9e6724097c 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -21,6 +21,7 @@ #include "exec/page-protection.h" #include "exec/cpu-common.h" +#include "exec/cpu-interrupt.h" #include "exec/memory.h" #include "exec/tswap.h" #include "hw/core/cpu.h" @@ -109,58 +110,6 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val CPUArchState *cpu_copy(CPUArchState *env); -/* Flags for use in ENV->INTERRUPT_PENDING. - - The numbers assigned here are non-sequential in order to preserve - binary compatibility with the vmstate dump. Bit 0 (0x0001) was - previously used for CPU_INTERRUPT_EXIT, and is cleared when loading - the vmstate dump. */ - -/* External hardware interrupt pending. This is typically used for - interrupts from devices. */ -#define CPU_INTERRUPT_HARD 0x0002 - -/* Exit the current TB. This is typically used when some system-level device - makes some change to the memory mapping. E.g. the a20 line change. */ -#define CPU_INTERRUPT_EXITTB 0x0004 - -/* Halt the CPU. */ -#define CPU_INTERRUPT_HALT 0x0020 - -/* Debug event pending. */ -#define CPU_INTERRUPT_DEBUG 0x0080 - -/* Reset signal. */ -#define CPU_INTERRUPT_RESET 0x0400 - -/* Several target-specific external hardware interrupts. Each target/cpu.h - should define proper names based on these defines. */ -#define CPU_INTERRUPT_TGT_EXT_0 0x0008 -#define CPU_INTERRUPT_TGT_EXT_1 0x0010 -#define CPU_INTERRUPT_TGT_EXT_2 0x0040 -#define CPU_INTERRUPT_TGT_EXT_3 0x0200 -#define CPU_INTERRUPT_TGT_EXT_4 0x1000 - -/* Several target-specific internal interrupts. These differ from the - preceding target-specific interrupts in that they are intended to - originate from within the cpu itself, typically in response to some - instruction being executed. These, therefore, are not masked while - single-stepping within the debugger. */ -#define CPU_INTERRUPT_TGT_INT_0 0x0100 -#define CPU_INTERRUPT_TGT_INT_1 0x0800 -#define CPU_INTERRUPT_TGT_INT_2 0x2000 - -/* First unused bit: 0x4000. */ - -/* The set of all bits that should be masked when single-stepping. */ -#define CPU_INTERRUPT_SSTEP_MASK \ - (CPU_INTERRUPT_HARD \ - | CPU_INTERRUPT_TGT_EXT_0 \ - | CPU_INTERRUPT_TGT_EXT_1 \ - | CPU_INTERRUPT_TGT_EXT_2 \ - | CPU_INTERRUPT_TGT_EXT_3 \ - | CPU_INTERRUPT_TGT_EXT_4) - #include "cpu.h" #ifdef CONFIG_USER_ONLY diff --git a/include/exec/cpu-interrupt.h b/include/exec/cpu-interrupt.h new file mode 100644 index 0000000000..40715193ca --- /dev/null +++ b/include/exec/cpu-interrupt.h @@ -0,0 +1,70 @@ +/* + * Flags for use with cpu_interrupt() + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef CPU_INTERRUPT_H +#define CPU_INTERRUPT_H + +/* + * The numbers assigned here are non-sequential in order to preserve binary + * compatibility with the vmstate dump. Bit 0 (0x0001) was previously used + * for CPU_INTERRUPT_EXIT, and is cleared when loading the vmstate dump. + */ + +/* + * External hardware interrupt pending. + * This is typically used for interrupts from devices. + */ +#define CPU_INTERRUPT_HARD 0x0002 + +/* + * Exit the current TB. This is typically used when some system-level device + * makes some change to the memory mapping. E.g. the a20 line change. + */ +#define CPU_INTERRUPT_EXITTB 0x0004 + +/* Halt the CPU. */ +#define CPU_INTERRUPT_HALT 0x0020 + +/* Debug event pending. */ +#define CPU_INTERRUPT_DEBUG 0x0080 + +/* Reset signal. */ +#define CPU_INTERRUPT_RESET 0x0400 + +/* + * Several target-specific external hardware interrupts. Each target/cpu.h + * should define proper names based on these defines. + */ +#define CPU_INTERRUPT_TGT_EXT_0 0x0008 +#define CPU_INTERRUPT_TGT_EXT_1 0x0010 +#define CPU_INTERRUPT_TGT_EXT_2 0x0040 +#define CPU_INTERRUPT_TGT_EXT_3 0x0200 +#define CPU_INTERRUPT_TGT_EXT_4 0x1000 + +/* + * Several target-specific internal interrupts. These differ from the + * preceding target-specific interrupts in that they are intended to + * originate from within the cpu itself, typically in response to some + * instruction being executed. These, therefore, are not masked while + * single-stepping within the debugger. + */ +#define CPU_INTERRUPT_TGT_INT_0 0x0100 +#define CPU_INTERRUPT_TGT_INT_1 0x0800 +#define CPU_INTERRUPT_TGT_INT_2 0x2000 + +/* First unused bit: 0x4000. */ + +/* The set of all bits that should be masked when single-stepping. */ +#define CPU_INTERRUPT_SSTEP_MASK \ + (CPU_INTERRUPT_HARD \ + | CPU_INTERRUPT_TGT_EXT_0 \ + | CPU_INTERRUPT_TGT_EXT_1 \ + | CPU_INTERRUPT_TGT_EXT_2 \ + | CPU_INTERRUPT_TGT_EXT_3 \ + | CPU_INTERRUPT_TGT_EXT_4) + +#endif /* CPU_INTERRUPT_H */ diff --git a/include/exec/poison.h b/include/exec/poison.h index 35721366d7..8ed04b3108 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -46,19 +46,6 @@ #pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS -#pragma GCC poison CPU_INTERRUPT_HARD -#pragma GCC poison CPU_INTERRUPT_EXITTB -#pragma GCC poison CPU_INTERRUPT_HALT -#pragma GCC poison CPU_INTERRUPT_DEBUG -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_0 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_1 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_2 - #pragma GCC poison CONFIG_ALPHA_DIS #pragma GCC poison CONFIG_HPPA_DIS #pragma GCC poison CONFIG_I386_DIS From patchwork Sat Mar 8 22:58:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D7B1C28B25 for ; Sat, 8 Mar 2025 23:00:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr38Y-0004bo-OD; Sat, 08 Mar 2025 17:59:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38Q-0004X6-Fi for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:10 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tr38O-0005Kp-GJ for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:09 -0500 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-2243803b776so34770505ad.0 for ; Sat, 08 Mar 2025 14:59:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741474747; x=1742079547; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rcajlMgTUfCgyOIfOLm4spslr595y2hmlpKS/Lu7HtA=; b=DFIqQhLYzA7RJwFFFlOH2ETr1xlkYu85UEcZfrmq0o6k/8MZvQXCcfGKn/R5mvrOnT m50htf86mzvTh5BcCC2/C1Cgu1WyjLGEWQ74kNiH1qb4PUTFel8up5xvodUvof8YpRJJ UXbgcCf3Da/qzPgQIxYuDuCm6uPpPJy7x07PJLx9HWHtiQrKxC6DFZi3iqXmyfoB+uWS N3yFiBac9ZtuaNmNCHh9x1tSyiw53pPxb6Pwzldnuy7YxqbH+ydJhXbaTBAXAp2Ss7w8 BCW9KFfiEv+MmVT6EJnbGjKhdg25og24NOB32vCFLBdCclPmMk1y2TNIrigfQIl6ofr+ 0K1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741474747; x=1742079547; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rcajlMgTUfCgyOIfOLm4spslr595y2hmlpKS/Lu7HtA=; b=vyDJV2KliJYf0JX4ByVmr0znFGhwFvrsX6mrNPnStBKP+jzBhGsq1JaCOzlZyjbUZd IhC5DDLVpz1gJt4y/HhceeNUF0pfv+DfVs5vWgcPzLjXuywh4mQjdXCrxG1GSQvWCN3w ZPj6DJJljgi7zJpD5m8Rg8Hqvd7oqZ7EqEfE6As843Krs0uo4kiix0n62kyb6bMR78FK Xf5tv8lxyTakwZ6vrIES1gIc/Z1SGnsuoEiihifYAe9RpL4cNeDRU5GZ672nUKv8KNYk BdOrLkFLhRHDC0nV51GWGwfl6pmWGziSFhpvHL4yb6vbKnrCUM9gLdRp1ejMwmdI4swB YQ5Q== X-Gm-Message-State: AOJu0Yw6mzmTw9mqo1xTT+UY4IATwEgrEF2NmqjnYWcdPcrt725WFi5Z WyOSJInmniiPrKiNHnFA5P58ax/Z1H/zb0KldbZs+CWqliq5O+zgRReVhntjSFaJKiT0m5h23HZ 6 X-Gm-Gg: ASbGncu2c0TrI9SAj1PmJJiFF9Fd/BIwWsI4m7tnQm4G0BXNydnT9jtYnndSOf58AKN qoyaWxiCTL0tSek7I1+0bbT37R97RN2eAHc0aKR91G4e4cstLyGRy7YHZB2o7deV9IFTwa9ENxO byytkym4CKdZBddgeh6Jkay5aRuLHDTdENhUlNg/3ltWqqUC9N0JDW5cHhcvGSEpNDUFF3b1AWX DHg3OZTRgOwWnqjdcvVwZSQLtcVWJ704l7uJNR6szqrVqwCQFEGrN7za5066lyA9dQDZMQOq7sa C1vln7Rsd3khKh/WbOz5ngIwwUo3jJquL40FjAEaGA1736aOxYy2eDG9bcRrAxsd9F1i7YFzJvC V X-Google-Smtp-Source: AGHT+IF9UEhBahvFHy7TfbJiahotKU7YBC/qh0HKvNvAc0yHgbPU5VAoydc+4fZCx/bHSult98GuqA== X-Received: by 2002:a17:902:eb81:b0:224:1935:d9a3 with SMTP id d9443c01a7336-2242888ab01mr150766635ad.21.1741474747234; Sat, 08 Mar 2025 14:59:07 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 05/23] accel/tcg: Compile watchpoint.c once Date: Sat, 8 Mar 2025 14:58:44 -0800 Message-ID: <20250308225902.1208237-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move tb_check_watchpoint declaration from tb-internal.h, which is still target-specific, to internal-common.h, which isn't. Otherwise, all that is required to build watchpoint.c once is to include the new exec/cpu-interrupt.h instead of exec/exec-all.h. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/internal-common.h | 2 ++ accel/tcg/tb-internal.h | 2 -- accel/tcg/watchpoint.c | 5 ++--- accel/tcg/meson.build | 2 +- 4 files changed, 5 insertions(+), 6 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 7ef620d963..9b6ab3a8cc 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -72,4 +72,6 @@ void tcg_exec_unrealizefn(CPUState *cpu); /* current cflags for hashing/comparison */ uint32_t curr_cflags(CPUState *cpu); +void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); + #endif diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index abd423fcf5..62a59a5307 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -75,6 +75,4 @@ void tb_invalidate_phys_range_fast(ram_addr_t ram_addr, bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc); -void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); - #endif diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index 40112b2b2e..ba8c9859cf 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -19,11 +19,10 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" -#include "qemu/error-report.h" -#include "exec/exec-all.h" +#include "exec/breakpoint.h" +#include "exec/cpu-interrupt.h" #include "exec/page-protection.h" #include "exec/translation-block.h" -#include "tb-internal.h" #include "system/tcg.h" #include "system/replay.h" #include "accel/tcg/cpu-ops.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 69f4808ac4..979ce90eb0 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', - 'watchpoint.c', 'tcg-accel-ops.c', 'tcg-accel-ops-mttcg.c', 'tcg-accel-ops-icount.c', @@ -30,4 +29,5 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', 'monitor.c', + 'watchpoint.c', )) From patchwork Sat Mar 8 22:58:45 2025 Content-Type: text/plain; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 06/23] exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h' Date: Sat, 8 Mar 2025 14:58:45 -0800 Message-ID: <20250308225902.1208237-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Message-ID: <20241114011310.3615-14-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/exec/cputlb.h | 7 +++++++ include/exec/exec-all.h | 3 --- include/exec/ram_addr.h | 1 + system/physmem.c | 1 + 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index ef18642a32..6cac7d530f 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -32,4 +32,11 @@ void tlb_unprotect_code(ram_addr_t ram_addr); #endif /* CONFIG_TCG */ +#ifndef CONFIG_USER_ONLY + +void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); +void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); + +#endif + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 8eb0df48f9..f24256fb5e 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -486,9 +486,6 @@ static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, #if !defined(CONFIG_USER_ONLY) -void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); -void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); - MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, hwaddr *xlat, hwaddr *plen, diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 94bb3ccbe4..3d8df4edf1 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -23,6 +23,7 @@ #include "cpu.h" #include "system/xen.h" #include "system/tcg.h" +#include "exec/cputlb.h" #include "exec/ramlist.h" #include "exec/ramblock.h" #include "exec/exec-all.h" diff --git a/system/physmem.c b/system/physmem.c index 8c1736f84e..a6af555f4b 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -32,6 +32,7 @@ #endif /* CONFIG_TCG */ #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/translation-block.h" From patchwork Sat Mar 8 22:58:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0F7CC28B2E for ; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 07/23] exec: Declare tlb_set_page_full() in 'exec/cputlb.h' Date: Sat, 8 Mar 2025 14:58:46 -0800 Message-ID: <20250308225902.1208237-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-16-philmd@linaro.org> --- include/exec/cputlb.h | 23 +++++++++++++++++++++++ include/exec/exec-all.h | 22 ---------------------- target/sparc/mmu_helper.c | 2 +- 3 files changed, 24 insertions(+), 23 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 6cac7d530f..733ef012d1 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -21,6 +21,7 @@ #define CPUTLB_H #include "exec/cpu-common.h" +#include "exec/vaddr.h" #ifdef CONFIG_TCG @@ -39,4 +40,26 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); #endif +/** + * tlb_set_page_full: + * @cpu: CPU context + * @mmu_idx: mmu index of the tlb to modify + * @addr: virtual address of the entry to add + * @full: the details of the tlb entry + * + * Add an entry to @cpu tlb index @mmu_idx. All of the fields of + * @full must be filled, except for xlat_section, and constitute + * the complete description of the translated page. + * + * This is generally called by the target tlb_fill function after + * having performed a successful page table walk to find the physical + * address and attributes for the translation. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only + * used by tlb_flush_page. + */ +void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, + CPUTLBEntryFull *full); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f24256fb5e..f43c67366b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -156,28 +156,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap, unsigned bits); -/** - * tlb_set_page_full: - * @cpu: CPU context - * @mmu_idx: mmu index of the tlb to modify - * @addr: virtual address of the entry to add - * @full: the details of the tlb entry - * - * Add an entry to @cpu tlb index @mmu_idx. All of the fields of - * @full must be filled, except for xlat_section, and constitute - * the complete description of the translated page. - * - * This is generally called by the target tlb_fill function after - * having performed a successful page table walk to find the physical - * address and attributes for the translation. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only - * used by tlb_flush_page. - */ -void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, - CPUTLBEntryFull *full); - /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 9ff06026b8..7548d01777 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "qemu/qemu-print.h" #include "trace.h" From patchwork Sat Mar 8 22:58:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33E7FC282EC for ; Sat, 8 Mar 2025 23:02:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr38d-0004dh-7a; Sat, 08 Mar 2025 17:59:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38S-0004Yv-Du for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:12 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tr38Q-0005Lf-Lh for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:12 -0500 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-225477548e1so10272865ad.0 for ; Sat, 08 Mar 2025 14:59:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741474749; x=1742079549; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OZUhu3BnFzDT2DJGeBZFOFqKQQp7EogeXchL7RAMkqI=; b=gxQjwbFGTYLCzHiuRkwTvYMJIBp7mICGJ5b197fSY6uQPIoJMWNPEkHS5bWeXmpYDu qcGfY01ahjFCD5dvxoRgClWK5T0dq0n/V9yXWezO9Ig7Tk9Au4Nj3cm+g7Z8ClVyFo9j Pjj9lu4/9U1URrgO+nstGCLbcstiZ49QdH0RoDXN3Brb1MlXkfep364lRQZWgeU7Gvg/ tZeAOE/Fa6xiTwl00nmp5WOYECSKYlNRq4mFayywf6q1Dx/tej8LpB1DXtekMcoiuZhx FBFuFkc/ptplFVysi/ei+vFnTDdQBGnSBJSQFqtTg7JCoS4E0JBnme/wqOOwmeJXp4tY LLFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741474749; x=1742079549; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OZUhu3BnFzDT2DJGeBZFOFqKQQp7EogeXchL7RAMkqI=; b=g50fqURkNgp6MeOs7XJPlC/fTcAJDAwLaOKuOGjy5O89lND/Jd0WyDTEDTmniUJB9X XWQ3ou5tt2b8m8XXfTx2ILP++7OiyaTDrpgWUo+Ppc0Pxt64lqHoHN4sc/Wtoo1rYCOM t/dO/w6aJoLxWHQ0GwApVXe58u4EmSKW+9dc/ExRJLAJvPJQKeEWHkg0m/LNh2dkku8S lEct8+C5RfGor4+AYm3izJckKnWI1ABcFIaL41WlZomgsAZri+KWi5ifgEcDMPTB0T84 ++NKeWH07jFV3Atjzaa0CYHlNviiAuSOJyZH6bcu9VupRVFF0kte++OGHOzjoPomUU8x wuYg== X-Gm-Message-State: AOJu0YztYefabE3rVDBo+PFWGctIAkaSv8Ag/2rDQH09hRu723g+mOBH nNkxQ046+3nqOBwOy8bZkuxnrzsvqEI4U8jHXWfpzH8kPASahDyY47Yiz3JtWpc66LXjI6Sir1b j X-Gm-Gg: ASbGncuR2suN/iVXQAOvUii1G70Qgi3odrhR48Ez2h1N/XhDZIWRToE7Qn4k35yQu07 6iiw+1IZukR2C93TER1Cy6QsADvPcz34o9l0UAitRnGdI2TjsmAoCEhYwUlOzH5i+0FvfJRWZOb xxnIS+iZuOtiPLWJMr/71JaBR0wZnlnC/UiSGv5goB6RJjkp+cPmRINed3h/buRX2Bu8sAbEuoZ sLRRKSXkz4KxCnIXold97bonju1aZT7AVshhI/eIdJ8eTMSNOuKH5N6QMhrwRqboOfs+aN79BLw l6je72QeCGETKEmtCnkLMhHJ5o0FDbITmnUL2Mp/CJq0+guBTXaAyXdDZjP8TSJV1SyVOxxaFwT w X-Google-Smtp-Source: AGHT+IE3dT/L3ABJKjRYygN4jGaIS5mHRrX+2jiFHVKGPVfWhzLfKEtochPP4IkpERNbxDBRMo5tLQ== X-Received: by 2002:a17:903:40cb:b0:223:44c5:4eb8 with SMTP id d9443c01a7336-22428c0752cmr146209285ad.32.1741474749073; Sat, 08 Mar 2025 14:59:09 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 08/23] exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h' Date: Sat, 8 Mar 2025 14:58:47 -0800 Message-ID: <20250308225902.1208237-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-17-philmd@linaro.org> --- include/exec/cputlb.h | 28 ++++++++++++++++++++++++++++ include/exec/exec-all.h | 25 ------------------------- target/i386/tcg/system/excp_helper.c | 2 +- target/microblaze/helper.c | 2 +- 4 files changed, 30 insertions(+), 27 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 733ef012d1..56dd05a148 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -21,6 +21,8 @@ #define CPUTLB_H #include "exec/cpu-common.h" +#include "exec/hwaddr.h" +#include "exec/memattrs.h" #include "exec/vaddr.h" #ifdef CONFIG_TCG @@ -62,4 +64,30 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, CPUTLBEntryFull *full); +/** + * tlb_set_page_with_attrs: + * @cpu: CPU to add this TLB entry for + * @addr: virtual address of page to add entry for + * @paddr: physical address of the page + * @attrs: memory transaction attributes + * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) + * @mmu_idx: MMU index to insert TLB entry for + * @size: size of the page in bytes + * + * Add an entry to this CPU's TLB (a mapping from virtual address + * @addr to physical address @paddr) with the specified memory + * transaction attributes. This is generally called by the target CPU + * specific code after it has been called through the tlb_fill() + * entry point and performed a successful page table walk to find + * the physical address and attributes for the virtual address + * which provoked the TLB miss. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only + * used by tlb_flush_page. + */ +void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, vaddr size); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f43c67366b..62d6300752 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -156,31 +156,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap, unsigned bits); -/** - * tlb_set_page_with_attrs: - * @cpu: CPU to add this TLB entry for - * @addr: virtual address of page to add entry for - * @paddr: physical address of the page - * @attrs: memory transaction attributes - * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) - * @mmu_idx: MMU index to insert TLB entry for - * @size: size of the page in bytes - * - * Add an entry to this CPU's TLB (a mapping from virtual address - * @addr to physical address @paddr) with the specified memory - * transaction attributes. This is generally called by the target CPU - * specific code after it has been called through the tlb_fill() - * entry point and performed a successful page table walk to find - * the physical address and attributes for the virtual address - * which provoked the TLB miss. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only - * used by tlb_flush_page. - */ -void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, - hwaddr paddr, MemTxAttrs attrs, - int prot, int mmu_idx, vaddr size); /* tlb_set_page: * * This function is equivalent to calling tlb_set_page_with_attrs() diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c index 864e3140e3..6876329de2 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/cpu_ldst.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "tcg/helper-tcg.h" diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5d3259ce31..27fc929bee 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "qemu/host-utils.h" #include "exec/log.h" From patchwork Sat Mar 8 22:58:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BDC7C282EC for ; Sat, 8 Mar 2025 23:02:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr38d-0004di-7b; Sat, 08 Mar 2025 17:59:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38T-0004Zu-En for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:13 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tr38R-0005Lu-86 for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:12 -0500 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-223959039f4so60749495ad.3 for ; Sat, 08 Mar 2025 14:59:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741474750; x=1742079550; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4u5PBwHEPecUaxrqA3yTEFMGllvxnHxvoZEJcDTq3Zs=; b=D4ndGY7BtFWutR9tk1CMKnVIuFIwVa1Bvdu7mOH3sTk141TqOJYXO1/JWBt47g5i6j 5wYMyW+hCfGEAAoOcCZ84Eh3j7xotuJUIm6r1PITOAmIBdb5nQYTQXfpGxbNvc+VcE7P Mdsdk3L9zrcPeJmHqbM4CufyX5UkU6xdcSjAmqs4kyOrT0sZMlf93iGB2Xqbirv6B4fm REhFNwsK+Q3obvQqm02SN7pgZtYEkkRnhdweHdL/H3hZ7l0BXkU0fx0bz7BRJiagUjL/ N+N80I/CXm3fDfVAebAfBp8yqRgI0AFBQ3dq2jn4dHdtUDwl1uVFZI1X6uJ5L/ejg1oy Cw4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741474750; x=1742079550; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4u5PBwHEPecUaxrqA3yTEFMGllvxnHxvoZEJcDTq3Zs=; b=VUZOrrAAInW12MH3DQE8giEaF6bmKI3+aaG22D2Z56ZNLnI+Lsmd1EHBnh2d8jHoRb nl4uPJHUCno0bwAS8HBYqu/8B0iPUG+mHqG8a/aH8yj1NCb1U96XtbRGzC+Z7l6nDL23 eEZ5YUd+ZIGq3aq+/mjjz0FbP94+jX7lQMkNviCX1yGd/t8xsat+v0hVSKALGzUAwqih CUP7RJFX/o/7pUzdpVc5z/k3bmH3nWVODvTgt5KE4Z0sMuCRu57rvvoG0Sm0gMTsjQkx WS9WQ3jUaXnRRfkb6GuZSVqr8cipWCu0YLCJwIRejCz656fPy9gUWWDfwBdjorEDwL0A KiKg== X-Gm-Message-State: AOJu0Yy36Ty49G7KR9tmEDrsHnmS21NCYPnGf4f4FGx6UiYQirgomZ5r filJGUCtCUTdfsWrh26USJJhBALYHtH/eoJl42kG1X1gnMnJQ+WiSrrNl2nUvUm7AqjlxV72C6T j X-Gm-Gg: ASbGncsNRN8EaeMyJB3SiQmpYG6JdLMZf/fpo1Up0fwbUweRJ3CVDDQsjXRTbwu6jmS C0+xf8a96RhHp48HqNg/OcZHgfgCB1C8NsoU+N3ewL61PrCUc+glG/tByzAh3OqNAiD4xwlVU9f nplD+0AOTQ9w8faz7tgaoOwH5jTlWL9nh82JGk/87SzWARo+ifE6I+BniONumcB8ZVHjSLoQAzI X1rNpoUBW4+194RLtp3RCGiLKWwxtPUYkl/MNGRx8Ps57jZO5LUwtCW6g6upgN0RnvrazwFEVAA VbPMh66KuHGHdIbVwVU7ZXNscuI4p+/wkyHdRJeYBwRCI5Mb5c688xkldu82gzgnaXZtvx8iRSz q X-Google-Smtp-Source: AGHT+IHkcp12zRGYST6rP7g60xgT2DJu0QbKhCD1443sluPBgq0OzC7BmkUFpwQydTJzENI4ZmWqhg== X-Received: by 2002:a17:902:ec89:b0:224:10a2:cad9 with SMTP id d9443c01a7336-22428bd5852mr161238565ad.41.1741474749910; Sat, 08 Mar 2025 14:59:09 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 09/23] exec: Declare tlb_set_page() in 'exec/cputlb.h' Date: Sat, 8 Mar 2025 14:58:48 -0800 Message-ID: <20250308225902.1208237-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-18-philmd@linaro.org> --- include/exec/cputlb.h | 11 +++++++++++ include/exec/exec-all.h | 9 --------- target/alpha/helper.c | 2 +- target/avr/helper.c | 2 +- target/loongarch/tcg/tlb_helper.c | 1 + target/m68k/helper.c | 1 + target/mips/tcg/system/tlb_helper.c | 1 + target/openrisc/mmu.c | 2 +- target/ppc/mmu_helper.c | 1 + target/riscv/cpu_helper.c | 1 + target/rx/cpu.c | 2 +- target/s390x/tcg/excp_helper.c | 1 + target/sh4/helper.c | 1 + target/tricore/helper.c | 2 +- target/xtensa/helper.c | 2 +- 15 files changed, 24 insertions(+), 15 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 56dd05a148..cdfaf17403 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -90,4 +90,15 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, hwaddr paddr, MemTxAttrs attrs, int prot, int mmu_idx, vaddr size); +/** + * tlb_set_page: + * + * This function is equivalent to calling tlb_set_page_with_attrs() + * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided + * as a convenience for CPUs which don't use memory transaction attributes. + */ +void tlb_set_page(CPUState *cpu, vaddr addr, + hwaddr paddr, int prot, + int mmu_idx, vaddr size); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 62d6300752..a3aa8448d0 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -156,15 +156,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap, unsigned bits); -/* tlb_set_page: - * - * This function is equivalent to calling tlb_set_page_with_attrs() - * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided - * as a convenience for CPUs which don't use memory transaction attributes. - */ -void tlb_set_page(CPUState *cpu, vaddr addr, - hwaddr paddr, int prot, - int mmu_idx, vaddr size); #else static inline void tlb_flush_page(CPUState *cpu, vaddr addr) { diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 2f1000c99f..57cefcba14 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "fpu/softfloat-types.h" #include "exec/helper-proto.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index 9ea6870e44..3412312ad5 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,7 +23,7 @@ #include "qemu/error-report.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index a323606e5a..f6b63c7224 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -12,6 +12,7 @@ #include "cpu.h" #include "internals.h" #include "exec/helper-proto.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" diff --git a/target/m68k/helper.c b/target/m68k/helper.c index beefeb7069..0bf574830f 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/gdbstub.h" diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c index e98bb95951..ca4d6b27bc 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internal.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index c632d5230b..47ac783c52 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "gdbstub/helpers.h" #include "qemu/host-utils.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index a802bc9c62..ad9ba8294c 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -24,6 +24,7 @@ #include "kvm_ppc.h" #include "mmu-hash64.h" #include "mmu-hash32.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/log.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 34092f372d..6c4391d96b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "internals.h" #include "pmu.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "instmap.h" diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 1c40c8977e..f01e069a90 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -21,7 +21,7 @@ #include "qapi/error.h" #include "cpu.h" #include "migration/vmstate.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/translation-block.h" #include "hw/loader.h" diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 4c0b692c9e..f969850f87 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "s390x-internal.h" #include "tcg_s390x.h" diff --git a/target/sh4/helper.c b/target/sh4/helper.c index b8774e046e..7567e6c8b6 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/log.h" diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 9898752eb0..a64412e6bd 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -19,7 +19,7 @@ #include "qemu/log.h" #include "hw/registerfields.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "fpu/softfloat-helpers.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f64699b116..4824b97e37 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -28,7 +28,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" From patchwork Sat Mar 8 22:58:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8FABCC28B2E for ; Sat, 8 Mar 2025 23:06:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr38y-0004qP-LO; Sat, 08 Mar 2025 17:59:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 10/23] exec: Declare tlb_hit*() in 'exec/cputlb.h' Date: Sat, 8 Mar 2025 14:58:49 -0800 Message-ID: <20250308225902.1208237-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-20-philmd@linaro.org> --- include/exec/cpu-all.h | 23 ----------------------- accel/tcg/cputlb.c | 23 +++++++++++++++++++++++ 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 9e6724097c..8cd6c00cf8 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -179,29 +179,6 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); -/** - * tlb_hit_page: return true if page aligned @addr is a hit against the - * TLB entry @tlb_addr - * - * @addr: virtual address to test (must be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) -{ - return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); -} - -/** - * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr - * - * @addr: virtual address to test (need not be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) -{ - return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); -} - #endif /* !CONFIG_USER_ONLY */ /* Validate correct placement of CPUArchState. */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c8761683a0..fb22048876 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1201,6 +1201,29 @@ void tlb_set_page(CPUState *cpu, vaddr addr, prot, mmu_idx, size); } +/** + * tlb_hit_page: return true if page aligned @addr is a hit against the + * TLB entry @tlb_addr + * + * @addr: virtual address to test (must be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) +{ + return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); +} + +/** + * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr + * + * @addr: virtual address to test (need not be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) +{ + return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); +} + /* * Note: tlb_fill_align() can trigger a resize of the TLB. * This means that all of the caller's prior references to the TLB table From patchwork Sat Mar 8 22:58:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E6F5C282EC for ; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 11/23] exec: Declare tlb_flush*() in 'exec/cputlb.h' Date: Sat, 8 Mar 2025 14:58:50 -0800 Message-ID: <20250308225902.1208237-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Message-ID: <20241114011310.3615-19-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/exec/cputlb.h | 200 +++++++++++++++++++++++++-- include/exec/exec-all.h | 184 ------------------------ accel/tcg/tcg-accel-ops.c | 2 +- cpu-target.c | 1 + hw/intc/armv7m_nvic.c | 2 +- hw/ppc/spapr_nested.c | 1 + hw/sh4/sh7750.c | 1 + system/watchpoint.c | 3 +- target/alpha/sys_helper.c | 2 +- target/arm/helper.c | 1 + target/arm/tcg/tlb-insns.c | 2 +- target/hppa/mem_helper.c | 1 + target/i386/helper.c | 2 +- target/i386/machine.c | 2 +- target/i386/tcg/fpu_helper.c | 2 +- target/i386/tcg/misc_helper.c | 2 +- target/i386/tcg/system/misc_helper.c | 2 +- target/i386/tcg/system/svm_helper.c | 2 +- target/loongarch/tcg/csr_helper.c | 2 +- target/microblaze/mmu.c | 2 +- target/mips/system/cp0.c | 2 +- target/mips/tcg/system/cp0_helper.c | 2 +- target/openrisc/sys_helper.c | 1 + target/ppc/helper_regs.c | 2 +- target/ppc/misc_helper.c | 1 + target/riscv/csr.c | 1 + target/riscv/op_helper.c | 1 + target/riscv/pmp.c | 2 +- target/s390x/gdbstub.c | 2 +- target/s390x/sigp.c | 1 + target/s390x/tcg/mem_helper.c | 1 + target/s390x/tcg/misc_helper.c | 1 + target/sparc/ldst_helper.c | 1 + target/xtensa/mmu_helper.c | 1 + 34 files changed, 224 insertions(+), 211 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index cdfaf17403..8125f6809c 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -25,21 +25,14 @@ #include "exec/memattrs.h" #include "exec/vaddr.h" -#ifdef CONFIG_TCG - -#if !defined(CONFIG_USER_ONLY) -/* cputlb.c */ +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); #endif -#endif /* CONFIG_TCG */ - #ifndef CONFIG_USER_ONLY - void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); - #endif /** @@ -101,4 +94,193 @@ void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, int mmu_idx, vaddr size); -#endif +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) +/** + * tlb_flush_page: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of the specified CPU, for all + * MMU indexes. + */ +void tlb_flush_page(CPUState *cpu, vaddr addr); + +/** + * tlb_flush_page_all_cpus_synced: + * @cpu: src CPU of the flush + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of all CPUs, for all + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); + +/** + * tlb_flush: + * @cpu: CPU whose TLB should be flushed + * + * Flush the entire TLB for the specified CPU. Most CPU architectures + * allow the implementation to drop entries from the TLB at any time + * so this is generally safe. If more selective flushing is required + * use one of the other functions for efficiency. + */ +void tlb_flush(CPUState *cpu); + +/** + * tlb_flush_all_cpus_synced: + * @cpu: src CPU of the flush + * + * Flush the entire TLB for all CPUs, for all MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_all_cpus_synced(CPUState *src_cpu); + +/** + * tlb_flush_page_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, + uint16_t idxmap); + +/** + * tlb_flush_page_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of all CPUs, for the specified + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap); + +/** + * tlb_flush_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @wait: If true ensure synchronisation by exiting the cpu_loop + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); + +/** + * tlb_flush_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from the TLB of all CPUs, for the specified + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); + +/** + * tlb_flush_page_bits_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * Similar to tlb_flush_page_mask, but with a bitmap of indexes. + */ +void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap, + unsigned bits); + +/** + * tlb_flush_range_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of the start of the range to be flushed + * @len: length of range to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), + * comparing only the low @bits worth of each virtual page. + */ +void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxmap, + unsigned bits); +#else +static inline void tlb_flush_page(CPUState *cpu, vaddr addr) +{ +} +static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr) +{ +} +static inline void tlb_flush(CPUState *cpu) +{ +} +static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) +{ +} +static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, + vaddr addr, uint16_t idxmap) +{ +} + +static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) +{ +} +static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + uint16_t idxmap) +{ +} +static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, + uint16_t idxmap) +{ +} +static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, + vaddr addr, + uint16_t idxmap, + unsigned bits) +{ +} +static inline void +tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bits) +{ +} +static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits) +{ +} +static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxmap, + unsigned bits) +{ +} +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ +#endif /* CPUTLB_H */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a3aa8448d0..a758b7a843 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -27,190 +27,6 @@ #include "exec/mmu-access-type.h" #include "exec/translation-block.h" -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) -/* cputlb.c */ -/** - * tlb_flush_page: - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of the specified CPU, for all - * MMU indexes. - */ -void tlb_flush_page(CPUState *cpu, vaddr addr); -/** - * tlb_flush_page_all_cpus_synced: - * @cpu: src CPU of the flush - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of all CPUs, for all - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); -/** - * tlb_flush: - * @cpu: CPU whose TLB should be flushed - * - * Flush the entire TLB for the specified CPU. Most CPU architectures - * allow the implementation to drop entries from the TLB at any time - * so this is generally safe. If more selective flushing is required - * use one of the other functions for efficiency. - */ -void tlb_flush(CPUState *cpu); -/** - * tlb_flush_all_cpus_synced: - * @cpu: src CPU of the flush - * - * Flush the entire TLB for all CPUs, for all MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_all_cpus_synced(CPUState *src_cpu); -/** - * tlb_flush_page_by_mmuidx: - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of the specified CPU, for the specified - * MMU indexes. - */ -void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_page_by_mmuidx_all_cpus_synced: - * @cpu: Originating CPU of the flush - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of all CPUs, for the specified - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_by_mmuidx: - * @cpu: CPU whose TLB should be flushed - * @wait: If true ensure synchronisation by exiting the cpu_loop - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from the TLB of the specified CPU, for the specified - * MMU indexes. - */ -void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); -/** - * tlb_flush_by_mmuidx_all_cpus_synced: - * @cpu: Originating CPU of the flush - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from the TLB of all CPUs, for the specified - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); - -/** - * tlb_flush_page_bits_by_mmuidx - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of mmu indexes to flush - * @bits: number of significant bits in address - * - * Similar to tlb_flush_page_mask, but with a bitmap of indexes. - */ -void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bits); - -/* Similarly, with broadcast and syncing. */ -void tlb_flush_page_bits_by_mmuidx_all_cpus_synced - (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits); - -/** - * tlb_flush_range_by_mmuidx - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of the start of the range to be flushed - * @len: length of range to be flushed - * @idxmap: bitmap of mmu indexes to flush - * @bits: number of significant bits in address - * - * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), - * comparing only the low @bits worth of each virtual page. - */ -void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits); - -/* Similarly, with broadcast and syncing. */ -void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxmap, - unsigned bits); - -#else -static inline void tlb_flush_page(CPUState *cpu, vaddr addr) -{ -} -static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr) -{ -} -static inline void tlb_flush(CPUState *cpu) -{ -} -static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) -{ -} -static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, - vaddr addr, uint16_t idxmap) -{ -} - -static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) -{ -} -static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - uint16_t idxmap) -{ -} -static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, - uint16_t idxmap) -{ -} -static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, - vaddr addr, - uint16_t idxmap, - unsigned bits) -{ -} -static inline void -tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bits) -{ -} -static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits) -{ -} -static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxmap, - unsigned bits) -{ -} -#endif - #if defined(CONFIG_TCG) /** diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 132c5d1461..53e580d128 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -33,7 +33,7 @@ #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "qemu/timer.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/hwaddr.h" #include "exec/tb-flush.h" #include "exec/translation-block.h" diff --git a/cpu-target.c b/cpu-target.c index 5aa6c4b0c6..b6e66d5ac0 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -31,6 +31,7 @@ #include "exec/tswap.h" #include "exec/replay-core.h" #include "exec/cpu-common.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/tb-flush.h" #include "exec/log.h" diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 5fd0760982..7212c87c68 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -22,7 +22,7 @@ #include "system/runstate.h" #include "target/arm/cpu.h" #include "target/arm/cpu-features.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/memop.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 7def8eb73b..23958c6383 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -1,6 +1,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "helper_regs.h" #include "hw/ppc/ppc.h" #include "hw/ppc/spapr.h" diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 8892eaddcb..6faf0e3ca8 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -36,6 +36,7 @@ #include "hw/sh4/sh_intc.h" #include "hw/timer/tmu012.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "trace.h" typedef struct SH7750State { diff --git a/system/watchpoint.c b/system/watchpoint.c index 2aa2a9ea63..08dbd8483d 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -19,7 +19,8 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" +#include "exec/target_page.h" #include "hw/core/cpu.h" /* Add a watchpoint. */ diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index 54ee93f34c..51e3254428 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/helper-proto.h" #include "system/runstate.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index 71dead7241..e786c8df5f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -18,6 +18,7 @@ #include "qemu/timer.h" #include "qemu/bitops.h" #include "qemu/qemu-print.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/translation-block.h" #include "hw/irq.h" diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index fadc61a76e..630a481f0f 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -7,7 +7,7 @@ */ #include "qemu/osdep.h" #include "qemu/log.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "cpu.h" #include "internals.h" #include "cpu-features.h" diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 304f0b61e2..fb1d93ef1f 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "hw/core/cpu.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index 3bc15fba6e..c07b1b16ea 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qapi/qapi-events-run-state.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/translation-block.h" #include "system/runstate.h" #ifndef CONFIG_USER_ONLY diff --git a/target/i386/machine.c b/target/i386/machine.c index d9d4f25d1a..70f632a36f 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1,6 +1,6 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "hw/isa/isa.h" #include "migration/cpu.h" #include "kvm/hyperv.h" diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4858ae9a5f..c1184ca219 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -21,7 +21,7 @@ #include #include "cpu.h" #include "tcg-cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index ed4cda8001..2b5f092a23 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "helper-tcg.h" /* diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/misc_helper.c index c9c4d42f84..ce18c75b9f 100644 --- a/target/i386/tcg/system/misc_helper.c +++ b/target/i386/tcg/system/misc_helper.c @@ -23,7 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "tcg/helper-tcg.h" #include "hw/i386/apic.h" diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/svm_helper.c index 5f95b5227b..f9982b72d1 100644 --- a/target/i386/tcg/system/svm_helper.c +++ b/target/i386/tcg/system/svm_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "tcg/helper-tcg.h" diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c index 6c95be9910..84f7ff25f6 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -12,7 +12,7 @@ #include "internals.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "hw/irq.h" #include "cpu-csr.h" diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 2423ac6172..f8587d5ac4 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" static unsigned int tlb_decode_size(unsigned int f) diff --git a/target/mips/system/cp0.c b/target/mips/system/cp0.c index bae37f515b..ff7d3db00c 100644 --- a/target/mips/system/cp0.c +++ b/target/mips/system/cp0.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" /* Called for updates to CP0_Status. */ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) diff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/cp0_helper.c index 79a5c833ce..01a07a169f 100644 --- a/target/mips/tcg/system/cp0_helper.c +++ b/target/mips/tcg/system/cp0_helper.c @@ -27,7 +27,7 @@ #include "internal.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" /* SMP helpers. */ diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 77567afba4..21bc137ccc 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/helper-proto.h" #include "exception.h" #ifndef CONFIG_USER_ONLY diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 3ad4273c16..f211bc9830 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "qemu/main-loop.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "system/kvm.h" #include "system/tcg.h" #include "helper_regs.h" diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index f0ca80153b..e379da6010 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0ebcca4597..49566d3c08 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -25,6 +25,7 @@ #include "pmu.h" #include "time_helper.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/tb-flush.h" #include "system/cpu-timers.h" #include "qemu/guest-random.h" diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f156bfab12..0d4220ba93 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "trace.h" diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 85ab270dad..b0841d44f4 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -24,7 +24,7 @@ #include "qapi/error.h" #include "cpu.h" #include "trace.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 6879430adc..6bca376f2b 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "s390x-internal.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/gdbstub.h" #include "gdbstub/helpers.h" #include "qemu/bitops.h" diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index cf53b23291..6a4d9c5081 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -15,6 +15,7 @@ #include "system/hw_accel.h" #include "system/runstate.h" #include "exec/address-spaces.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "system/tcg.h" #include "trace.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index ea9fa64d6b..8187b917ba 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -26,6 +26,7 @@ #include "exec/helper-proto.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 0245451472..31266aeda4 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/timer.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "qapi/error.h" #include "tcg_s390x.h" diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 4c54e45655..b559afc9a9 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -24,6 +24,7 @@ #include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #ifdef CONFIG_USER_ONLY diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 29b84d5dbf..63be741a42 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -32,6 +32,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" From patchwork Sat Mar 8 22:58:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 12/23] system: Build watchpoint.c once Date: Sat, 8 Mar 2025 14:58:51 -0800 Message-ID: <20250308225902.1208237-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that watchpoint.c uses cputlb.h instead of exec-all.h, it can be built once. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- system/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/system/meson.build b/system/meson.build index 4952f4b2c7..c83d80fa24 100644 --- a/system/meson.build +++ b/system/meson.build @@ -3,7 +3,6 @@ specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: [files( 'ioport.c', 'memory.c', 'physmem.c', - 'watchpoint.c', )]) system_ss.add(files( @@ -24,6 +23,7 @@ system_ss.add(files( 'runstate.c', 'tpm-hmp-cmds.c', 'vl.c', + 'watchpoint.c', ), sdl, libpmem, libdaxctl) if have_tpm From patchwork Sat Mar 8 22:58:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98202C282EC for ; Sat, 8 Mar 2025 23:06:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr395-0004sI-GZ; Sat, 08 Mar 2025 17:59:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38W-0004ae-Ih for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:16 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tr38U-0005Mn-6D for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:15 -0500 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-223959039f4so60749705ad.3 for ; Sat, 08 Mar 2025 14:59:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741474753; x=1742079553; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ckxZuevLuUfuaGbBEffRCMPAF7260cqu8cz/74iaKKY=; b=dMdfAOqUIzYd8XuX2TUOdcuBgDHiHLqlqkvneHVB8l8Pm4zU4xT6id6Wf+/w/xA9FD dP0kPokLR7ChkWdaFrVUhQkttSketrP/USWKKcoSFfufy2LH1P9WsoCtEuLkqme2LZAW +K6FlAns+byKfLIbot3HqXX9v4kR8AypRrj4Ui3ugtZij+w4JQHflStQKtDcelRPo4Kw Xyeh8roLme5aP25cYhSh0mPZsKKHN4zFz535bEJZEcUD0r9USPQbDpIrEI2O13VO6KSU gRU8bHZ7lyQuawDGHT7enQWPcvUE8eeFQGS/0sh7zQURTQTivTkEZ0maDGkG7Ho6sV5o Bsbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741474753; x=1742079553; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ckxZuevLuUfuaGbBEffRCMPAF7260cqu8cz/74iaKKY=; b=li8wmfVKDrJ4o4eo5PMBMpMG1h6VoBrjDMSZlXRaAMlpeIpeZd4vUhTrlwId1BRmLJ C/pRtCNzFckAAMu/E87T5PmjvjHyMt/p0UhWz0ujggTD/0C2SCJ0vGiMXYIDu27uBn4f 0nkAWqIQ82caUaDl2WFh7KxKgLypTBVGaMryPc8Kl+7mQ4Gnf/D/NFWLCTg5O75sQAFO nTWPK48/NLwS6iZ6/Vkb2tWel/aJ+ob+HYzmCnp4dmCqremHhHWriqv+74qdzcchRuUN 24yRL2q1zFoX/Q6LRe3MjGi6SruRenCrJZWS8fVAUfB6HRX+/Owqm7LHUW63n/ZJtutF 6dzA== X-Gm-Message-State: AOJu0YwbldDZR3cpWKsVd0H6EbW9otlFznnGnzUOcMCgdIKWtYbL2DI4 sBkfnDarO+E2AgvXBGeY5GKXxAX6uHUDJhE9/htCaHlEkR+b/ZqsprZ8GZniKBBK3uPqL4pd29E j X-Gm-Gg: ASbGncvGSz8X6vEdAE+ZnIEdTZ+ZAtoP0crXpnXQvKgSzpzWixrc7D9dKqvWqdXvr64 0+/GYC4udx/ny1+JYAkWgOzapLwHsPJHGAomWl2PFnHiIYNRE/nruTj/n6dkZTgsOKURwySvXLE PWOQCTKYdRtF8J46l9JzD2s/M+7EDsfqlPXCvcJ/e9SqRHJykhkK4tuEpEcJDJvpBEVMgclqA0D PS/3S43CnXNKVdRLd5kop366JuhItQFXK7ZNoZJ7M5e6kdzpsmgc/CGsA9V277sWf7B+r98czyg ng9K/7VDJ56cOyP3sKF7ksv44hT01bcVxjbwEbuAckJj2/8lMHXfRYq8ax+rmKHJa3YdaAxm6LD D X-Google-Smtp-Source: AGHT+IEiEYoPRMQxBxzxapygUV9DqIGFTjIgyouF3X0bt8oGs1CIHm+RpSU34EdBYwPlrJ4B2vqmVQ== X-Received: by 2002:a17:902:e80e:b0:223:669f:ca2d with SMTP id d9443c01a7336-22428bd5819mr141040385ad.35.1741474752759; Sat, 08 Mar 2025 14:59:12 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 13/23] accel/tcg: Build tcg-accel-ops.c once Date: Sat, 8 Mar 2025 14:58:52 -0800 Message-ID: <20250308225902.1208237-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that tcg-accel-ops.c uses cputlb.h instead of exec-all.h, it can be built once. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 979ce90eb0..70ada21f42 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', - 'tcg-accel-ops.c', 'tcg-accel-ops-mttcg.c', 'tcg-accel-ops-icount.c', 'tcg-accel-ops-rr.c', @@ -29,5 +28,6 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', 'monitor.c', + 'tcg-accel-ops.c', 'watchpoint.c', )) From patchwork Sat Mar 8 22:58:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56A3FC282EC for ; Sat, 8 Mar 2025 23:06:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr38y-0004qN-9b; Sat, 08 Mar 2025 17:59:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38X-0004bE-Ty for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:17 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tr38V-0005My-3h for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:17 -0500 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-223fd89d036so60316795ad.1 for ; Sat, 08 Mar 2025 14:59:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741474753; x=1742079553; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RZdIHDSHGx7DjYFPOKN73GJ/ocYoTkMO/3fUlNv68hU=; b=S85kEc3bMa1xDjtFsc/k9EQEcYnGSLgb+xwlAAQGk4jmSEYu3JgObDweviuOD/72Y4 T2Hw3Owk2jbPlcpkxzdVA60IiVojxHhRnVlDvbpdbCx+CV/0cEosWvJHbKNb1Jx6lc9j Y6Ke6rTpvpBLtfOBZ4QGgbkkyZ290+IoG1WC3rbcLhqrHzBjNox8b79ZlGa3y7iv3bX3 a0KZd2So/c+goNjy55thNdYZU1De4NyMQMyroddgBUNEeZJovqpdUlKH0xfvDC8AhLhs MabyzCAl/9QXauAFImb3aWIiKgSVHru0FVQ8b6txHhqpvEc6RW/ylRrDuX1HBlCeU2O4 yFww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741474753; x=1742079553; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RZdIHDSHGx7DjYFPOKN73GJ/ocYoTkMO/3fUlNv68hU=; b=gvdwBvwu46JIe39spNZfOBBM91wTi6wwzdXO7EVEft/bU7dwMpZBqHLHT1QlHPB5dD aA8Iu8UgJUre7qdEwqNGpl2HnFqIJvwJ/6ejarTNEtSbAQqd4TmiefDButeVXtiAn25w BOZKUp3bpQO4h+MJ7NMBK+uzskzOVAo1JLW6ns7S80Z2QFLu2Fiytt9hHUKJ1PG3G/da OtwLdKjlTW5VwBsAzsEIBgIYuMa7Cr9SxJAMALKCpCk6VVcT+DgGr19VKsKHK6mIE5gH vntDasmsicZFeFaQ3oGV5hzF/VsAmy8NCeq9/3ClKokZCW9qf+ogR2rUAMZiqGz8wWIn b/+g== X-Gm-Message-State: AOJu0YyPOGpWjBYjAmcqj6ytmgOIuDXTpiKB0l1DlbYFJhwnFqWyS21h tPoJmBZVWLkwfDC1U6iaxvGrWCLoaIwuJb/2yR2UMnoWGWJwa8ZNCvgPm8cMvfRLcrOYTq2RonB V X-Gm-Gg: ASbGncsYX7Gk39BgEsL9mtq8XCQOmdXredwUYg/Qk7IwTki6DkpkFRB15RPbMVBLGt2 p8l3JkN4/xeVhehRh4SgomrWb8kWfmJfkxOEYUy6Aini37X7KfRcQfCrR64CEKAEiy+dGwegplV QhNnGTkQyAS9qOIi33hBj81jv8UEabewWADs2LFNCKhMTX921gz2iKvcsyw3e76BuhoiXaJcFhK 7Fy1coJREUlubz43rPg4i6fphKpfNTrL8Tiyl4KnWxwmFPTU/hk4K3+osybCTI6k+IR1eSFoeCA cM8gg4x0TZINEOCUtnCprSeUQbITKZtMFw1L7YckDQbJ+C7hm9DmPeSQ0h5h1j2Gc72W+8334+o t X-Google-Smtp-Source: AGHT+IE21d60jB2o9YAF2moE+D60odVDqouNX0EtxQaAYpWS+O4td3+raYZept6mJ3O2QXKgVSmDbg== X-Received: by 2002:a17:902:f689:b0:223:5645:8e1a with SMTP id d9443c01a7336-22428c1cd3emr105428625ad.51.1741474753372; Sat, 08 Mar 2025 14:59:13 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 14/23] accel/tcg: Build tcg-accel-ops-icount.c once Date: Sat, 8 Mar 2025 14:58:53 -0800 Message-ID: <20250308225902.1208237-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All that is required is to avoid including exec-all.h. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tcg-accel-ops-icount.c | 2 +- accel/tcg/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c index d6b472a0b0..27cf1044c7 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -28,7 +28,7 @@ #include "system/cpu-timers.h" #include "qemu/main-loop.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" +#include "hw/core/cpu.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-icount.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 70ada21f42..891b724eb6 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -21,7 +21,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', 'tcg-accel-ops-mttcg.c', - 'tcg-accel-ops-icount.c', 'tcg-accel-ops-rr.c', )) @@ -29,5 +28,6 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', 'monitor.c', 'tcg-accel-ops.c', + 'tcg-accel-ops-icount.c', 'watchpoint.c', )) From patchwork Sat Mar 8 22:58:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19271C282EC for ; Sat, 8 Mar 2025 23:02:27 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr39W-0005Gl-Jb; Sat, 08 Mar 2025 18:00:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38Y-0004bM-47 for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:18 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tr38W-0005N4-8Y for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:17 -0500 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-22438c356c8so24061475ad.1 for ; Sat, 08 Mar 2025 14:59:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741474754; x=1742079554; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eHwc77IufCe9x4orDpSXC5RbYlXYJFooG8dZmFw32y4=; b=ic+vU4cmT3reUaa15NL/SW0dcHsC9vNZZH8jF4X8C77PirjnHM3vgg4yGo0WNQd1XL hIxB2CHl1ITzZPEXbj0cN9mAL6FKGLq+eTPw8BQJ4xwbkkYKnPh+Jndkd6v3bkGY1W6c XSp8fArG3fbDZtV1iFJp4r21T8Kso2NxoIyEAV0kMbyyD1eeGzXEyMsfBryxYBF0J1BK KgXVWBoMbWyiX4HXYtw9fjAXwwSOLU4eKQjNOOH58KtptqBem3RYRRu+ItzePHSkNJAP BA2+PyCLOdl2OiHbI/Quknhow8+1AWs+nHP22qQ2al4QZ8p+FO7tafpSm9w93DhSscJT UF2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741474754; x=1742079554; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eHwc77IufCe9x4orDpSXC5RbYlXYJFooG8dZmFw32y4=; b=mFi2oTNDvZFOFI15cKrFZcJbQODw7Q6fVDY2tiaGUX05cii/J9e8fQ4jAaRthnWLW7 9hMA9QLevTJjklFKpvezk3wTJh0xFL3XL0fnTr7N/qIx60hj27tBCAH50TDpiqiIntth LJCw/4GMKkjkEymnHUYR1ZRfy/KVN1N9jRnLUmxmkLcr1rGr/MJvK0Kkf2APwJ3prIu/ t7+b8ABByM4ewWzTQoX8BzMn6tdpoFZ4dICain+aERfbB8af2pJkMHqsi2ARwfjoJCKm dpjJ7OVi4JezUVTYCfOjz+IdI3K1gWBmYXOFfuJ/gIg852wSaDwsPBlLFdgWDJx3MUkG FF8g== X-Gm-Message-State: AOJu0Yx9Fbs0Y0MZP3KDujhAV4ZFUOnhE0oVHuCP/XFAOIrDjq8D5GrS 1fqtOS+cqBSGTJZzWVQEzBMyfnL+bR98EqkKRBDMXlBqDg1bsoSBmWDKgcmae/hiHiE52L9W3DJ 5 X-Gm-Gg: ASbGnctGFs2Q69PLZ4Hz8WMyizMPkiPpkNwCHU/xNyMPnW4w/8V33JBUHMulcOYbEuQ yX+ghzrR/oWrfzyYJq5MirrGh99tG9HTJi53sxqbF/MGOn7trROQ/aJhZ1qt52hNySCwa+Ufp1i WpBAsIp/CP0xCqpLrwtxYMViM8i9lbap3Kr4FRSbs5awrsDxUhpi+odc+gGXbO8ty9ANEKuRPa7 7hgeUYA05YzYRwGahytRr0Zd+loHwDv1ezT9lRi5Aq9zgtYEyli/pRdrWtwKQa7ZMxZ6B7fTv5B fJWXZT4urUqHuZi9D25PK8wHBzdvXBWFqZM/1jNXFhxgde5GsiOwbvtsn/iyhPppRCgDyq0fQEh J X-Google-Smtp-Source: AGHT+IEgMclFE7Cbr/jsyychjDSp0NlXatKf6N0/X+VEUMITu7jff8kQm8mQPJPD9/5anny8ARZ/qA== X-Received: by 2002:a17:902:ec89:b0:224:10a2:cad9 with SMTP id d9443c01a7336-22428bd5852mr161240585ad.41.1741474753969; Sat, 08 Mar 2025 14:59:13 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 15/23] accel/tcg: Build tcg-accel-ops-rr.c once Date: Sat, 8 Mar 2025 14:58:54 -0800 Message-ID: <20250308225902.1208237-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All that is required is to use cpu-common.h instead of exec-all.h. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tcg-accel-ops-rr.c | 2 +- accel/tcg/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 028b385af9..f62cf24e1d 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -31,7 +31,7 @@ #include "qemu/main-loop.h" #include "qemu/notify.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" +#include "exec/cpu-common.h" #include "tcg/startup.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-rr.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 891b724eb6..87c1394b62 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -21,7 +21,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', 'tcg-accel-ops-mttcg.c', - 'tcg-accel-ops-rr.c', )) system_ss.add(when: ['CONFIG_TCG'], if_true: files( @@ -29,5 +28,6 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'monitor.c', 'tcg-accel-ops.c', 'tcg-accel-ops-icount.c', + 'tcg-accel-ops-rr.c', 'watchpoint.c', )) From patchwork Sat Mar 8 22:58:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BDBE7C282EC for ; Sat, 8 Mar 2025 23:00:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr39C-000514-L2; Sat, 08 Mar 2025 17:59:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38Y-0004bL-4e for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:18 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tr38W-0005NA-8i for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:17 -0500 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-224100e9a5cso56104845ad.2 for ; Sat, 08 Mar 2025 14:59:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741474754; x=1742079554; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PQ7VRfSKG1Ts2qHzv0Mc2UE7mllYcyWQa1NNvIfU4kY=; b=FjmXOQR/sVWs+avbB2i2yPM+IpctSSh5ibddNdlXm3T9460Wc52+3/fWTo28DeCm4k ON7HzQG39ZZxG5qDyRAOVrrt28JGIYYHUMgikNu2aN6zbm6eF6DAnjQTIaai8PL0M2Xg qbi26fQJbgFzX7g00s7abPi7opyJKXSmOBjza4YfWeIlJmFDrhhP9W4GCq5gfXnpcQ57 LYMgcZCIimBDaoaR05KrpJnqxjuudgkVPapVG7tN7vMglIisMB5h+j6jiSZcc8LoN+sr Afn+fxUEU2Jxtr37pReID1P6sPnilX7rpghwito0yTt1tkYo5ADhhSwajhzs75csbgf2 MAQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741474754; x=1742079554; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PQ7VRfSKG1Ts2qHzv0Mc2UE7mllYcyWQa1NNvIfU4kY=; b=dLY+XVREQv21FfEqotKo9Y8sqlUE8z0boMWl16u1WyBMezSHhBmXhDxjv8D9vnTSso 3Uo3EqxTaIteuFCARzBRDIcPDiHjGUUlKDBPevQAwLbSb+mrmrwl2YfzI6qei69cG/DC vxRfg7Dm3tjlhdhAN5dMic4LuVdRe5qUec5zyYlVrd/luOKNeN0MIjCNM2a8zJrH6sQV cEvcKZGMD0YGjB0YoZzeZJ9Eg4srsCq5Ia/wqFmmJSLpNzRRz9tyk625woRYymGT/d5D t9H62AqG5bPSQ3n1A5jIPT+FIbjJxfqrNMjOFZj0ZXFtXTByS9/Al1TKn3RlIr9ocToq PE8A== X-Gm-Message-State: AOJu0Yyo+gBXATyoEkBYsarwXeq4Vfv4RuQ8PcJdTfq7ssfnLdgwfu/O 3j6SnIneEBiWwY/f0EldD0YA6tKalF989vCl2A7xeApWav4ZllOz9W66F6Gtv536bRYJ4ljKB9L H X-Gm-Gg: ASbGncse6uMg8kVnENnUdqmJ+C/MDznS0kJ14LrDQw5rKnz1Vw6Gjmm6+hS+vXiRL40 lDy0NzO7sSEG0ahOdHyEcY+t7ig5JRb9ftoGrmFLFvQAbxjGUkhr6gEOtEau51DiKuKbJJfB+ex LvR6yezMTCvbS3w+2KWcFRQB/MBEq165Shze6/tmgGsr+rQF3Oofb7L8euiG4MYzf3zy7NqSc4+ d4oOmDCJPP+HucVsnlVvXzzatMYAw5Au2z1RhJqIbIouUfSEjYGsLmXD64d/6K0SVYaEoi2gLHP aTpKnaJdy6RrqO8kMslzuPBsqsztmSPiaAEv93XYDJV8qRJ/+7WiFPMeN+oScSa/yoNZzVxfkDN Z X-Google-Smtp-Source: AGHT+IERSo3yeN1yI+8Yqb936MopykyHrFDIBOzqTPWwZuMtjqnS03zdsQTnG9yU1ENTIyh07wIjsg== X-Received: by 2002:a17:903:40cb:b0:223:44c5:4eb8 with SMTP id d9443c01a7336-22428c0752cmr146211635ad.32.1741474754592; Sat, 08 Mar 2025 14:59:14 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 16/23] accel/tcg: Build tcg-accel-ops-mttcg.c once Date: Sat, 8 Mar 2025 14:58:55 -0800 Message-ID: <20250308225902.1208237-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All that is required is to avoid including exec-all.h. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tcg-accel-ops-mttcg.c | 1 - accel/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c index ba7cf6819d..bdcc385ae9 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -30,7 +30,6 @@ #include "qemu/main-loop.h" #include "qemu/notify.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" #include "hw/boards.h" #include "tcg/startup.h" #include "tcg-accel-ops.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 87c1394b62..81fb25da5c 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', - 'tcg-accel-ops-mttcg.c', )) system_ss.add(when: ['CONFIG_TCG'], if_true: files( @@ -28,6 +27,7 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'monitor.c', 'tcg-accel-ops.c', 'tcg-accel-ops-icount.c', + 'tcg-accel-ops-mttcg.c', 'tcg-accel-ops-rr.c', 'watchpoint.c', )) From patchwork Sat Mar 8 22:58:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA86DC282EC for ; Sat, 8 Mar 2025 23:05:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr39e-0005oC-25; Sat, 08 Mar 2025 18:00:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38Z-0004cj-At for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:19 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tr38X-0005NP-27 for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:19 -0500 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-22401f4d35aso55290645ad.2 for ; Sat, 08 Mar 2025 14:59:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741474755; x=1742079555; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pLDUWdvnnBB356eedHeiVggZlsL+ljood1zAHBJkFew=; b=Rm3+vDtt63gVMmcgLcp6g1ngRsh2cyRRnHulV8Y0JmlD9prC8hYyELdDCtASrmvdxK 2XSHG3DFRbTWVmgHEz727aaSdVpa9lYPLtkIkz1ByQR/it/xUfjuO2j6jOaflVD9yHyv eA3wPk99o6hrtfzrz0MB40B9c7jfstgO7Sb3wiOE83ba3nLqr78A/dUi7K+a/wAiu0mB AFKvRhQXdhRJfWN0MnoivWCvVv7VSQ61+730UIV/JOtM8l/iq05a1RkcNAjW0DxdVLiN 9adH5Wp/rzcEBAuCTufqB575KQxr1sjghZz1Dm6y3UO+gnvUI2tfFmN5UdXB3Y+M3H0b f7uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741474755; x=1742079555; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pLDUWdvnnBB356eedHeiVggZlsL+ljood1zAHBJkFew=; b=Sx9aOt4YmiWxmyD1mhfsLdnkHqZtxw9a/tS3UFRuKyuAGlJjZb2UeGjoXdhCik/RgF PZjv7BedGn6WWL9UIERdGbzfLHJkH4uUATFTlcgLApTlPC4jWVxjuN1aOmqPGcTRVQoU 9UHh0rzMnDLlsTb8AlMh/IMIPXN2untDIC93LXzHmvTsSY0IOyPgdm10TEpQXTrwUyW7 Wn3Y6NYqRKpifqe5BTMzXvrgEPQlA0nJfUJMSt7hr3GBjZbtHz5IlYBBUsNDXKTkQ4g7 M/xHxxtBEC4LxIj80EGOphBeXuvgKpJKF3YFxAjkdv6DYgTUPtmJrnRDza1JvkI5wQ0c C/JA== X-Gm-Message-State: AOJu0Yy03mifMBc3cEMbduMp7MiURWAGs/Ouhjq6YftusmplMSIRGo4h jN0Y3kPqOiIVogjvKmsV6Vtzph8u1RmuWZbyUGEmlfiDDT5rcVbk1vYw4nv01fKXqEs8mCTJxUD Q X-Gm-Gg: ASbGnctffzElIjVPDq143b8NLxtUQU0tmaS+2ZpOiSHu2argmdw7e41aWz66ufYnkPM EWDQhpkCKJ/GpBg7svQKLcUd+S19EvUow9etaoydgg38qvOTzYSOGglC+Un9STrrc3igrVGjjRG K1+/rI60amXNV2eHc9otw6aubzTndp6qlh3F4KfMkgnOo0lTS+ZYopbhv/vY36NER4xMocLSn4F eD8DBsqYztEKVTDtS3o1MngomC8BXWSOj1ubE0t6nZXsOzHL0370uL6na3xKjLHeGeZhkKk0GG1 zhnEUo5c2zFcdt0ndCFPbT0jn8y/DWMPoXk0nJCHCW4SMlM/qtusxah5NybnePcDuM2drmmFtTV 9 X-Google-Smtp-Source: AGHT+IHaQPXRYsw+ROqemtdEfbQtJ4SegmYcx6iDbcgH/6HAsUb4SKfHxpYSO2jDqICeqJJWkbDdnw== X-Received: by 2002:a17:902:ccc5:b0:223:f408:c3cf with SMTP id d9443c01a7336-224288971fcmr144299935ad.21.1741474755261; Sat, 08 Mar 2025 14:59:15 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 17/23] accel/tcg: Restrict GETPC_ADJ to 'tb-internal.h' Date: Sat, 8 Mar 2025 14:58:56 -0800 Message-ID: <20250308225902.1208237-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé GETPC_ADJ is only used within accel/tcg/, no need to expose it to all the code base. Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20250308072348.65723-2-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/tb-internal.h | 11 +++++++++++ include/exec/exec-all.h | 9 --------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index 62a59a5307..68aa8d17f4 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -13,6 +13,17 @@ #include "exec/exec-all.h" #include "exec/translation-block.h" +/* + * The true return address will often point to a host insn that is part of + * the next translated guest insn. Adjust the address backward to point to + * the middle of the call insn. Subtracting one would do the job except for + * several compressed mode architectures (arm, mips) which set the low bit + * to indicate the compressed mode; subtracting two works around that. It + * is also the case that there are no host isas that contain a call insn + * smaller than 4 bytes, so we don't worry about special-casing this. + */ +#define GETPC_ADJ 2 + #ifdef CONFIG_SOFTMMU #define CPU_TLB_DYN_MIN_BITS 6 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a758b7a843..2ac98e56c4 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -186,15 +186,6 @@ extern __thread uintptr_t tci_tb_ptr; ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) #endif -/* The true return address will often point to a host insn that is part of - the next translated guest insn. Adjust the address backward to point to - the middle of the call insn. Subtracting one would do the job except for - several compressed mode architectures (arm, mips) which set the low bit - to indicate the compressed mode; subtracting two works around that. It - is also the case that there are no host isas that contain a call insn - smaller than 4 bytes, so we don't worry about special-casing this. */ -#define GETPC_ADJ 2 - #if !defined(CONFIG_USER_ONLY) /** From patchwork Sat Mar 8 22:58:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 304EBC282EC for ; Sat, 8 Mar 2025 23:00:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr38u-0004jM-0y; Sat, 08 Mar 2025 17:59:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38c-0004fA-In for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:23 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tr38X-0005NY-JH for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:22 -0500 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-22113560c57so56984475ad.2 for ; Sat, 08 Mar 2025 14:59:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741474756; x=1742079556; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=svzUK2bXhs+AmT8lF2QtHzM82zox0Nlbc/AZRsQwWac=; b=KuirUA343UmB2asjx8QJh4Jg3UnIfH0I5ec1HWZeDCfNAnLOmme9KnEe7WGXoO5uqA xYXSKVswylvYCNQu4QR6tm4OoFbcNQAAZxonBDHkM59IX2w0bRuzWjsV60AcUuVj/jc6 DEl6f/6CA8kpRwQAAvayxD0zDYBp6P2iNpV7xw0n4QGmq3BL/VZ8l3DHwaI7hxkDqK94 tiCyrE8P9w40uUvT+lYKo0P0j9LC2t2GQxs84uNcIb3/v6GkDRYqS8ugRHr2tP1Sj1la h7UR3X9mkE+DP3QIwrk2kjoEEHbCdjAxZy/lOU0L5spBgpqrYCyR7+Wcqk1IFlu4b5UZ bWTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741474756; x=1742079556; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=svzUK2bXhs+AmT8lF2QtHzM82zox0Nlbc/AZRsQwWac=; b=tw9Nym6o/DRIlJhV776uWzBFNYw1kC4mlxwpncYiO4p+Rhdat4apm+sbIAER47OxBG D8UK/D3eHPIIfoOZSnDXIX7SE993vTP0HNnoBtAw+aXQAr/CZwEyMlbvTKTtAAFVRr/l 59dvPKkxYit+NWmcv4r12G8yWsgJbJJZ2uvZvMNJpF1oPkzt2MloBmd7f2kLdS6AoQYf nXYFmtIysCkK/wTmZliHvLzHdlgwHh0bv3Rg0mCd9ARxwiOtBgRPOpzdAu5YtYhnqwM8 WhTMswd0w6c7HxjTfyyziy8kSyE4rSrHm/egMguZzAOLvZM1+IDuvImrOVyQODYLbDJz EE9g== X-Gm-Message-State: AOJu0YyY9JENxqi77MHlvCmTYrZhyNO7vktH5i4l7098GkdtdzyoLHNy cCvPJQ8zZRMcM7dZCwz6g3macnMS6ouXgqlgCnULA6pCjoiCin2VSetWy21jL202Vi9zHSgZITI U X-Gm-Gg: ASbGncuxyuVRwNTYHIMKYG/cl51HdjMtSmh/r6gPEZ7k5i6oGFuZpq2S2TMLlC5YJkt 0THv29s55aBSOWNpFfL+SVZzZRC0ZqqRnKWdyGJTR2Drf0zTY+duDeOOy8AaiWXxwP7pPWjJin1 v1rrYWx2D9k4nmkyvGDuy0snuIhIyg6RbeF1CvgwtU6YM3jAkM9Ps0Y++rJ26lZ1JQ87YKzCpHa BQElvsNASa61S8+7RwkfDGOrWU2IY2JodZCZ1hF28LAiwDUiqM8VhbEC4wnqICtJO2S5nPOvq/Z uimbKRYLDOlt4ccxNd3+tUSYc6KlsSPzz2bd85G97DbQ09mIEOPkTdHxIyt+bA4/taPs9fWgBOj o X-Google-Smtp-Source: AGHT+IGg0tyL+QhYxEOtKPYKY+ZZEziEW3uRceSjy36AlfbHF1GPcevxGjWdvuJFc9J/7aZ9G9xyKg== X-Received: by 2002:a17:903:22c8:b0:224:256e:5e3f with SMTP id d9443c01a7336-22428993846mr139577155ad.25.1741474756248; Sat, 08 Mar 2025 14:59:16 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , =?utf-8?q?Philippe_Mathi?= =?utf-8?q?eu-Daud=C3=A9?= Subject: [PULL 18/23] accel/tcg: Split out getpc.h Date: Sat, 8 Mar 2025 14:58:57 -0800 Message-ID: <20250308225902.1208237-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Split out GETPC to a target-independent header. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20250308072348.65723-3-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/accel/tcg/getpc.h | 24 ++++++++++++++++++++++++ include/exec/exec-all.h | 10 +--------- 2 files changed, 25 insertions(+), 9 deletions(-) create mode 100644 include/accel/tcg/getpc.h diff --git a/include/accel/tcg/getpc.h b/include/accel/tcg/getpc.h new file mode 100644 index 0000000000..8a97ce34e7 --- /dev/null +++ b/include/accel/tcg/getpc.h @@ -0,0 +1,24 @@ +/* + * Get host pc for helper unwinding. + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_GETPC_H +#define ACCEL_TCG_GETPC_H + +#ifndef CONFIG_TCG +#error Can only include this header with TCG +#endif + +/* GETPC is the true target of the return instruction that we'll execute. */ +#ifdef CONFIG_TCG_INTERPRETER +extern __thread uintptr_t tci_tb_ptr; +# define GETPC() tci_tb_ptr +#else +# define GETPC() \ + ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) +#endif + +#endif /* ACCEL_TCG_GETPC_H */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2ac98e56c4..dd5c40f223 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -28,6 +28,7 @@ #include "exec/translation-block.h" #if defined(CONFIG_TCG) +#include "accel/tcg/getpc.h" /** * probe_access: @@ -177,15 +178,6 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last); void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); -/* GETPC is the true target of the return instruction that we'll execute. */ -#if defined(CONFIG_TCG_INTERPRETER) -extern __thread uintptr_t tci_tb_ptr; -# define GETPC() tci_tb_ptr -#else -# define GETPC() \ - ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) -#endif - #if !defined(CONFIG_USER_ONLY) /** From patchwork Sat Mar 8 22:58:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007954 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 69B18C282EC for ; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 19/23] qemu/atomic: Rename atomic128-cas.h headers using .h.inc suffix Date: Sat, 8 Mar 2025 14:58:58 -0800 Message-ID: <20250308225902.1208237-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented in the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename 'atomic128-cas.h' as 'atomic128-cas.h.inc'. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-ID: <20241212141018.59428-2-philmd@linaro.org> --- host/include/aarch64/host/atomic128-cas.h | 2 +- include/qemu/atomic128.h | 2 +- .../generic/host/{atomic128-cas.h => atomic128-cas.h.inc} | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename host/include/generic/host/{atomic128-cas.h => atomic128-cas.h.inc} (100%) diff --git a/host/include/aarch64/host/atomic128-cas.h b/host/include/aarch64/host/atomic128-cas.h index 58630107bc..991da4ef54 100644 --- a/host/include/aarch64/host/atomic128-cas.h +++ b/host/include/aarch64/host/atomic128-cas.h @@ -13,7 +13,7 @@ /* Through gcc 10, aarch64 has no support for 128-bit atomics. */ #if defined(CONFIG_ATOMIC128) || defined(CONFIG_CMPXCHG128) -#include "host/include/generic/host/atomic128-cas.h" +#include "host/include/generic/host/atomic128-cas.h.inc" #else static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h index 88af6d4ea3..03c27022f0 100644 --- a/include/qemu/atomic128.h +++ b/include/qemu/atomic128.h @@ -58,7 +58,7 @@ * Therefore, special case each platform. */ -#include "host/atomic128-cas.h" +#include "host/atomic128-cas.h.inc" #include "host/atomic128-ldst.h" #endif /* QEMU_ATOMIC128_H */ diff --git a/host/include/generic/host/atomic128-cas.h b/host/include/generic/host/atomic128-cas.h.inc similarity index 100% rename from host/include/generic/host/atomic128-cas.h rename to host/include/generic/host/atomic128-cas.h.inc From patchwork Sat Mar 8 22:58:59 2025 Content-Type: text/plain; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 20/23] qemu/atomic: Rename atomic128-ldst.h headers using .h.inc suffix Date: Sat, 8 Mar 2025 14:58:59 -0800 Message-ID: <20250308225902.1208237-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented in the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename 'atomic128-ldst.h' as 'atomic128-ldst.h.inc'. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-ID: <20241212141018.59428-3-philmd@linaro.org> --- include/qemu/atomic128.h | 2 +- .../aarch64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} | 0 .../generic/host/{atomic128-ldst.h => atomic128-ldst.h.inc} | 0 .../loongarch64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} | 0 .../x86_64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} | 2 +- host/include/x86_64/host/load-extract-al16-al8.h.inc | 2 +- 6 files changed, 3 insertions(+), 3 deletions(-) rename host/include/aarch64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} (100%) rename host/include/generic/host/{atomic128-ldst.h => atomic128-ldst.h.inc} (100%) rename host/include/loongarch64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} (100%) rename host/include/x86_64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} (96%) diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h index 03c27022f0..448fb64479 100644 --- a/include/qemu/atomic128.h +++ b/include/qemu/atomic128.h @@ -59,6 +59,6 @@ */ #include "host/atomic128-cas.h.inc" -#include "host/atomic128-ldst.h" +#include "host/atomic128-ldst.h.inc" #endif /* QEMU_ATOMIC128_H */ diff --git a/host/include/aarch64/host/atomic128-ldst.h b/host/include/aarch64/host/atomic128-ldst.h.inc similarity index 100% rename from host/include/aarch64/host/atomic128-ldst.h rename to host/include/aarch64/host/atomic128-ldst.h.inc diff --git a/host/include/generic/host/atomic128-ldst.h b/host/include/generic/host/atomic128-ldst.h.inc similarity index 100% rename from host/include/generic/host/atomic128-ldst.h rename to host/include/generic/host/atomic128-ldst.h.inc diff --git a/host/include/loongarch64/host/atomic128-ldst.h b/host/include/loongarch64/host/atomic128-ldst.h.inc similarity index 100% rename from host/include/loongarch64/host/atomic128-ldst.h rename to host/include/loongarch64/host/atomic128-ldst.h.inc diff --git a/host/include/x86_64/host/atomic128-ldst.h b/host/include/x86_64/host/atomic128-ldst.h.inc similarity index 96% rename from host/include/x86_64/host/atomic128-ldst.h rename to host/include/x86_64/host/atomic128-ldst.h.inc index 8d6f909d3c..4c698e3246 100644 --- a/host/include/x86_64/host/atomic128-ldst.h +++ b/host/include/x86_64/host/atomic128-ldst.h.inc @@ -69,7 +69,7 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) } #else /* Provide QEMU_ERROR stubs. */ -#include "host/include/generic/host/atomic128-ldst.h" +#include "host/include/generic/host/atomic128-ldst.h.inc" #endif #endif /* X86_64_ATOMIC128_LDST_H */ diff --git a/host/include/x86_64/host/load-extract-al16-al8.h.inc b/host/include/x86_64/host/load-extract-al16-al8.h.inc index baa506b7b5..b837c37868 100644 --- a/host/include/x86_64/host/load-extract-al16-al8.h.inc +++ b/host/include/x86_64/host/load-extract-al16-al8.h.inc @@ -9,7 +9,7 @@ #define X86_64_LOAD_EXTRACT_AL16_AL8_H #ifdef CONFIG_INT128_TYPE -#include "host/atomic128-ldst.h" +#include "host/atomic128-ldst.h.inc" /** * load_atom_extract_al16_or_al8: From patchwork Sat Mar 8 22:59:00 2025 Content-Type: text/plain; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 21/23] qemu/atomic128: Include missing 'qemu/atomic.h' header Date: Sat, 8 Mar 2025 14:59:00 -0800 Message-ID: <20250308225902.1208237-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé qatomic_cmpxchg__nocheck() is declared in "qemu/atomic.h". Include it in order to avoid when refactoring unrelated headers: In file included from ../../accel/tcg/tcg-runtime-gvec.c:22: In file included from include/exec/helper-proto-common.h:10: In file included from include/qemu/atomic128.h:61: host/include/generic/host/atomic128-cas.h.inc:23:11: error: call to undeclared function 'qatomic_cmpxchg__nocheck'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 23 | r.i = qatomic_cmpxchg__nocheck(ptr_align, c.i, n.i); | ^ 1 error generated. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20241212141018.59428-4-philmd@linaro.org> --- include/qemu/atomic128.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h index 448fb64479..31e5c48d8f 100644 --- a/include/qemu/atomic128.h +++ b/include/qemu/atomic128.h @@ -13,6 +13,7 @@ #ifndef QEMU_ATOMIC128_H #define QEMU_ATOMIC128_H +#include "qemu/atomic.h" #include "qemu/int128.h" /* From patchwork Sat Mar 8 22:59:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 14007942 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B13CBC282EC for ; Sat, 8 Mar 2025 23:00:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tr39W-0005Gy-JV; Sat, 08 Mar 2025 18:00:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tr38b-0004f4-Uk for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:23 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tr38a-0005OM-7D for qemu-devel@nongnu.org; Sat, 08 Mar 2025 17:59:21 -0500 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-224019ad9edso72454195ad.1 for ; Sat, 08 Mar 2025 14:59:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741474759; x=1742079559; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KDCdWZkLjIT6VVlI83+qjJp41u3agVi8F9xK/yxm2ro=; b=FPqBDS5a5ECM7YyxAT8ENvZJSjiU7UFA4+RCsJo+nX5/zUgBxIcThlW7gQgerQEuCP GG+F98bvfD0eGr6yqPfrMMQuE0QY+CD5NfsBtGxETPSw7+SQ+v87lgk2VpA64IpxgbBV d+LaDGhkHWeyMRMS6eK0lV1iHzU0wdXdezMQqVh2ES/C+9Ghd6gxneGGEPvpFun2YCJB c9EQaVTDwdilARaOs0lbIL8BNwo3orkQ6GmBUytfnaNOkjevjbXpkcNv4UnnpZhBz2q+ BGsi9QZgU4qNImklx6221yuZSIh3XdlHiVQEeuFjA1ZPjK9jPDIVWpmktTE/tdEWD9pZ SLzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741474759; x=1742079559; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KDCdWZkLjIT6VVlI83+qjJp41u3agVi8F9xK/yxm2ro=; b=MyaLcT3Js5f4aPKDLOzGI1/r4moI6o3bY0CP8N2uHE4VULf4+cBrM3IdFKJwqxdoRA BttP5OJys2/X2IWNiiFnsV1rGjgKQZZGlqfuUhUVGtalSTpDxl0Fq4Kp7kxFUX54IFhG keoSQeeuPB62dcEcmgdgT73fSf/Xp7RiPAc6XU1TMV/EJzShGQ48evpjHdPmC7G3o/8S M+1s4yQTmf2kxcbQxHCoh+90cxHHBuaZO5ifARtyjY7pJcALPiE18XD1sTpfJV1gB8SJ gnqKOK3mHJZqiRFswbP1KRp8slblcieGlJH84V5THuuZWy9LWhk6xngZsHBqzJHX7e8v jo7w== X-Gm-Message-State: AOJu0Yy56sDfpv6sltsBHp6JDCsce5vpIg2Ac7FbdpYFcyWlfGBNgC2v K8r80Fg6DcuinIIkRjF++/Xr6gfn+85etfAgNG7a3CgrRl0oLGkdaEaRNjMZZTJZBqbck23cED8 U X-Gm-Gg: ASbGncvbnf2Am1gX571XHGPsTh4wHTt3RZ5XAR2zI20NIpwamVRnbEaYDJER+bJd2GX cUsf9Ii2k9iBM1HdRK2mt8n5kLAG1WCZY/EmOOwK6z7y4fm/58qlO+8ohmr7IsC78exyauh2BtR wOjUmLRyEWinOB29RoP94ocLcJWHJEdObGuiGd4c7TwUeBM8xv2xPMzkcMNEpB4ZfUPog2fbobX 329jyaNOuL4Jrj228rSqDmwi0kfAR+Rx3HT2PeEUCvFONODY61aw8ecM3BooFD4/V4TRBvP6AQU FfrKFKao3cjJE4Z7d/nwNzfADLRptZWZG7f8N8RZDJjL8qreimq7E2XkmJYFvHq1d/ueNK9hmlo T X-Google-Smtp-Source: AGHT+IEd7Vf+G6b+cSwKctez5TubMnm038AOVMZFW7EMiHSSzd03A90BbPPTQeKNHsgmOzTJAwlH4A== X-Received: by 2002:a17:902:d551:b0:224:1ec0:8a1a with SMTP id d9443c01a7336-22428ad54d8mr129329395ad.51.1741474758707; Sat, 08 Mar 2025 14:59:18 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 22/23] accel/tcg: Build tcg-runtime.c once Date: Sat, 8 Mar 2025 14:59:01 -0800 Message-ID: <20250308225902.1208237-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.c | 8 ++------ accel/tcg/meson.build | 2 +- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 9fa539ad3d..fa7ed9739c 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -23,13 +23,9 @@ */ #include "qemu/osdep.h" #include "qemu/host-utils.h" -#include "cpu.h" +#include "exec/cpu-common.h" #include "exec/helper-proto-common.h" -#include "exec/cpu_ldst.h" -#include "exec/exec-all.h" -#include "disas/disas.h" -#include "exec/log.h" -#include "tcg/tcg.h" +#include "accel/tcg/getpc.h" #define HELPER_H "accel/tcg/tcg-runtime.h" #include "exec/helper-info.c.inc" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 81fb25da5c..411fe28dea 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,5 +1,6 @@ common_ss.add(when: 'CONFIG_TCG', if_true: files( 'cpu-exec-common.c', + 'tcg-runtime.c', )) tcg_specific_ss = ss.source_set() tcg_specific_ss.add(files( @@ -7,7 +8,6 @@ tcg_specific_ss.add(files( 'cpu-exec.c', 'tb-maint.c', 'tcg-runtime-gvec.c', - 'tcg-runtime.c', 'translate-all.c', 'translator.c', )) From patchwork Sat Mar 8 22:59:02 2025 Content-Type: text/plain; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22410a908a0sm51831175ad.162.2025.03.08.14.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 14:59:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 23/23] accel/tcg: Build tcg-runtime-gvec.c once Date: Sat, 8 Mar 2025 14:59:02 -0800 Message-ID: <20250308225902.1208237-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime-gvec.c | 1 - accel/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index afca89baa1..ff927c5dd8 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" -#include "cpu.h" #include "exec/helper-proto-common.h" #include "tcg/tcg-gvec-desc.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 411fe28dea..38ff227eb0 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,13 +1,13 @@ common_ss.add(when: 'CONFIG_TCG', if_true: files( 'cpu-exec-common.c', 'tcg-runtime.c', + 'tcg-runtime-gvec.c', )) tcg_specific_ss = ss.source_set() tcg_specific_ss.add(files( 'tcg-all.c', 'cpu-exec.c', 'tb-maint.c', - 'tcg-runtime-gvec.c', 'translate-all.c', 'translator.c', ))