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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:39 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 01/13] clk: en7523: convert driver to regmap API Date: Sun, 9 Mar 2025 14:29:32 +0100 Message-ID: <20250309132959.19045-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert driver to regmap API, in preparation for support of Airoha AN7583 as the SCU will be an MFD and the regmap will be provided in the parent node. Also Airoha EN7581 benefits from this in preparation of USB support that required checking and configuring SCU SSR bits. While at it also cleanup some register mask and use bitfield macro. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 137 ++++++++++++++++++++++----------------- 1 file changed, 76 insertions(+), 61 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 15bbdeb60b8e..314e7450313f 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only +#include #include #include #include @@ -34,6 +35,7 @@ #define REG_RESET_CONTROL_PCIE2 BIT(26) /* EN7581 */ #define REG_NP_SCU_PCIC 0x88 +#define REG_PCIE_CTRL GENMASK(7, 0) #define REG_NP_SCU_SSTR 0x9c #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) @@ -63,14 +65,14 @@ struct en_clk_desc { }; struct en_clk_gate { - void __iomem *base; + struct regmap *map; struct clk_hw hw; }; struct en_rst_data { const u16 *bank_ofs; const u16 *idx_map; - void __iomem *base; + struct regmap *map; struct reset_controller_dev rcdev; }; @@ -388,44 +390,44 @@ static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val) static int en7523_pci_is_enabled(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + u32 val; - return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); + regmap_read(cg->map, REG_PCI_CONTROL, &val); + return !!(val & REG_PCI_CONTROL_REFCLK_EN1); } static int en7523_pci_prepare(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; + struct regmap *map = cg->map; + u32 mask; /* Need to pull device low before reset */ - val = readl(np_base + REG_PCI_CONTROL); - val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); - writel(val, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, + REG_PCI_CONTROL_PERSTOUT1 | + REG_PCI_CONTROL_PERSTOUT); usleep_range(1000, 2000); /* Enable PCIe port 1 */ - val |= REG_PCI_CONTROL_REFCLK_EN1; - writel(val, np_base + REG_PCI_CONTROL); + regmap_set_bits(map, REG_PCI_CONTROL, + REG_PCI_CONTROL_REFCLK_EN1); usleep_range(1000, 2000); /* Reset to default */ - val = readl(np_base + REG_RESET_CONTROL1); mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | REG_RESET_CONTROL_PCIEHB; - writel(val & ~mask, np_base + REG_RESET_CONTROL1); + regmap_clear_bits(map, REG_RESET_CONTROL1, mask); usleep_range(1000, 2000); - writel(val | mask, np_base + REG_RESET_CONTROL1); + regmap_set_bits(map, REG_RESET_CONTROL1, mask); msleep(100); - writel(val & ~mask, np_base + REG_RESET_CONTROL1); + regmap_clear_bits(map, REG_RESET_CONTROL1, mask); usleep_range(5000, 10000); /* Release device */ mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; - val = readl(np_base + REG_PCI_CONTROL); - writel(val & ~mask, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, mask); usleep_range(1000, 2000); - writel(val | mask, np_base + REG_PCI_CONTROL); + regmap_set_bits(map, REG_PCI_CONTROL, mask); msleep(250); return 0; @@ -434,16 +436,13 @@ static int en7523_pci_prepare(struct clk_hw *hw) static void en7523_pci_unprepare(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val; + struct regmap *map = cg->map; - val = readl(np_base + REG_PCI_CONTROL); - val &= ~REG_PCI_CONTROL_REFCLK_EN1; - writel(val, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, REG_PCI_CONTROL_REFCLK_EN1); } static struct clk_hw *en7523_register_pcie_clk(struct device *dev, - void __iomem *np_base) + struct regmap *clk_map) { const struct en_clk_soc_data *soc_data = device_get_match_data(dev); struct clk_init_data init = { @@ -456,7 +455,7 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev, if (!cg) return NULL; - cg->base = np_base; + cg->map = clk_map; cg->hw.init = &init; if (init.ops->unprepare) @@ -474,21 +473,20 @@ static int en7581_pci_is_enabled(struct clk_hw *hw) u32 val, mask; mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; - val = readl(cg->base + REG_PCI_CONTROL); + regmap_read(cg->map, REG_PCI_CONTROL, &val); return (val & mask) == mask; } static int en7581_pci_enable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; + struct regmap *map = cg->map; + u32 mask; mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | REG_PCI_CONTROL_PERSTOUT; - val = readl(np_base + REG_PCI_CONTROL); - writel(val | mask, np_base + REG_PCI_CONTROL); + regmap_set_bits(map, REG_PCI_CONTROL, mask); return 0; } @@ -496,19 +494,18 @@ static int en7581_pci_enable(struct clk_hw *hw) static void en7581_pci_disable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; + struct regmap *map = cg->map; + u32 mask; mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | REG_PCI_CONTROL_PERSTOUT; - val = readl(np_base + REG_PCI_CONTROL); - writel(val & ~mask, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, mask); usleep_range(1000, 2000); } static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, - void __iomem *base, void __iomem *np_base) + struct regmap *map, struct regmap *clk_map) { struct clk_hw *hw; u32 rate; @@ -517,10 +514,12 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { const struct en_clk_desc *desc = &en7523_base_clks[i]; u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; - u32 val = readl(base + desc->base_reg); + u32 val; + + regmap_read(map, desc->base_reg, &val); rate = en7523_get_base_rate(desc, val); - val = readl(base + reg); + regmap_read(map, reg, &val); rate /= en7523_get_div(desc, val); hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); @@ -533,30 +532,47 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat clk_data->hws[desc->id] = hw; } - hw = en7523_register_pcie_clk(dev, np_base); + hw = en7523_register_pcie_clk(dev, clk_map); clk_data->hws[EN7523_CLK_PCIE] = hw; } +static const struct regmap_config en7523_clk_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + static int en7523_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { void __iomem *base, *np_base; + struct regmap *map, *clk_map; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); + map = devm_regmap_init_mmio(&pdev->dev, base, + &en7523_clk_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + np_base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(np_base)) return PTR_ERR(np_base); - en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + clk_map = devm_regmap_init_mmio(&pdev->dev, np_base, + &en7523_clk_regmap_config); + if (IS_ERR(clk_map)) + return PTR_ERR(clk_map); + + en7523_register_clocks(&pdev->dev, clk_data, map, clk_map); return 0; } static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, - struct regmap *map, void __iomem *base) + struct regmap *map, struct regmap *clk_map) { struct clk_hw *hw; u32 rate; @@ -593,7 +609,7 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat clk_data->hws[desc->id] = hw; } - hw = en7523_register_pcie_clk(dev, base); + hw = en7523_register_pcie_clk(dev, clk_map); clk_data->hws[EN7523_CLK_PCIE] = hw; } @@ -601,15 +617,10 @@ static int en7523_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); - void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; - u32 val; + u32 addr = rst_data->bank_ofs[id / RST_NR_PER_BANK]; - val = readl(addr); - if (assert) - val |= BIT(id % RST_NR_PER_BANK); - else - val &= ~BIT(id % RST_NR_PER_BANK); - writel(val, addr); + regmap_update_bits(rst_data->map, addr, BIT(id % RST_NR_PER_BANK), + assert ? BIT(id % RST_NR_PER_BANK) : 0); return 0; } @@ -630,9 +641,11 @@ static int en7523_reset_status(struct reset_controller_dev *rcdev, unsigned long id) { struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); - void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; + u32 addr = rst_data->bank_ofs[id / RST_NR_PER_BANK]; + u32 val; - return !!(readl(addr) & BIT(id % RST_NR_PER_BANK)); + regmap_read(rst_data->map, addr, &val); + return !!(val & BIT(id % RST_NR_PER_BANK)); } static int en7523_reset_xlate(struct reset_controller_dev *rcdev, @@ -652,7 +665,7 @@ static const struct reset_control_ops en7581_reset_ops = { .status = en7523_reset_status, }; -static int en7581_reset_register(struct device *dev, void __iomem *base) +static int en7581_reset_register(struct device *dev, struct regmap *map) { struct en_rst_data *rst_data; @@ -662,7 +675,7 @@ static int en7581_reset_register(struct device *dev, void __iomem *base) rst_data->bank_ofs = en7581_rst_ofs; rst_data->idx_map = en7581_rst_map; - rst_data->base = base; + rst_data->map = map; rst_data->rcdev.nr_resets = ARRAY_SIZE(en7581_rst_map); rst_data->rcdev.of_xlate = en7523_reset_xlate; @@ -678,9 +691,8 @@ static int en7581_reset_register(struct device *dev, void __iomem *base) static int en7581_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { - struct regmap *map; + struct regmap *map, *clk_map; void __iomem *base; - u32 val; map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); if (IS_ERR(map)) @@ -690,15 +702,18 @@ static int en7581_clk_hw_init(struct platform_device *pdev, if (IS_ERR(base)) return PTR_ERR(base); - en7581_register_clocks(&pdev->dev, clk_data, map, base); + clk_map = devm_regmap_init_mmio(&pdev->dev, base, &en7523_clk_regmap_config); + if (IS_ERR(clk_map)) + return PTR_ERR(clk_map); + + en7581_register_clocks(&pdev->dev, clk_data, map, clk_map); - val = readl(base + REG_NP_SCU_SSTR); - val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:40 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 02/13] clk: en7523: generalize register clocks function Date: Sun, 9 Mar 2025 14:29:33 +0100 Message-ID: <20250309132959.19045-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Generalize register clocks function for Airoha EN7523 and EN7581 clocks driver. The same logic is applied for both clock hence code can be reduced and simplified by putting the base_clocks struct in the soc_data and passing that to a generic register clocks function. There is always the pattern where the last clock is always the PCIe one. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 130 ++++++++++++++++----------------------- 1 file changed, 53 insertions(+), 77 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 314e7450313f..2a74bc8fed24 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -78,8 +78,10 @@ struct en_rst_data { struct en_clk_soc_data { u32 num_clocks; + const struct en_clk_desc *base_clks; const struct clk_ops pcie_ops; int (*hw_init)(struct platform_device *pdev, + const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data); }; @@ -467,6 +469,50 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev, return &cg->hw; } +static void en75xx_register_clocks(struct device *dev, + const struct en_clk_soc_data *soc_data, + struct clk_hw_onecell_data *clk_data, + struct regmap *map, struct regmap *clk_map) +{ + struct clk_hw *hw; + u32 rate; + int i; + + for (i = 0; i < soc_data->num_clocks - 1; i++) { + const struct en_clk_desc *desc = &soc_data->base_clks[i]; + u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; + int err; + + err = regmap_read(map, desc->base_reg, &val); + if (err) { + pr_err("Failed reading fixed clk rate %s: %d\n", + desc->name, err); + continue; + } + rate = en7523_get_base_rate(desc, val); + + err = regmap_read(map, reg, &val); + if (err) { + pr_err("Failed reading fixed clk div %s: %d\n", + desc->name, err); + continue; + } + rate /= en7523_get_div(desc, val); + + hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + + clk_data->hws[desc->id] = hw; + } + + hw = en7523_register_pcie_clk(dev, clk_map); + clk_data->hws[soc_data->num_clocks] = hw; +} + static int en7581_pci_is_enabled(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); @@ -504,38 +550,6 @@ static void en7581_pci_disable(struct clk_hw *hw) usleep_range(1000, 2000); } -static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, - struct regmap *map, struct regmap *clk_map) -{ - struct clk_hw *hw; - u32 rate; - int i; - - for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { - const struct en_clk_desc *desc = &en7523_base_clks[i]; - u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; - u32 val; - - regmap_read(map, desc->base_reg, &val); - - rate = en7523_get_base_rate(desc, val); - regmap_read(map, reg, &val); - rate /= en7523_get_div(desc, val); - - hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %ld\n", - desc->name, PTR_ERR(hw)); - continue; - } - - clk_data->hws[desc->id] = hw; - } - - hw = en7523_register_pcie_clk(dev, clk_map); - clk_data->hws[EN7523_CLK_PCIE] = hw; -} - static const struct regmap_config en7523_clk_regmap_config = { .reg_bits = 32, .val_bits = 32, @@ -543,6 +557,7 @@ static const struct regmap_config en7523_clk_regmap_config = { }; static int en7523_clk_hw_init(struct platform_device *pdev, + const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data) { void __iomem *base, *np_base; @@ -566,53 +581,11 @@ static int en7523_clk_hw_init(struct platform_device *pdev, if (IS_ERR(clk_map)) return PTR_ERR(clk_map); - en7523_register_clocks(&pdev->dev, clk_data, map, clk_map); + en75xx_register_clocks(&pdev->dev, soc_data, clk_data, map, clk_map); return 0; } -static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, - struct regmap *map, struct regmap *clk_map) -{ - struct clk_hw *hw; - u32 rate; - int i; - - for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) { - const struct en_clk_desc *desc = &en7581_base_clks[i]; - u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; - int err; - - err = regmap_read(map, desc->base_reg, &val); - if (err) { - pr_err("Failed reading fixed clk rate %s: %d\n", - desc->name, err); - continue; - } - rate = en7523_get_base_rate(desc, val); - - err = regmap_read(map, reg, &val); - if (err) { - pr_err("Failed reading fixed clk div %s: %d\n", - desc->name, err); - continue; - } - rate /= en7523_get_div(desc, val); - - hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %ld\n", - desc->name, PTR_ERR(hw)); - continue; - } - - clk_data->hws[desc->id] = hw; - } - - hw = en7523_register_pcie_clk(dev, clk_map); - clk_data->hws[EN7523_CLK_PCIE] = hw; -} - static int en7523_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -689,6 +662,7 @@ static int en7581_reset_register(struct device *dev, struct regmap *map) } static int en7581_clk_hw_init(struct platform_device *pdev, + const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data) { struct regmap *map, *clk_map; @@ -706,7 +680,7 @@ static int en7581_clk_hw_init(struct platform_device *pdev, if (IS_ERR(clk_map)) return PTR_ERR(clk_map); - en7581_register_clocks(&pdev->dev, clk_data, map, clk_map); + en75xx_register_clocks(&pdev->dev, soc_data, clk_data, map, clk_map); regmap_clear_bits(clk_map, REG_NP_SCU_SSTR, REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); @@ -732,7 +706,7 @@ static int en7523_clk_probe(struct platform_device *pdev) return -ENOMEM; clk_data->num = soc_data->num_clocks; - r = soc_data->hw_init(pdev, clk_data); + r = soc_data->hw_init(pdev, soc_data, clk_data); if (r) return r; @@ -740,6 +714,7 @@ static int en7523_clk_probe(struct platform_device *pdev) } static const struct en_clk_soc_data en7523_data = { + .base_clks = en7523_base_clks, .num_clocks = ARRAY_SIZE(en7523_base_clks) + 1, .pcie_ops = { .is_enabled = en7523_pci_is_enabled, @@ -750,6 +725,7 @@ static const struct en_clk_soc_data en7523_data = { }; static const struct en_clk_soc_data en7581_data = { + .base_clks = en7581_base_clks, /* We increment num_clocks by 1 to account for additional PCIe clock */ .num_clocks = ARRAY_SIZE(en7581_base_clks) + 1, .pcie_ops = { From patchwork Sun Mar 9 13:29:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 14008425 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD9391DDA0E; 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:42 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 03/13] dt-bindings: soc: airoha: add SCU SSR Serdes port binding Date: Sun, 9 Mar 2025 14:29:34 +0100 Message-ID: <20250309132959.19045-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add Airoha AN7581 SCU SSR Serdes port binding to define what mode is supported by each Serdes port. These special binding are needed to identify and provide the port mode from any user driver. These modes are mutually exclusive and driver needs to correctly validate the current mode for the Serdes port in use. Signed-off-by: Christian Marangi --- MAINTAINERS | 6 ++++++ include/dt-bindings/soc/airoha,scu-ssr.h | 24 ++++++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 include/dt-bindings/soc/airoha,scu-ssr.h diff --git a/MAINTAINERS b/MAINTAINERS index 3eee238c2ea2..d3125268d63f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -736,6 +736,12 @@ F: Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml F: drivers/phy/phy-airoha-pcie-regs.h F: drivers/phy/phy-airoha-pcie.c +AIROHA SCU SSR DRIVER +M: Christian Marangi +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: include/dt-bindings/soc/airoha,scu-ssr.h + AIROHA SPI SNFI DRIVER M: Lorenzo Bianconi M: Ray Liu diff --git a/include/dt-bindings/soc/airoha,scu-ssr.h b/include/dt-bindings/soc/airoha,scu-ssr.h new file mode 100644 index 000000000000..b14457c10d77 --- /dev/null +++ b/include/dt-bindings/soc/airoha,scu-ssr.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_AIROHA_SCU_SSR_H +#define __DT_BINDINGS_AIROHA_SCU_SSR_H + +/* WiFi1 port can be PCIe0 2 line, PCIe0 1 line or Ethernet (USXGMII/HSGMII) */ +#define AIROHA_SCU_SSR_WIFI1_PCIE0_2LINE 0 +#define AIROHA_SCU_SSR_WIFI1_PCIE0 1 +#define AIROHA_SCU_SSR_WIFI1_ETHERNET 2 + +/* WiFi2 port can be PCIe0 2 line, PCIe1 1 line or Ethernet (USXGMII/HSGMII) */ +#define AIROHA_SCU_SSR_WIFI2_PCIE0_2LINE 0 +#define AIROHA_SCU_SSR_WIFI2_PCIE1 1 +#define AIROHA_SCU_SSR_WIFI2_ETHERNET 2 + +/* USB1 port can be USB 3.0 port or Ethernet (HSGMII) */ +#define AIROHA_SCU_SSR_USB1_USB 0 +#define AIROHA_SCU_SSR_USB1_ETHERNET 1 + +/* USB2 port can be USB 3.0 port or PCIe2 1 line */ +#define AIROHA_SCU_SSR_USB2_USB 0 +#define AIROHA_SCU_SSR_USB2_PCIE2 1 + +#endif /* __DT_BINDINGS_AIROHA_SCU_SSR_H */ From patchwork Sun Mar 9 13:29:35 2025 Content-Type: text/plain; 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:44 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 04/13] dt-bindings: soc: airoha: add Documentation for Airoha AN7581 SCU SSR Date: Sun, 9 Mar 2025 14:29:35 +0100 Message-ID: <20250309132959.19045-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Airoha AN7581 SoC have in the SCU register space particular address that control how some peripheral are configured. These are toggeled in the System Status Register and are used to toggle Serdes port for USB 3.0 mode or HSGMII, USB 3.0 mode or PCIe2 or setup port for PCIe mode or Ethrnet mode (HSGMII/USXGMII). Modes are mutually exclusive and selecting one mode cause the other feature to not work (example a mode in USB 3.0 cause PCIe port 2 to not work) This depends also on what is physically connected to the Hardware and needs to correctly reflect the System Status Register bits. Special care is needed for PCIe port 0 in 2 line mode that requires both WiFi1 and WiFi2 Serdes port set to PCIe0 2 Line mode. Signed-off-by: Christian Marangi --- .../soc/airoha/airoha,an7581-scu-ssr.yaml | 106 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/airoha/airoha,an7581-scu-ssr.yaml diff --git a/Documentation/devicetree/bindings/soc/airoha/airoha,an7581-scu-ssr.yaml b/Documentation/devicetree/bindings/soc/airoha/airoha,an7581-scu-ssr.yaml new file mode 100644 index 000000000000..4bbf6e3b79a4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/airoha/airoha,an7581-scu-ssr.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/airoha/airoha,an7581-scu-ssr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7581 SCU System Status Register + +maintainers: + - Christian Marangi + +description: > + The Airoha AN7581 SoC have in the SCU register space particular + address that control how some peripheral are configured. + + These are toggeled in the System Status Register and are used to + toggle Serdes port for USB 3.0 mode or HSGMII, USB 3.0 mode or PCIe2 + or setup port for PCIe mode or Ethrnet mode (HSGMII/USXGMII). + + Modes are mutually exclusive and selecting one mode cause the + other feature to not work (example a mode in USB 3.0 cause PCIe + port 2 to not work) This depends also on what is physically + connected to the Hardware and needs to correctly reflect the + System Status Register bits. + + Special care is needed for PCIe port 0 in 2 line mode that + requires both WiFi1 and WiFi2 Serdes port set to PCIe0 2 Line + mode. + +properties: + compatible: + const: airoha,an7581-scu-ssr + + airoha,serdes-wifi1: + description: | + Configure the Wifi1 Serdes port for: + - 0: PCIe0 2 Line + - 1: PCIe0 1 Line + - 2: Ethernet modes (HSGMII/USXGMII) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 1 + + airoha,serdes-wifi2: + description: | + Configure the Wifi2 Serdes port for: + - 0: PCIe0 2 Line + - 1: PCIe1 1 Line + - 2: Ethernet modes (HSGMII/USXGMII) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 1 + + airoha,serdes-usb1: + description: | + Configure the USB1 Serdes port for: + - 0: USB 3.0 + - 1: Ethernet modes (HSGMII) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + default: 0 + + airoha,serdes-usb2: + description: | + Configure the USB2 Serdes port for: + - 0: USB 3.0 + - 1: PCIe2 1 Line + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + default: 0 + +required: + - compatible + +allOf: + - if: + properties: + airoha,serdes-wifi1: + const: 0 + then: + properties: + airoha,serdes-wifi2: + const: 0 + + - if: + properties: + airoha,serdes-wifi2: + const: 0 + then: + properties: + airoha,serdes-wifi1: + const: 0 + +additionalProperties: false + +examples: + - | + #include + + system-controller { + compatible = "airoha,an7581-scu-ssr"; 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:45 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 05/13] dt-bindings: mfd: add Documentation for Airoha EN7581 SCU Date: Sun, 9 Mar 2025 14:29:36 +0100 Message-ID: <20250309132959.19045-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add Documentation for Airoha EN7581 SCU. Airoha EN7581 SoC expose registers to control miscellaneous pheriperals via the SCU (System Controller Unit). Example of these pheriperals are reset-controller, clock-controller, PCIe line speed controller and bits to configure different Serdes ports for USB or Ethernet usage. Signed-off-by: Christian Marangi --- .../mfd/airoha,en7581-scu-sysctl.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/airoha,en7581-scu-sysctl.yaml diff --git a/Documentation/devicetree/bindings/mfd/airoha,en7581-scu-sysctl.yaml b/Documentation/devicetree/bindings/mfd/airoha,en7581-scu-sysctl.yaml new file mode 100644 index 000000000000..d7dc66f912c1 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/airoha,en7581-scu-sysctl.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/airoha,en7581-scu-sysctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 SCU (System Controller Unit) + +maintainers: + - Christian Marangi + +description: + Airoha EN7581 SoC expose registers to control miscellaneous + pheriperals via the SCU (System Controller Unit). + + Example of these pheriperals are reset-controller, clock-controller, + PCIe line speed controller and bits to configure different Serdes ports + for USB or Ethernet usage. + +properties: + compatible: + items: + - const: airoha,en7581-scu-sysctl + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clock-controller: + type: object + $ref: /schemas/clock/airoha,en7523-scu.yaml + description: + Child node definition for EN7581 Clock controller + + system-controller: + type: object + $ref: /schemas/soc/airoha/airoha,an7581-scu-ssr.yaml + description: + Child node definition for EN7581 System Status Register + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + system-controller@1fb00000 { + compatible = "airoha,en7581-scu-sysctl", "syscon", "simple-mfd"; + reg = <0x1fb00000 0x970>; + + clock-controller { + compatible = "airoha,en7581-scu"; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + system-controller { + compatible = "airoha,an7581-scu-ssr"; + + airoha,serdes-usb2 = ; + }; + }; From patchwork Sun Mar 9 13:29:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 14008428 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CF301E521A; Sun, 9 Mar 2025 13:30:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741527051; cv=none; b=X2svrtxle75JiNkJsFRU6X84vEGaO1x1bbbzWJIve8SV+t8CS+C5BAuk53yKipCYrS49V/rx23ZY32oV9d44JlVEXqCIh8RE0BHhCR+vCHFaWD2puF6NYQBBp0bm2U+lEB0hjtA7lmqK31P17Y+taKReUyKIgeNPxoKwW73AuNU= ARC-Message-Signature: i=1; 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:47 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 06/13] dt-bindings: clock: airoha: make reg optional for Airoha EN7581 Date: Sun, 9 Mar 2025 14:29:37 +0100 Message-ID: <20250309132959.19045-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Airoha EN7581 clock-controller registers are placed in the SCU (System Controller Unit). Now that additional pheriperals are supported for the SCU, a dedicated SCU node is created and the clock-controller is moved as a child of such node hence the register property is taken from the parent node. To support this, make the reg property optional and provide an additional example for this case. Driver supports both old and new implementation by checking the presence of the reg property and parsing the register accordingly. Signed-off-by: Christian Marangi --- .../bindings/clock/airoha,en7523-scu.yaml | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index fe2c5c1baf43..84e6c3d43868 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -51,7 +51,6 @@ properties: required: - compatible - - reg - '#clock-cells' allOf: @@ -66,6 +65,9 @@ allOf: '#reset-cells': false + required: + - reg + - if: properties: compatible: @@ -99,3 +101,12 @@ examples: #reset-cells = <1>; }; }; + + # Example with clock-controller in SCU MFD + - | + clock-controller { + compatible = "airoha,en7581-scu"; + + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Sun Mar 9 13:29:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 14008429 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D11CC1EFF9C; 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:49 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 07/13] clk: en7523: support getting regmap from parent node for EN7581 Date: Sun, 9 Mar 2025 14:29:38 +0100 Message-ID: <20250309132959.19045-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for getting clock regmap from parent node for Airoha EN7581. This is needed to support new implementation with SCU (System Controller Unit) as an MFD and clock-controller node as a child node of it. In such implementation the register regmap is provided as a syscon from the parent node. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 2a74bc8fed24..29cb7ccea29a 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -665,6 +665,7 @@ static int en7581_clk_hw_init(struct platform_device *pdev, const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data) { + struct device *dev = &pdev->dev; struct regmap *map, *clk_map; void __iomem *base; @@ -672,22 +673,28 @@ static int en7581_clk_hw_init(struct platform_device *pdev, if (IS_ERR(map)) return PTR_ERR(map); - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_map = devm_regmap_init_mmio(&pdev->dev, base, &en7523_clk_regmap_config); - if (IS_ERR(clk_map)) - return PTR_ERR(clk_map); + if (of_property_present(dev->of_node, "reg")) { + base = devm_platform_ioremap_resource(pdev, 0); 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:51 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 08/13] soc: airoha: add support for configuring SCU SSR Serdes port Date: Sun, 9 Mar 2025 14:29:39 +0100 Message-ID: <20250309132959.19045-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for configuring SCU SSR Serdes port. Airoha AN7581 SoC can configure the different Serdes port by toggling bits in the SCU register space. Port Serdes mode are mutually exclusive, force example the USB2 Serdes port can either used for USB 3.0 or PCIe 2 port. Enabling USB 3.0 makes the PCIe 2 to not work. The current supported Serdes port are: - WiFi 1 and defaults to PCIe0 1 line mode - Wifi 2 and defaults to PCIe1 1 line mode - USB 1 and defaults to USB 3.0 mode - USB 2 and defaults to USB 3.0 mode WiFi 1, WiFi 2 and USB 1 also support a particular Ethernet mode that can toggle between USXGMII or HSGMII mode (USB 1 only to HSGMII) Such mode doesn't configure bits as specific Ethernet PCS driver will take care of configuring the Serdes mode based on what is required. This driver is to correctly setup these bits and provide an API to read the current status of the Serdes port. Single driver can't independently set the Serdes port mode as that would cause a conflict if someone declare, for example, in DT (and enable) PCIe 2 port and USB2 3.0 port. Drivers will use the airoha_scu_ssr_get_serdes_mode function and will validate the Serdes port is the expected one and fail if it's not. Each driver will have to define in DT the phandle airoha,scu-ssr pointing to the SCU SSR node. Signed-off-by: Christian Marangi --- MAINTAINERS | 1 + drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/airoha/Kconfig | 18 ++ drivers/soc/airoha/Makefile | 3 + drivers/soc/airoha/airoha-scu-ssr.c | 195 ++++++++++++++++++++++ include/linux/soc/airoha/airoha-scu-ssr.h | 17 ++ include/linux/soc/soc/airoha-scu-ssr.h | 17 ++ 8 files changed, 253 insertions(+) create mode 100644 drivers/soc/airoha/Kconfig create mode 100644 drivers/soc/airoha/Makefile create mode 100644 drivers/soc/airoha/airoha-scu-ssr.c create mode 100644 include/linux/soc/airoha/airoha-scu-ssr.h create mode 100644 include/linux/soc/soc/airoha-scu-ssr.h diff --git a/MAINTAINERS b/MAINTAINERS index 9944845ae9f5..fe34c80b8d52 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -741,6 +741,7 @@ M: Christian Marangi L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/soc/airoha/airoha,an7581-scu-ssr.yaml +F: drivers/soc/airoha/airoha-scu-ssr.c F: include/dt-bindings/soc/airoha,scu-ssr.h AIROHA SPI SNFI DRIVER diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 6a8daeb8c4b9..21bacefd2e06 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only menu "SOC (System On Chip) specific Drivers" +source "drivers/soc/airoha/Kconfig" source "drivers/soc/amlogic/Kconfig" source "drivers/soc/apple/Kconfig" source "drivers/soc/aspeed/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 2037a8695cb2..4338730af0aa 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -3,6 +3,7 @@ # Makefile for the Linux Kernel SOC specific device drivers. # +obj-$(CONFIG_ARCH_AIROHA) += airoha/ obj-y += apple/ obj-y += aspeed/ obj-$(CONFIG_ARCH_AT91) += atmel/ diff --git a/drivers/soc/airoha/Kconfig b/drivers/soc/airoha/Kconfig new file mode 100644 index 000000000000..56c677f8238d --- /dev/null +++ b/drivers/soc/airoha/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config AIROHA_SCU_SSR + tristate "Airoha SCU SSR Driver" + depends on ARCH_AIROHA || COMPILE_TEST + depends on OF + help + Say 'Y' here to add support for Airoha SCU SSR driver. + + Airoha SoC pheriperal (like USB/PCIe/Ethernet port) are + selected by toggling specific bit. Serdes Port line + are mutually exclusive such as selecting PCIe port 2 + disable support for USB port 2 3.0 mode. + + This driver is used to configure such bit and expose + an API to read the current status from a user of such + Serdes lines. + diff --git a/drivers/soc/airoha/Makefile b/drivers/soc/airoha/Makefile new file mode 100644 index 000000000000..530825251ae9 --- /dev/null +++ b/drivers/soc/airoha/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_AIROHA_SCU_SSR) += airoha-scu-ssr.o diff --git a/drivers/soc/airoha/airoha-scu-ssr.c b/drivers/soc/airoha/airoha-scu-ssr.c new file mode 100644 index 000000000000..fe65b5b91146 --- /dev/null +++ b/drivers/soc/airoha/airoha-scu-ssr.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Author: Christian Marangi + */ + +#include +#include +#include +#include +#include +#include +#include + +#define AIROHA_SCU_PCIC 0x88 +#define AIROHA_SCU_PCIE_2LANE_MODE BIT(14) + +#define AIROHA_SCU_SSR3 0x94 +#define AIROHA_SCU_SSUSB_HSGMII_SEL BIT(29) + +#define AIROHA_SCU_SSTR 0x9c +#define AIROHA_SCU_PCIE_XSI0_SEL GENMASK(14, 13) +#define AIROHA_SCU_PCIE_XSI0_SEL_PCIE FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x0) +#define AIROHA_SCU_PCIE_XSI1_SEL GENMASK(12, 11) +#define AIROHA_SCU_PCIE_XSI1_SEL_PCIE FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x0) +#define AIROHA_SCU_USB_PCIE_SEL BIT(3) + +struct airoha_scu_ssr_priv { + struct device *dev; + struct regmap *regmap; + + u32 serdes_port[AIROHA_SCU_MAX_SERDES_PORT]; +}; + +int airoha_scu_ssr_get_serdes_mode(struct device *dev, + enum airoha_scu_serdes_port port) +{ + struct airoha_scu_ssr_priv *priv; + struct platform_device *pdev; + struct device_node *np; + + np = of_parse_phandle(dev->of_node, "airoha,scu-ssr", 0); + if (!np) + return -ENODEV; + + if (!of_device_is_available(np)) { + of_node_put(np); + return -ENODEV; + } + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev || !platform_get_drvdata(pdev)) { + if (pdev) + put_device(&pdev->dev); + return -EPROBE_DEFER; + } + + priv = platform_get_drvdata(pdev); + + return priv->serdes_port[port]; +} +EXPORT_SYMBOL_GPL(airoha_scu_ssr_get_serdes_mode); + +static int airoha_scu_ssr_apply_modes(struct airoha_scu_ssr_priv *priv) +{ + int ret; + + /* + * This is a very bad scenario and needs to be correctly warned + * as it cause PCIe malfunction + */ + if ((priv->serdes_port[AIROHA_SCU_SERDES_WIFI1] == AIROHA_SCU_SSR_WIFI1_PCIE0_2LINE && + priv->serdes_port[AIROHA_SCU_SERDES_WIFI2] != AIROHA_SCU_SSR_WIFI2_PCIE0_2LINE) || + (priv->serdes_port[AIROHA_SCU_SERDES_WIFI1] != AIROHA_SCU_SSR_WIFI1_PCIE0_2LINE && + priv->serdes_port[AIROHA_SCU_SERDES_WIFI2] == AIROHA_SCU_SSR_WIFI2_PCIE0_2LINE)) { + WARN(true, "Wrong Serdes configuration for PCIe0 2 Line mode. Please check DT.\n"); + return -EINVAL; + } + + /* PCS driver takes case of setting the SCU bit for HSGMII or USXGMII */ + if (priv->serdes_port[AIROHA_SCU_SERDES_WIFI1] == AIROHA_SCU_SSR_WIFI1_PCIE0_2LINE || + priv->serdes_port[AIROHA_SCU_SERDES_WIFI1] == AIROHA_SCU_SSR_WIFI1_PCIE0) { + ret = regmap_update_bits(priv->regmap, AIROHA_SCU_SSTR, + AIROHA_SCU_PCIE_XSI0_SEL, + AIROHA_SCU_PCIE_XSI0_SEL_PCIE); + if (ret) + return ret; + } + + /* PCS driver takes case of setting the SCU bit for HSGMII or USXGMII */ + if (priv->serdes_port[AIROHA_SCU_SERDES_WIFI2] == AIROHA_SCU_SSR_WIFI2_PCIE0_2LINE || + priv->serdes_port[AIROHA_SCU_SERDES_WIFI2] == AIROHA_SCU_SSR_WIFI2_PCIE1) { + ret = regmap_update_bits(priv->regmap, AIROHA_SCU_SSTR, + AIROHA_SCU_PCIE_XSI1_SEL, + AIROHA_SCU_PCIE_XSI1_SEL_PCIE); + if (ret) + return ret; + } + + /* Toggle PCIe0 2 Line mode if enabled or not */ + if (priv->serdes_port[AIROHA_SCU_SERDES_WIFI1] == AIROHA_SCU_SSR_WIFI1_PCIE0_2LINE) + ret = regmap_set_bits(priv->regmap, AIROHA_SCU_PCIC, + AIROHA_SCU_PCIE_2LANE_MODE); + else + ret = regmap_clear_bits(priv->regmap, AIROHA_SCU_PCIC, + AIROHA_SCU_PCIE_2LANE_MODE); + if (ret) + return ret; + + if (priv->serdes_port[AIROHA_SCU_SERDES_USB1] == AIROHA_SCU_SSR_USB1_ETHERNET) + ret = regmap_clear_bits(priv->regmap, AIROHA_SCU_SSR3, + AIROHA_SCU_SSUSB_HSGMII_SEL); + else + ret = regmap_set_bits(priv->regmap, AIROHA_SCU_SSR3, + AIROHA_SCU_SSUSB_HSGMII_SEL); + if (ret) + return ret; + + if (priv->serdes_port[AIROHA_SCU_SERDES_USB2] == AIROHA_SCU_SSR_USB2_PCIE2) + ret = regmap_clear_bits(priv->regmap, AIROHA_SCU_SSTR, + AIROHA_SCU_USB_PCIE_SEL); + else + ret = regmap_set_bits(priv->regmap, AIROHA_SCU_SSTR, + AIROHA_SCU_USB_PCIE_SEL); + if (ret) + return ret; + + return 0; +} + +static int airoha_scu_ssr_probe(struct platform_device *pdev) +{ + struct airoha_scu_ssr_priv *priv; + struct device *dev = &pdev->dev; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + + /* Get regmap from MFD */ + priv->regmap = dev_get_regmap(dev->parent, NULL); + if (!priv->regmap) + return -EINVAL; + + /* If not set, default to PCIE0 1 line */ + if (of_property_read_u32(dev->of_node, "airoha,serdes-wifi1", + &priv->serdes_port[AIROHA_SCU_SERDES_WIFI1])) + priv->serdes_port[AIROHA_SCU_SERDES_WIFI1] = AIROHA_SCU_SSR_WIFI1_PCIE0; + + /* If not set, default to PCIE1 1 line */ + if (of_property_read_u32(dev->of_node, "airoha,serdes-wifi2", + &priv->serdes_port[AIROHA_SCU_SERDES_WIFI2])) + priv->serdes_port[AIROHA_SCU_SERDES_WIFI1] = AIROHA_SCU_SSR_WIFI2_PCIE1; + + /* If not set, default to USB1 USB 3.0 */ + if (of_property_read_u32(dev->of_node, "airoha,serdes-usb1", + &priv->serdes_port[AIROHA_SCU_SERDES_USB1])) + priv->serdes_port[AIROHA_SCU_SERDES_WIFI1] = AIROHA_SCU_SSR_USB1_USB; + + /* If not set, default to USB2 USB 3.0 */ + if (of_property_read_u32(dev->of_node, "airoha,serdes-usb2", + &priv->serdes_port[AIROHA_SCU_SERDES_USB2])) + priv->serdes_port[AIROHA_SCU_SERDES_WIFI1] = AIROHA_SCU_SSR_USB2_USB; + + ret = airoha_scu_ssr_apply_modes(priv); + if (ret) + return ret; + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static const struct of_device_id airoha_phy_id_table[] = { + { .compatible = "airoha,an7581-scu-ssr" }, + { }, +}; +MODULE_DEVICE_TABLE(of, airoha_phy_id_table); + +static struct platform_driver airoha_scu_ssr_driver = { + .probe = airoha_scu_ssr_probe, + .driver = { + .name = "airoha-scu-ssr", + .of_match_table = airoha_phy_id_table, + }, +}; + +module_platform_driver(airoha_scu_ssr_driver); + +MODULE_AUTHOR("Christian Marangi "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Airoha SCU SSR/STR driver"); diff --git a/include/linux/soc/airoha/airoha-scu-ssr.h b/include/linux/soc/airoha/airoha-scu-ssr.h new file mode 100644 index 000000000000..d5ff50dc224f --- /dev/null +++ b/include/linux/soc/airoha/airoha-scu-ssr.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __AIROHA_SCU_SSR__ +#define __AIROHA_SCU_SSR__ + +enum airoha_scu_serdes_port { + AIROHA_SCU_SERDES_WIFI1 = 0, + AIROHA_SCU_SERDES_WIFI2, + AIROHA_SCU_SERDES_USB1, + AIROHA_SCU_SERDES_USB2, + + AIROHA_SCU_MAX_SERDES_PORT, +}; + +int airoha_scu_ssr_get_serdes_mode(struct device *dev, + enum airoha_scu_serdes_port port); + +#endif diff --git a/include/linux/soc/soc/airoha-scu-ssr.h b/include/linux/soc/soc/airoha-scu-ssr.h new file mode 100644 index 000000000000..d5ff50dc224f --- /dev/null +++ b/include/linux/soc/soc/airoha-scu-ssr.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __AIROHA_SCU_SSR__ +#define __AIROHA_SCU_SSR__ + +enum airoha_scu_serdes_port { + AIROHA_SCU_SERDES_WIFI1 = 0, + AIROHA_SCU_SERDES_WIFI2, + AIROHA_SCU_SERDES_USB1, + AIROHA_SCU_SERDES_USB2, + + AIROHA_SCU_MAX_SERDES_PORT, +}; + +int airoha_scu_ssr_get_serdes_mode(struct device *dev, + enum airoha_scu_serdes_port port); + +#endif From patchwork Sun Mar 9 13:29:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 14008431 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 408441F099F; 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:52 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 09/13] dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY Date: Sun, 9 Mar 2025 14:29:40 +0100 Message-ID: <20250309132959.19045-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add documentation for Airoha AN7581 USB PHY that describe the USB PHY for the USB controller. Airoha AN7581 SoC support a maximum of 2 USB port. The USB 2.0 mode is always supported. The USB 3.0 mode is optional and depends on the Serdes mode currently configured on the system for the USB port. If USB 3.0 node is defined, then airoha,scu-ssr property is required for Serdes mode validation. Signed-off-by: Christian Marangi --- .../bindings/phy/airoha,an7581-usb-phy.yaml | 106 ++++++++++++++++++ MAINTAINERS | 6 + 2 files changed, 112 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml new file mode 100644 index 000000000000..39127cfb63a7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/airoha,an7581-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7581 SoC USB PHY + +maintainers: + - Christian Marangi + +description: > + The Airoha AN7581 SoC USB PHY describes the USB PHY for the USB controller. + + Airoha AN7581 SoC support a maximum of 2 USB port. The USB 2.0 mode is + always supported. The USB 3.0 mode is optional and depends on the Serdes + mode currently configured on the system for the USB port. If USB 3.0 node + is defined, then airoha,scu-ssr property is required for Serdes mode + validation. + +properties: + compatible: + const: airoha,an7581-usb-phy + + reg: + maxItems: 1 + + airoha,port-id: + description: Describe the physical port this USB PHY refer to. A dedicated + osciallator is used for each port for the USB 2.0 Slew Rate calibration. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + airoha,scu-ssr: + description: Phandle to the SCU SSR node for USB 3.0 Serdes mode validation. + $ref: /schemas/types.yaml#/definitions/phandle + + usb2-phy: + type: object + + properties: + '#phy-cells': + const: 1 + + required: + - '#phy-cells' + + additionalProperties: false + + usb3-phy: + type: object + + properties: + '#phy-cells': + const: 1 + + required: + - '#phy-cells' + + additionalProperties: false + +required: + - compatible + - reg + - airoha,port-id + - usb2-phy + +if: + required: + - usb3-phy +then: + required: + - airoha,scu-ssr + +additionalProperties: false + +examples: + - | + phy@1fac0000 { + compatible = "airoha,an7581-usb-phy"; + reg = <0x1fac0000 0x10000>; + + airoha,port-id = <0>; + airoha,scu-ssr = <&scu_ssr>; + + usb0_u2: usb2-phy { + #phy-cells = <1>; + }; + + usb0_u3: usb3-phy { + #phy-cells = <1>; + }; + }; + + - | + phy@1fae0000 { + compatible = "airoha,an7581-usb-phy"; + reg = <0x1fae0000 0x10000>; + + airoha,port-id = <1>; + + usb1_u2: usb2-phy { + #phy-cells = <1>; + }; + }; + diff --git a/MAINTAINERS b/MAINTAINERS index fe34c80b8d52..c2dd385e9165 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -753,6 +753,12 @@ S: Maintained F: Documentation/devicetree/bindings/spi/airoha,en7581-snand.yaml F: drivers/spi/spi-airoha-snfi.c +AIROHA USB PHY DRIVER +M: Christian Marangi +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yam + AIRSPY MEDIA DRIVER L: linux-media@vger.kernel.org S: Orphan From patchwork Sun Mar 9 13:29:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 14008432 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 870D91F4C81; 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:54 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 10/13] phy: airoha: Add support for Airoha AN7581 USB PHY Date: Sun, 9 Mar 2025 14:29:41 +0100 Message-ID: <20250309132959.19045-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for Airoha AN7581 USB PHY driver. AN7581 supports up to 2 USB port with USB 2.0 mode always supported and USB 3.0 mode available only if the Serdes port is correctly configured for USB 3.0. On xLate probe, the Serdes mode is validated and the driver return error if the Serdes mode doesn't reflect the expected mode. This is required as Serdes mode are controlled by the SCU SSR bits and can be either USB 3.0 mode or HSGMII or PCIe 2. In such case USB 3.0 won't work. If the USB 3.0 mode is not supported, the modes needs to be also disabled in the xHCI node or the driver will report unsable clock and fail probe. Signed-off-by: Christian Marangi --- MAINTAINERS | 1 + drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 3 +- drivers/phy/airoha/Kconfig | 13 + drivers/phy/airoha/Makefile | 3 + drivers/phy/airoha/phy-airoha-usb.c | 554 ++++++++++++++++++++++++++++ 6 files changed, 574 insertions(+), 1 deletion(-) create mode 100644 drivers/phy/airoha/Kconfig create mode 100644 drivers/phy/airoha/Makefile create mode 100644 drivers/phy/airoha/phy-airoha-usb.c diff --git a/MAINTAINERS b/MAINTAINERS index c2dd385e9165..1835e488ccaa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -758,6 +758,7 @@ M: Christian Marangi L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yam +F: drivers/phy/airoha/phy-airoha-usb.c AIRSPY MEDIA DRIVER L: linux-media@vger.kernel.org diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 8d58efe998ec..19c9c518fc3d 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -93,6 +93,7 @@ config PHY_NXP_PTN3222 schemes. It supports all three USB 2.0 data rates: Low Speed, Full Speed and High Speed. +source "drivers/phy/airoha/Kconfig" source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index e281442acc75..71708c6865b8 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -12,7 +12,8 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o -obj-y += allwinner/ \ +obj-y += airoha/ \ + allwinner/ \ amlogic/ \ broadcom/ \ cadence/ \ diff --git a/drivers/phy/airoha/Kconfig b/drivers/phy/airoha/Kconfig new file mode 100644 index 000000000000..5a2bc2e5d397 --- /dev/null +++ b/drivers/phy/airoha/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for Mediatek devices +# +config PHY_AIROHA_USB + tristate "Airoha USB PHY Driver" + depends on ARCH_AIROHA || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Say 'Y' here to add support for Airoha USB PHY driver. + This driver create the basic PHY instance and provides initialize + callback for USB port. diff --git a/drivers/phy/airoha/Makefile b/drivers/phy/airoha/Makefile new file mode 100644 index 000000000000..deddab0bbc81 --- /dev/null +++ b/drivers/phy/airoha/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_PHY_AIROHA_USB) += phy-airoha-usb.o diff --git a/drivers/phy/airoha/phy-airoha-usb.c b/drivers/phy/airoha/phy-airoha-usb.c new file mode 100644 index 000000000000..efc89c674342 --- /dev/null +++ b/drivers/phy/airoha/phy-airoha-usb.c @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Author: Christian Marangi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* U2PHY */ +#define AIROHA_USB_PHY_FMCR0 0x100 +#define AIROHA_USB_PHY_MONCLK_SEL GENMASK(27, 26) +#define AIROHA_USB_PHY_MONCLK_SEL0 FIELD_PREP_CONST(AIROHA_USB_PHY_MONCLK_SEL, 0x0) +#define AIROHA_USB_PHY_MONCLK_SEL1 FIELD_PREP_CONST(AIROHA_USB_PHY_MONCLK_SEL, 0x1) +#define AIROHA_USB_PHY_MONCLK_SEL2 FIELD_PREP_CONST(AIROHA_USB_PHY_MONCLK_SEL, 0x2) +#define AIROHA_USB_PHY_MONCLK_SEL3 FIELD_PREP_CONST(AIROHA_USB_PHY_MONCLK_SEL, 0x3) +#define AIROHA_USB_PHY_FREQDET_EN BIT(24) +#define AIROHA_USB_PHY_CYCLECNT GENMASK(23, 0) +#define AIROHA_USB_PHY_FMMONR0 0x10c +#define AIROHA_USB_PHY_USB_FM_OUT GENMASK(31, 0) +#define AIROHA_USB_PHY_FMMONR1 0x110 +#define AIROHA_USB_PHY_FRCK_EN BIT(8) + +#define AIROHA_USB_PHY_USBPHYACR4 0x310 +#define AIROHA_USB_PHY_USB20_FS_CR GENMASK(10, 8) +#define AIROHA_USB_PHY_USB20_FS_CR_MAX FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_CR, 0x0) +#define AIROHA_USB_PHY_USB20_FS_CR_NORMAL FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_CR, 0x2) +#define AIROHA_USB_PHY_USB20_FS_CR_SMALLER FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_CR, 0x4) +#define AIROHA_USB_PHY_USB20_FS_CR_MIN FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_CR, 0x6) +#define AIROHA_USB_PHY_USB20_FS_SR GENMASK(2, 0) +#define AIROHA_USB_PHY_USB20_FS_SR_MAX FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_SR, 0x0) +#define AIROHA_USB_PHY_USB20_FS_SR_NORMAL FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_SR, 0x2) +#define AIROHA_USB_PHY_USB20_FS_SR_SMALLER FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_SR, 0x4) +#define AIROHA_USB_PHY_USB20_FS_SR_MIN FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_SR, 0x6) +#define AIROHA_USB_PHY_USBPHYACR5 0x314 +#define AIROHA_USB_PHY_USB20_HSTX_SRCAL_EN BIT(15) +#define AIROHA_USB_PHY_USB20_HSTX_SRCTRL GENMASK(14, 12) +#define AIROHA_USB_PHY_USBPHYACR6 0x318 +#define AIROHA_USB_PHY_USB20_BC11_SW_EN BIT(23) +#define AIROHA_USB_PHY_USB20_DISCTH GENMASK(7, 4) +#define AIROHA_USB_PHY_USB20_DISCTH_400 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x0) +#define AIROHA_USB_PHY_USB20_DISCTH_420 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x1) +#define AIROHA_USB_PHY_USB20_DISCTH_440 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x2) +#define AIROHA_USB_PHY_USB20_DISCTH_460 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x3) +#define AIROHA_USB_PHY_USB20_DISCTH_480 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x4) +#define AIROHA_USB_PHY_USB20_DISCTH_500 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x5) +#define AIROHA_USB_PHY_USB20_DISCTH_520 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x6) +#define AIROHA_USB_PHY_USB20_DISCTH_540 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x7) +#define AIROHA_USB_PHY_USB20_DISCTH_560 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x8) +#define AIROHA_USB_PHY_USB20_DISCTH_580 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x9) +#define AIROHA_USB_PHY_USB20_DISCTH_600 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0xa) +#define AIROHA_USB_PHY_USB20_DISCTH_620 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0xb) +#define AIROHA_USB_PHY_USB20_DISCTH_640 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0xc) +#define AIROHA_USB_PHY_USB20_DISCTH_660 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0xd) +#define AIROHA_USB_PHY_USB20_DISCTH_680 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0xe) +#define AIROHA_USB_PHY_USB20_DISCTH_700 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0xf) +#define AIROHA_USB_PHY_USB20_SQTH GENMASK(3, 0) +#define AIROHA_USB_PHY_USB20_SQTH_85 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x0) +#define AIROHA_USB_PHY_USB20_SQTH_90 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x1) +#define AIROHA_USB_PHY_USB20_SQTH_95 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x2) +#define AIROHA_USB_PHY_USB20_SQTH_100 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x3) +#define AIROHA_USB_PHY_USB20_SQTH_105 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x4) +#define AIROHA_USB_PHY_USB20_SQTH_110 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x5) +#define AIROHA_USB_PHY_USB20_SQTH_115 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x6) +#define AIROHA_USB_PHY_USB20_SQTH_120 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x7) +#define AIROHA_USB_PHY_USB20_SQTH_125 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x8) +#define AIROHA_USB_PHY_USB20_SQTH_130 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x9) +#define AIROHA_USB_PHY_USB20_SQTH_135 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0xa) +#define AIROHA_USB_PHY_USB20_SQTH_140 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0xb) +#define AIROHA_USB_PHY_USB20_SQTH_145 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0xc) +#define AIROHA_USB_PHY_USB20_SQTH_150 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0xd) +#define AIROHA_USB_PHY_USB20_SQTH_155 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0xe) +#define AIROHA_USB_PHY_USB20_SQTH_160 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0xf) + +#define AIROHA_USB_PHY_U2PHYDTM1 0x36c +#define AIROHA_USB_PHY_FORCE_IDDIG BIT(9) +#define AIROHA_USB_PHY_IDDIG BIT(1) + +#define AIROHA_USB_PHY_GPIO_CTLD 0x80c +#define AIROHA_USB_PHY_C60802_GPIO_CTLD GENMASK(31, 0) +#define AIROHA_USB_PHY_SSUSB_IP_SW_RST BIT(31) +#define AIROHA_USB_PHY_MCU_BUS_CK_GATE_EN BIT(30) +#define AIROHA_USB_PHY_FORCE_SSUSB_IP_SW_RST BIT(29) +#define AIROHA_USB_PHY_SSUSB_SW_RST BIT(28) + +#define AIROHA_USB_PHY_U3_PHYA_REG0 0xb00 +#define AIROHA_USB_PHY_SSUSB_BG_DIV GENMASK(29, 28) +#define AIROHA_USB_PHY_SSUSB_BG_DIV_2 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_BG_DIV, 0x0) +#define AIROHA_USB_PHY_SSUSB_BG_DIV_4 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_BG_DIV, 0x1) +#define AIROHA_USB_PHY_SSUSB_BG_DIV_8 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_BG_DIV, 0x2) +#define AIROHA_USB_PHY_SSUSB_BG_DIV_16 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_BG_DIV, 0x3) +#define AIROHA_USB_PHY_U3_PHYA_REG1 0xb04 +#define AIROHA_USB_PHY_SSUSB_XTAL_TOP_RESERVE GENMASK(25, 10) +#define AIROHA_USB_PHY_U3_PHYA_REG6 0xb18 +#define AIROHA_USB_PHY_SSUSB_CDR_RESERVE GENMASK(31, 24) +#define AIROHA_USB_PHY_U3_PHYA_REG8 0xb20 +#define AIROHA_USB_PHY_SSUSB_CDR_RST_DLY GENMASK(7, 6) +#define AIROHA_USB_PHY_SSUSB_CDR_RST_DLY_32 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_CDR_RST_DLY, 0x0) +#define AIROHA_USB_PHY_SSUSB_CDR_RST_DLY_64 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_CDR_RST_DLY, 0x1) +#define AIROHA_USB_PHY_SSUSB_CDR_RST_DLY_128 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_CDR_RST_DLY, 0x2) +#define AIROHA_USB_PHY_SSUSB_CDR_RST_DLY_216 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_CDR_RST_DLY, 0x3) + +#define AIROHA_USB_PHY_U3_PHYA_DA_REG19 0xc38 +#define AIROHA_USB_PHY_SSUSB_PLL_SSC_DELTA1_U3 GENMASK(15, 0) + +#define AIROHA_USB_PHY_U2_FM_DET_CYCLE_CNT 1024 +#define AIROHA_USB_PHY_REF_CK 20 +#define AIROHA_USB_PHY_U2_SR_COEF 28 +#define AIROHA_USB_PHY_U2_SR_COEF_DIVISOR 1000 + +#define AIROHA_USB_PHY_FREQDET_SLEEP 1000 /* 1ms */ +#define AIROHA_USB_PHY_FREQDET_TIMEOUT (AIROHA_USB_PHY_FREQDET_SLEEP * 10) + +#define AIROHA_USB_PHY_MAX_INSTANCE 2 + +struct airoha_usb_phy_instance { + struct phy *phy; + u32 type; +}; + +struct airoha_usb_phy_priv { + struct device *dev; + + struct regmap *regmap; + + unsigned int id; + + struct airoha_usb_phy_instance *phys[AIROHA_USB_PHY_MAX_INSTANCE]; +}; + +static int airoha_usb_phy_u2_slew_rate_calibration(struct airoha_usb_phy_priv *priv) +{ + u32 fm_out; + u32 srctrl; + + /* Enable HS TX SR calibration */ + regmap_set_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR5, + AIROHA_USB_PHY_USB20_HSTX_SRCAL_EN); + + usleep_range(1000, 1500); + + /* Enable Free run clock */ + regmap_set_bits(priv->regmap, AIROHA_USB_PHY_FMMONR1, + AIROHA_USB_PHY_FRCK_EN); + + /* Select Monitor Clock */ + regmap_update_bits(priv->regmap, AIROHA_USB_PHY_FMCR0, + AIROHA_USB_PHY_MONCLK_SEL, + priv->id == 0 ? AIROHA_USB_PHY_MONCLK_SEL0 : + AIROHA_USB_PHY_MONCLK_SEL1); + + /* Set cyclecnt */ + regmap_update_bits(priv->regmap, AIROHA_USB_PHY_FMCR0, + AIROHA_USB_PHY_CYCLECNT, + FIELD_PREP(AIROHA_USB_PHY_CYCLECNT, + AIROHA_USB_PHY_U2_FM_DET_CYCLE_CNT)); + + /* Enable Frequency meter */ + regmap_set_bits(priv->regmap, AIROHA_USB_PHY_FMCR0, + AIROHA_USB_PHY_FREQDET_EN); + + /* Timeout can happen and we will apply workaround at the end */ + regmap_read_poll_timeout(priv->regmap, AIROHA_USB_PHY_FMMONR0, fm_out, + fm_out, AIROHA_USB_PHY_FREQDET_SLEEP, + AIROHA_USB_PHY_FREQDET_TIMEOUT); + + /* Disable Frequency meter */ + regmap_clear_bits(priv->regmap, AIROHA_USB_PHY_FMCR0, + AIROHA_USB_PHY_FREQDET_EN); + + /* Disable Free run clock */ + regmap_clear_bits(priv->regmap, AIROHA_USB_PHY_FMMONR1, + AIROHA_USB_PHY_FRCK_EN); + + /* Disable HS TX SR calibration */ + regmap_clear_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR5, + AIROHA_USB_PHY_USB20_HSTX_SRCAL_EN); + + usleep_range(1000, 1500); + + /* Frequency was not detected, use default SR calibration value */ + if (!fm_out) { + srctrl = 0x5; + dev_err(priv->dev, "Frequency not detected, using default SR calibration.\n"); + /* (1024 / FM_OUT) * REF_CK * U2_SR_COEF (round to the nearest digits) */ + } else { + srctrl = AIROHA_USB_PHY_REF_CK * AIROHA_USB_PHY_U2_SR_COEF; + srctrl = (srctrl * AIROHA_USB_PHY_U2_FM_DET_CYCLE_CNT) / fm_out; + srctrl = DIV_ROUND_CLOSEST(srctrl, AIROHA_USB_PHY_U2_SR_COEF_DIVISOR); + dev_dbg(priv->dev, "SR calibration applied: %x\n", srctrl); + } + + regmap_update_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR5, + AIROHA_USB_PHY_USB20_HSTX_SRCTRL, + FIELD_PREP(AIROHA_USB_PHY_USB20_HSTX_SRCTRL, srctrl)); + + return 0; +} + +static int airoha_usb_phy_u2_init(struct airoha_usb_phy_priv *priv) +{ + regmap_update_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR4, + AIROHA_USB_PHY_USB20_FS_CR, + AIROHA_USB_PHY_USB20_FS_CR_MIN); + + regmap_update_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR4, + AIROHA_USB_PHY_USB20_FS_SR, + AIROHA_USB_PHY_USB20_FS_SR_NORMAL); + + /* FIXME: evaluate if needed */ + regmap_update_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR6, + AIROHA_USB_PHY_USB20_SQTH, + AIROHA_USB_PHY_USB20_SQTH_130); + + regmap_update_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR6, + AIROHA_USB_PHY_USB20_DISCTH, + AIROHA_USB_PHY_USB20_DISCTH_600); + + /* Enable the USB port and then disable after calibration */ + regmap_clear_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR6, + AIROHA_USB_PHY_USB20_BC11_SW_EN); + + airoha_usb_phy_u2_slew_rate_calibration(priv); + + regmap_set_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR6, + AIROHA_USB_PHY_USB20_BC11_SW_EN); + + usleep_range(1000, 1500); + + return 0; +} + +/* + * USB 3.0 mode can only work if USB serdes is correctly set. + * This is validated in xLate function. + */ +static int airoha_usb_phy_u3_init(struct airoha_usb_phy_priv *priv) +{ + regmap_update_bits(priv->regmap, AIROHA_USB_PHY_U3_PHYA_REG8, + AIROHA_USB_PHY_SSUSB_CDR_RST_DLY, + AIROHA_USB_PHY_SSUSB_CDR_RST_DLY_32); + + regmap_update_bits(priv->regmap, AIROHA_USB_PHY_U3_PHYA_REG6, + AIROHA_USB_PHY_SSUSB_CDR_RESERVE, + FIELD_PREP(AIROHA_USB_PHY_SSUSB_CDR_RESERVE, 0xe)); + + regmap_update_bits(priv->regmap, AIROHA_USB_PHY_U3_PHYA_REG0, + AIROHA_USB_PHY_SSUSB_BG_DIV, + AIROHA_USB_PHY_SSUSB_BG_DIV_4); + + regmap_set_bits(priv->regmap, AIROHA_USB_PHY_U3_PHYA_REG1, + FIELD_PREP(AIROHA_USB_PHY_SSUSB_XTAL_TOP_RESERVE, 0x600)); + + regmap_update_bits(priv->regmap, AIROHA_USB_PHY_U3_PHYA_DA_REG19, + AIROHA_USB_PHY_SSUSB_PLL_SSC_DELTA1_U3, + FIELD_PREP(AIROHA_USB_PHY_SSUSB_PLL_SSC_DELTA1_U3, 0x43)); + + return 0; +} + +static int airoha_usb_phy_init(struct phy *phy) +{ + struct airoha_usb_phy_instance *instance = phy_get_drvdata(phy); + struct airoha_usb_phy_priv *priv = dev_get_drvdata(phy->dev.parent); + + if (instance->type == PHY_TYPE_USB2) + return airoha_usb_phy_u2_init(priv); + + return airoha_usb_phy_u3_init(priv); +} + +static int airoha_usb_phy_exit(struct phy *phy) +{ + return 0; +} + +static int airoha_usb_phy_u2_power_on(struct airoha_usb_phy_priv *priv) +{ + regmap_clear_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR6, + AIROHA_USB_PHY_USB20_BC11_SW_EN); + + usleep_range(1000, 1500); + + return 0; +} + +static int airoha_usb_phy_u3_power_on(struct airoha_usb_phy_priv *priv) +{ + regmap_clear_bits(priv->regmap, AIROHA_USB_PHY_GPIO_CTLD, + AIROHA_USB_PHY_SSUSB_IP_SW_RST | + AIROHA_USB_PHY_MCU_BUS_CK_GATE_EN | + AIROHA_USB_PHY_FORCE_SSUSB_IP_SW_RST | + AIROHA_USB_PHY_SSUSB_SW_RST); + + usleep_range(1000, 1500); + + return 0; +} + +static int airoha_usb_phy_power_on(struct phy *phy) +{ + struct airoha_usb_phy_instance *instance = phy_get_drvdata(phy); + struct airoha_usb_phy_priv *priv = dev_get_drvdata(phy->dev.parent); + + if (instance->type == PHY_TYPE_USB2) + return airoha_usb_phy_u2_power_on(priv); + + return airoha_usb_phy_u3_power_on(priv); +} + +static int airoha_usb_phy_u2_power_off(struct airoha_usb_phy_priv *priv) +{ + regmap_set_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR6, + AIROHA_USB_PHY_USB20_BC11_SW_EN); + + usleep_range(1000, 1500); + + return 0; +} + +static int airoha_usb_phy_u3_power_off(struct airoha_usb_phy_priv *priv) +{ + regmap_set_bits(priv->regmap, AIROHA_USB_PHY_GPIO_CTLD, + AIROHA_USB_PHY_SSUSB_IP_SW_RST | + AIROHA_USB_PHY_FORCE_SSUSB_IP_SW_RST); + + usleep_range(1000, 1500); + + return 0; +} + +static int airoha_usb_phy_power_off(struct phy *phy) +{ + struct airoha_usb_phy_instance *instance = phy_get_drvdata(phy); + struct airoha_usb_phy_priv *priv = dev_get_drvdata(phy->dev.parent); + + if (instance->type == PHY_TYPE_USB2) + return airoha_usb_phy_u2_power_off(priv); + + return airoha_usb_phy_u3_power_off(priv); +} + +static int airoha_usb_phy_u2_set_mode(struct airoha_usb_phy_priv *priv, + enum phy_mode mode) +{ + u32 val = 0; + + /* + * For Device and Host mode, enable force IDDIG. + * For Device set IDDIG, for Host clear IDDIG. + * For OTG disable force and clear IDDIG bit while at it. + */ + switch (mode) { + case PHY_MODE_USB_DEVICE: + val |= AIROHA_USB_PHY_IDDIG; + fallthrough; + case PHY_MODE_USB_HOST: + val |= AIROHA_USB_PHY_FORCE_IDDIG; + break; + case PHY_MODE_USB_OTG: + break; + default: + return 0; + } + + regmap_update_bits(priv->regmap, AIROHA_USB_PHY_U2PHYDTM1, + AIROHA_USB_PHY_FORCE_IDDIG | + AIROHA_USB_PHY_IDDIG, val); + + return 0; +} + +static int airoha_usb_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct airoha_usb_phy_instance *instance = phy_get_drvdata(phy); + struct airoha_usb_phy_priv *priv = dev_get_drvdata(phy->dev.parent); + + if (instance->type == PHY_TYPE_USB2) + return airoha_usb_phy_u2_set_mode(priv, mode); + + return 0; +} + +static struct phy *airoha_usb_phy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct airoha_usb_phy_priv *priv = dev_get_drvdata(dev); + struct airoha_usb_phy_instance *instance = NULL; + struct device_node *phy_np = args->np; + int index; + + if (args->args_count != 1) { + dev_err(dev, "invalid number of cells in 'phy' property\n"); + return ERR_PTR(-EINVAL); + } + + for (index = 0; index < AIROHA_USB_PHY_MAX_INSTANCE; index++) + if (phy_np == priv->phys[index]->phy->dev.of_node) { + instance = priv->phys[index]; + break; + } + + if (!instance) { + dev_err(dev, "failed to find appropriate phy\n"); + return ERR_PTR(-EINVAL); + } + + instance->type = args->args[0]; + if (!(instance->type == PHY_TYPE_USB2 || instance->type == PHY_TYPE_USB3)) { + dev_err(dev, "unsupported device type: %d\n", instance->type); + return ERR_PTR(-EINVAL); + } + + /* Validate Serdes for USB 3.0 */ + if (instance->type == PHY_TYPE_USB3) { + enum airoha_scu_serdes_port serdes_port; + int serdes_mode, expcted_mode; + + switch (priv->id) { + case 0: + serdes_port = AIROHA_SCU_SERDES_USB1; + expcted_mode = AIROHA_SCU_SSR_USB1_USB; + break; + case 1: + serdes_port = AIROHA_SCU_SERDES_USB2; + expcted_mode = AIROHA_SCU_SSR_USB2_USB; + break; + default: /* Impossible already validated */ + return ERR_PTR(-EINVAL); + } + + serdes_mode = airoha_scu_ssr_get_serdes_mode(dev, serdes_port); + if (serdes_mode < 0) { + dev_err(dev, "failed validating serdes mode for port %d: %d\n", + priv->id, serdes_mode); + return ERR_PTR(serdes_mode); + } + + if (serdes_mode != expcted_mode) { + dev_err(dev, "wrong serdes mode for port %d\n", + priv->id); + return ERR_PTR(-EINVAL); + } + } + + return instance->phy; +} + +static const struct phy_ops airoha_phy = { + .init = airoha_usb_phy_init, + .exit = airoha_usb_phy_exit, + .power_on = airoha_usb_phy_power_on, + .power_off = airoha_usb_phy_power_off, + .set_mode = airoha_usb_phy_set_mode, + .owner = THIS_MODULE, +}; + +static const struct regmap_config airoha_usb_phy_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static int airoha_usb_phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct airoha_usb_phy_priv *priv; + struct device *dev = &pdev->dev; + struct device_node *child_np; + void *base; + int port; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + + ret = of_property_read_u32(dev->of_node, "airoha,port-id", &priv->id); + if (ret) + return dev_err_probe(dev, ret, "port ID is mandatory for USB PHY calibration.\n"); + + if (priv->id > 1) + return dev_err_probe(dev, -EINVAL, "only 2 USB port are supported on the SoC.\n"); + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->regmap = devm_regmap_init_mmio(dev, base, &airoha_usb_phy_regmap_config); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + platform_set_drvdata(pdev, priv); + + port = 0; + for_each_child_of_node(dev->of_node, child_np) { + struct airoha_usb_phy_instance *instance; + + instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); + if (!instance) { + ret = -ENOMEM; + goto put_child; + } + + priv->phys[port] = instance; + + instance->phy = devm_phy_create(dev, child_np, &airoha_phy); + if (IS_ERR(instance->phy)) { + dev_err_probe(dev, PTR_ERR(instance->phy), "failed to create phy\n"); + ret = PTR_ERR(instance->phy); + goto put_child; + } + + phy_set_drvdata(instance->phy, instance); + + port++; + } + + phy_provider = devm_of_phy_provider_register(&pdev->dev, airoha_usb_phy_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); + +put_child: + of_node_put(child_np); + return ret; +} + +static const struct of_device_id airoha_phy_id_table[] = { + { .compatible = "airoha,an7581-usb-phy" }, + { }, +}; +MODULE_DEVICE_TABLE(of, airoha_phy_id_table); + +static struct platform_driver airoha_usb_driver = { + .probe = airoha_usb_phy_probe, + .driver = { + .name = "airoha-usb-phy", + .of_match_table = airoha_phy_id_table, + }, +}; + +module_platform_driver(airoha_usb_driver); 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:55 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 11/13] usb: host: add ARCH_AIROHA in XHCI MTK dependency Date: Sun, 9 Mar 2025 14:29:42 +0100 Message-ID: <20250309132959.19045-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Airoha SoC use the same register map a logic of the Mediatek xHCI driver, hence add it to the dependency list to permit compilation also on this ARCH. Signed-off-by: Christian Marangi --- drivers/usb/host/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index d011d6c753ed..9d8626f36ca6 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -71,7 +71,7 @@ config USB_XHCI_HISTB config USB_XHCI_MTK tristate "xHCI support for MediaTek SoCs" select MFD_SYSCON - depends on (MIPS && SOC_MT7621) || ARCH_MEDIATEK || COMPILE_TEST + depends on (MIPS && SOC_MT7621) || ARCH_MEDIATEK || ARCH_AIROHA || COMPILE_TEST help Say 'Y' to enable the support for the xHCI host controller found in MediaTek SoCs. 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:57 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 12/13] arm64: dts: airoha: en7581: convert SCU clock node to MFD implementation Date: Sun, 9 Mar 2025 14:29:43 +0100 Message-ID: <20250309132959.19045-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert SCU clock node for Airoha EN7581 to MFD implementation in preparation for USB support. Signed-off-by: Christian Marangi --- arch/arm64/boot/dts/airoha/en7581.dtsi | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi index 26b136940917..dfc12fa99748 100644 --- a/arch/arm64/boot/dts/airoha/en7581.dtsi +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi @@ -173,11 +173,16 @@ spi_nand: nand@0 { }; }; - scuclk: clock-controller@1fb00000 { - compatible = "airoha,en7581-scu"; + system-controller@1fb00000 { + compatible = "airoha,en7581-scu-sysctl", "syscon", "simple-mfd"; reg = <0x0 0x1fb00000 0x0 0x970>; - #clock-cells = <1>; - #reset-cells = <1>; + + scuclk: clock-controller { + compatible = "airoha,en7581-scu"; + + #clock-cells = <1>; + #reset-cells = <1>; + }; }; uart1: serial@1fbf0000 { From patchwork Sun Mar 9 13:29:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 14008435 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5C901F8759; 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[93.34.90.129]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3912bee262esm11867536f8f.0.2025.03.09.06.30.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 06:30:58 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: [PATCH 13/13] arm64: dts: airoha: en7581: add USB and SCU SSR nodes Date: Sun, 9 Mar 2025 14:29:44 +0100 Message-ID: <20250309132959.19045-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309132959.19045-1-ansuelsmth@gmail.com> References: <20250309132959.19045-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add SCU SSR and USB nodes required for USB support of Airoha EN7581. SCU SSR node is required to read and configure the current Serdes mode of the USB PHYs. Signed-off-by: Christian Marangi --- arch/arm64/boot/dts/airoha/en7581.dtsi | 61 ++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi index dfc12fa99748..5975da11ace0 100644 --- a/arch/arm64/boot/dts/airoha/en7581.dtsi +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include / { @@ -183,6 +184,10 @@ scuclk: clock-controller { #clock-cells = <1>; #reset-cells = <1>; }; + + scu_ssr: system-controller { + compatible = "airoha,an7581-scu-ssr"; + }; }; uart1: serial@1fbf0000 { @@ -200,6 +205,62 @@ rng@1faa1000 { interrupts = ; }; + usb0: usb@1fab0000 { + compatible = "mediatek,mtk-xhci"; + reg = <0x0 0x1fab0000 0x0 0x3e00>, + <0x0 0x1fab3e00 0x0 0x100>; + reg-names = "mac", "ippc"; + interrupts = ; + + phys = <&usb0_u2 PHY_TYPE_USB2>, <&usb0_u3 PHY_TYPE_USB3>; + + status = "disabled"; + }; + + phy@1fac0000 { + compatible = "airoha,an7581-usb-phy"; + reg = <0x0 0x1fac0000 0x0 0x10000>; + + airoha,port-id = <0>; + airoha,scu-ssr = <&scu_ssr>; + + usb0_u2: usb2-phy { + #phy-cells = <1>; + }; + + usb0_u3: usb3-phy { + #phy-cells = <1>; + }; + }; + + usb1: usb@1fad0000 { + compatible = "mediatek,mtk-xhci"; + reg = <0x0 0x1fad0000 0x0 0x3e00>, + <0x0 0x1fad3e00 0x0 0x100>; + reg-names = "mac", "ippc"; + interrupts = ; + + phys = <&usb1_u2 PHY_TYPE_USB2>, <&usb0_u3 PHY_TYPE_USB3>; + + status = "disabled"; + }; + + phy@1fae0000 { + compatible = "airoha,an7581-usb-phy"; + reg = <0x0 0x1fae0000 0x0 0x10000>; + + airoha,port-id = <1>; + airoha,scu-ssr = <&scu_ssr>; + + usb1_u2: usb2-phy { + #phy-cells = <1>; + }; + + usb1_u3: usb3-phy { + #phy-cells = <1>; + }; + }; + system-controller@1fbf0200 { compatible = "airoha,en7581-gpio-sysctl", "syscon", "simple-mfd";