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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43cfbae50aasm4331045e9.8.2025.03.09.17.06.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:06:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 01/14] hw/qdev-properties-system: Include missing 'qapi/qapi-types-common.h' Date: Mon, 10 Mar 2025 01:06:07 +0100 Message-ID: <20250310000620.70120-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org DEFINE_PROP_ENDIAN_NODEFAULT() macro uses ENDIAN_MODE_UNSPECIFIED which is defined in "qapi/qapi-types-common.h". Fixes: 4ec96630f93 ("hw/qdev-properties-system: Introduce EndianMode QAPI enum") Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-properties-system.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/qdev-properties-system.h b/include/hw/qdev-properties-system.h index b921392c525..49a3825eb46 100644 --- a/include/hw/qdev-properties-system.h +++ b/include/hw/qdev-properties-system.h @@ -1,6 +1,7 @@ #ifndef HW_QDEV_PROPERTIES_SYSTEM_H #define HW_QDEV_PROPERTIES_SYSTEM_H +#include "qapi/qapi-types-common.h" #include "hw/qdev-properties.h" bool qdev_prop_sanitize_s390x_loadparm(uint8_t *loadparm, const char *str, From patchwork Mon Mar 10 00:06:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 14009108 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2A7CC28B2E for ; Mon, 10 Mar 2025 00:09:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1trQfQ-0001uk-30; Sun, 09 Mar 2025 20:06:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1trQfL-0001pv-47 for qemu-devel@nongnu.org; Sun, 09 Mar 2025 20:06:43 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1trQfD-0007It-LK for qemu-devel@nongnu.org; Sun, 09 Mar 2025 20:06:42 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-43cfa7e7f54so1252325e9.1 for ; Sun, 09 Mar 2025 17:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741565194; x=1742169994; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QSCzkaWIhjHTeY3hvC0iPh38QiDjdtlUv2/bUUP3CZQ=; b=xB3cRIu4YwBsEV1XSmZOJ8cIlthIe+qreXMWFecgSQJm46m72J95mycCX9CQWMwDZl NvK9BD21pm7hA6ZHKElqRIz+1Z/qbn2WBBLkfct5+ax9FJY+wXkC2yvm4kvgLX8HW8py XfpqhoN+KCPo9mQ/SmyHA4dBiS4xXkPhOXiQA286SjXRvfZqW6NO7ZQEdnxcZWZW5rOZ HjWj8x4Y2V43poiejokYBhHlNZWbidDz7svgx+YWB5k3B3ggrdOAqCfayOxglFicuZKD Tiszd20zCJUDnrHkEwWp1Rn8IIC4UWKdAOdnsoVEvC/GbFHzKG+AtkLwprznSH3FIvBl GaCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741565194; x=1742169994; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QSCzkaWIhjHTeY3hvC0iPh38QiDjdtlUv2/bUUP3CZQ=; b=SoNXgaFpx5lMFwRe/akjNM423i6QnWTgtxIAQIkcCRed6SHW4FIbL+P48yF0YmiEa9 YEdyeS8vZM/0V7+SutkTWYDBVocPyUYQPYr/Iw504NCAtLML+aYKxqFJ42YXtyJDIepV urmpFhPO6QPFQip8MgBeKBZeplnOJWjY4pK8Ar1g+/gWI4zJPlng31Uu+nJXtQKjAi/c Cham/+x46nFmFSBliGlhVtL561kUohoYDEkd/iuB/TsbuBxEdaqA5hdbPmIQsS0B/Zb+ WVnvblriXUbIDIKYusjr5FF+V/of2wjClr24Tdmmzxp77kVfXHjv7IoBIPQCBV0K+Upt C8Tg== X-Forwarded-Encrypted: i=1; AJvYcCWIhKm97Rajuc+KpHy6DmWr2jKrbPefFqBRGaFb6Bvrhsvm/y2xQ1esuRVdF0tPyp6kWK1ud+hfDbfP@nongnu.org X-Gm-Message-State: AOJu0YyQMP1xqYMyOcQthUs/SLuCC5Wrb3ziP0vU3rrN+rc9QUqDLrrX n43XCcpWoHTkzxlYNUhIcpPuMAH3ChTHExSqNyfydwd3JBMRXm0Xb8Im6PfXukg= X-Gm-Gg: ASbGncv8i7ePiFmTxbHnpu2bnpB4yktjS0SyJFOLVG7XAOfwmbK6pY54Jd07t2tWxfy RV83vzNUqSeNF0fqYRpEXEpKoxnnq9/ncRpX6j6Ju59r/6W8ImTA7ffrTLTVzyDVP36seB43xAA 9zbshMaxpmjRqv+K6li8X0NB2uU7xE90M5Qw0AziXB0n3WIXRhR3XCHirWoqotrbZQgN9ydKRhF RLPDqPZXweLSy7MhyzKNtQewtyUOn3/q9G+RIF/fY5XLkrFpNgddWAFUu1I3V4wz+mnSthbfLnh /ZLk+ERo/G5+nqq3eXNBx45rpuqFJf+zwTcPjNHSXC00pT3wvY+GFPEzErQt+82gnhiqfToBOQe nUqAA2nG7sZpl4URTng4= X-Google-Smtp-Source: AGHT+IFbKwVNHM+WpFEKBfNJvsjk7dqcL6E6e9F2hjbj3R6N2hwQR7KolOqI9zLWIxHHnb9PxpCqKA== X-Received: by 2002:a05:600c:4ba8:b0:43b:4829:8067 with SMTP id 5b1f17b1804b1-43ce4abb2f5mr41307265e9.6.1741565194123; Sun, 09 Mar 2025 17:06:34 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43cea7f2afasm32401525e9.3.2025.03.09.17.06.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:06:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 02/14] hw/sd/sdhci: Remove need for SDHCIState::vendor field Date: Mon, 10 Mar 2025 01:06:08 +0100 Message-ID: <20250310000620.70120-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All instances of TYPE_IMX_USDHC set vendor=SDHCI_VENDOR_IMX. No need to special-case it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan Reviewed-by: Bernhard Beschow --- hw/sd/sdhci-internal.h | 1 - include/hw/sd/sdhci.h | 4 ---- hw/arm/fsl-imx25.c | 2 -- hw/arm/fsl-imx6.c | 2 -- hw/arm/fsl-imx6ul.c | 2 -- hw/arm/fsl-imx7.c | 2 -- hw/arm/fsl-imx8mp.c | 2 -- hw/sd/sdhci.c | 14 ++++---------- 8 files changed, 4 insertions(+), 25 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 9f768c418e0..9072b06bdde 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -311,7 +311,6 @@ extern const VMStateDescription sdhci_vmstate; DEFINE_PROP_UINT8("endianness", _state, endianness, DEVICE_LITTLE_ENDIAN), \ DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \ - DEFINE_PROP_UINT8("vendor", _state, vendor, SDHCI_VENDOR_NONE), \ \ /* Capabilities registers provide information on supported * features of this specific host controller implementation */ \ diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 38c08e28598..48247e9a20f 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -99,7 +99,6 @@ struct SDHCIState { uint8_t endianness; uint8_t sd_spec_version; uint8_t uhs_mode; - uint8_t vendor; /* For vendor specific functionality */ /* * Write Protect pin default active low for detecting SD card * to be protected. Set wp_inverted to invert the signal. @@ -108,9 +107,6 @@ struct SDHCIState { }; typedef struct SDHCIState SDHCIState; -#define SDHCI_VENDOR_NONE 0 -#define SDHCI_VENDOR_IMX 1 - /* * Controller does not provide transfer-complete interrupt when not * busy. diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 5359a6d8d3b..02214ca1a1c 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -243,8 +243,6 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) &error_abort); object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", IMX25_ESDHC_CAPABILITIES, &error_abort); - object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", - SDHCI_VENDOR_IMX, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) { return; } diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index dc86338b3a5..a114dc0d63d 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -327,8 +327,6 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) &error_abort); object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", IMX6_ESDHC_CAPABILITIES, &error_abort); - object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", - SDHCI_VENDOR_IMX, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) { return; } diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 34c4aa15cd0..ce8d3ef535f 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -531,8 +531,6 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_USDHC2_IRQ, }; - object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", - SDHCI_VENDOR_IMX, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 3374018cde0..ed1f10bca26 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -471,8 +471,6 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) FSL_IMX7_USDHC3_IRQ, }; - object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", - SDHCI_VENDOR_IMX, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 1ea98e14635..c3f6da63220 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -524,8 +524,6 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp) { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC3].addr, FSL_IMX8MP_USDHC3_IRQ }, }; - object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", - SDHCI_VENDOR_IMX, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), errp)) { return; } diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 1f45a77566c..149b748cbee 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1731,16 +1731,10 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) case USDHC_VENDOR_SPEC: s->vendor_spec = value; - switch (s->vendor) { - case SDHCI_VENDOR_IMX: - if (value & USDHC_IMX_FRC_SDCLK_ON) { - s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; - } else { - s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; - } - break; - default: - break; + if (value & USDHC_IMX_FRC_SDCLK_ON) { + s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c0e1476sm13191032f8f.70.2025.03.09.17.06.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:06:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 03/14] hw/sd/sdhci: Redefine SDHCI_QUIRK_NO_BUSY_IRQ bitmask as bit Date: Mon, 10 Mar 2025 01:06:09 +0100 Message-ID: <20250310000620.70120-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 8 ++++---- hw/sd/sdhci.c | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 48247e9a20f..096d607f4b7 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -108,13 +108,13 @@ struct SDHCIState { typedef struct SDHCIState SDHCIState; /* - * Controller does not provide transfer-complete interrupt when not - * busy. - * * NOTE: This definition is taken out of Linux kernel and so the * original bit number is preserved */ -#define SDHCI_QUIRK_NO_BUSY_IRQ BIT(14) +enum { + /* Controller does not provide transfer-complete interrupt when not busy. */ + SDHCI_QUIRK_NO_BUSY_IRQ = 14, +}; #define TYPE_PCI_SDHCI "sdhci-pci" DECLARE_INSTANCE_CHECKER(SDHCIState, PCI_SDHCI, diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 149b748cbee..1dc942a0e06 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -366,7 +366,7 @@ static void sdhci_send_command(SDHCIState *s) } } - if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && + if (!(s->quirks & BIT(SDHCI_QUIRK_NO_BUSY_IRQ)) && (s->norintstsen & SDHC_NISEN_TRSCMP) && (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { s->norintsts |= SDHC_NIS_TRSCMP; @@ -1886,7 +1886,7 @@ static void imx_usdhc_init(Object *obj) SDHCIState *s = SYSBUS_SDHCI(obj); s->io_ops = &usdhc_mmio_ops; - s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd8db6c7sm127555375e9.22.2025.03.09.17.06.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:06:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 04/14] hw/sd/sdhci: Include 'wp-inverted' property in quirk bitmask Date: Mon, 10 Mar 2025 01:06:10 +0100 Message-ID: <20250310000620.70120-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Import Linux's SDHCI_QUIRK_INVERTED_WRITE_PROTECT quirk definition. Replace 'wp_inverted' boolean by a bit in quirk bitmask. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 16 ++++++++++------ hw/arm/aspeed.c | 2 +- hw/sd/sdhci.c | 6 +++--- 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 096d607f4b7..d2e4f0f0050 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -30,7 +30,14 @@ #include "hw/sd/sd.h" #include "qom/object.h" -/* SD/MMC host controller state */ +/* + * SD/MMC host controller state + * + * QEMU interface: + * + QOM property "wp-inverted-quirk" inverts the Write Protect pin + * polarity (by default the polarity is active low for detecting SD + * card to be protected). + */ struct SDHCIState { /*< private >*/ union { @@ -99,11 +106,6 @@ struct SDHCIState { uint8_t endianness; uint8_t sd_spec_version; uint8_t uhs_mode; - /* - * Write Protect pin default active low for detecting SD card - * to be protected. Set wp_inverted to invert the signal. - */ - bool wp_inverted; }; typedef struct SDHCIState SDHCIState; @@ -114,6 +116,8 @@ typedef struct SDHCIState SDHCIState; enum { /* Controller does not provide transfer-complete interrupt when not busy. */ SDHCI_QUIRK_NO_BUSY_IRQ = 14, + /* Controller reports inverted write-protect state */ + SDHCI_QUIRK_INVERTED_WRITE_PROTECT = 16, }; #define TYPE_PCI_SDHCI "sdhci-pci" diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 98bf071139b..daee2376d50 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -412,7 +412,7 @@ static void aspeed_machine_init(MachineState *machine) if (amc->sdhci_wp_inverted) { for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), - "wp-inverted", true, &error_abort); + "wp-inverted-quirk", true, &error_abort); } } if (machine->kernel_filename) { diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 1dc942a0e06..19c600d5bfc 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -274,7 +274,7 @@ static void sdhci_set_readonly(DeviceState *dev, bool level) { SDHCIState *s = (SDHCIState *)dev; - if (s->wp_inverted) { + if (s->quirks & BIT(SDHCI_QUIRK_INVERTED_WRITE_PROTECT)) { level = !level; } @@ -1555,12 +1555,12 @@ void sdhci_common_class_init(ObjectClass *klass, const void *data) static const Property sdhci_sysbus_properties[] = { DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), + DEFINE_PROP_BIT("wp-inverted-quirk", SDHCIState, quirks, + SDHCI_QUIRK_INVERTED_WRITE_PROTECT, false), DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, false), DEFINE_PROP_LINK("dma", SDHCIState, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_BOOL("wp-inverted", SDHCIState, - wp_inverted, false), }; static void sdhci_sysbus_init(Object *obj) From patchwork Mon Mar 10 00:06:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 14009106 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E971DC28B28 for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfad7sm13082199f8f.26.2025.03.09.17.06.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:06:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 05/14] hw/sd/sdhci: Include 'pending-insert-quirk' property in quirk bitmask Date: Mon, 10 Mar 2025 01:06:11 +0100 Message-ID: <20250310000620.70120-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Import Linux's SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET quirk definition. Replace 'pending_insert_quirk' boolean (originally introduce in commit 0a7ac9f9e72 "sdhci: quirk property for card insert interrupt status on Raspberry Pi") by a bit in quirk bitmask. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 5 ++++- hw/sd/sdhci.c | 8 ++++---- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index d2e4f0f0050..2e6e719df7b 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -34,6 +34,8 @@ * SD/MMC host controller state * * QEMU interface: + * + QOM property "pending-insert-quirk" re-enables pending "card inserted" + * IRQ after reset (used by the Raspberry Pi controllers). * + QOM property "wp-inverted-quirk" inverts the Write Protect pin * polarity (by default the polarity is active low for detecting SD * card to be protected). @@ -101,7 +103,6 @@ struct SDHCIState { /* RO Host Controller Version Register always reads as 0x2401 */ /* Configurable properties */ - bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */ uint32_t quirks; uint8_t endianness; uint8_t sd_spec_version; @@ -118,6 +119,8 @@ enum { SDHCI_QUIRK_NO_BUSY_IRQ = 14, /* Controller reports inverted write-protect state */ SDHCI_QUIRK_INVERTED_WRITE_PROTECT = 16, + /* Controller losing signal/interrupt enable states after reset */ + SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET = 19, }; #define TYPE_PCI_SDHCI "sdhci-pci" diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 19c600d5bfc..d1b1b187874 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -320,7 +320,7 @@ static void sdhci_poweron_reset(DeviceState *dev) sdhci_reset(s); - if (s->pending_insert_quirk) { + if (s->quirks & BIT(SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)) { s->pending_insert_state = true; } } @@ -1307,7 +1307,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) * appears when first enabled after power on */ if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { - assert(s->pending_insert_quirk); + assert(s->quirks & BIT(SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)); s->norintsts |= SDHC_NIS_INSERT; s->pending_insert_state = false; } @@ -1557,8 +1557,8 @@ static const Property sdhci_sysbus_properties[] = { DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), DEFINE_PROP_BIT("wp-inverted-quirk", SDHCIState, quirks, SDHCI_QUIRK_INVERTED_WRITE_PROTECT, false), - DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, - false), + DEFINE_PROP_BIT("pending-insert-quirk", SDHCIState, quirks, + SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET, false), DEFINE_PROP_LINK("dma", SDHCIState, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), }; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfe0004sm12885561f8f.40.2025.03.09.17.06.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:06:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 06/14] hw/sd/sdhci: Introduce SDHCIClass stub Date: Mon, 10 Mar 2025 01:06:12 +0100 Message-ID: <20250310000620.70120-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org TYPE_SYSBUS_SDHCI is a bit odd because it uses an union to work with both SysBus / PCI parent. For this reason, we can not use the OBJECT_DECLARE_TYPE() macro twice (on SYSBUS_SDHCI & PCI_SDHCI) and we must keep a pair of lower DECLARE_INSTANCE_CHECKER) and DECLARE_CLASS_CHECKERS() for PCI, in order to avoid: include/hw/sd/sdhci.h:165:1: error: redefinition of 'glib_autoptr_clear_SDHCIState' include/hw/sd/sdhci.h:165:1: error: redefinition of 'glib_autoptr_cleanup_SDHCIState' include/hw/sd/sdhci.h:165:1: error: redefinition of 'glib_autoptr_destroy_SDHCIState' include/hw/sd/sdhci.h:165:1: error: redefinition of 'glib_listautoptr_cleanup_SDHCIState' include/hw/sd/sdhci.h:165:1: error: redefinition of 'glib_slistautoptr_cleanup_SDHCIState' include/hw/sd/sdhci.h:165:1: error: redefinition of 'glib_queueautoptr_cleanup_SDHCIState' 165 | OBJECT_DECLARE_TYPE(SDHCIState, SDHCIClass, SYSBUS_SDHCI) | ^ include/hw/sd/sdhci.h:158:1: note: previous definition is here 158 | OBJECT_DECLARE_TYPE(SDHCIState, SDHCIClass, PCI_SDHCI) | ^ Since we can not use SYSBUS_SDHCI_GET_CLASS() on PCI instances, cache the class reference in the object state as 'sc'. As this is not a normal use, introduce SDHCIClass in its own commit. Signed-off-by: Philippe Mathieu-Daudé --- I plan to remove the union later. --- include/hw/sd/sdhci.h | 17 +++++++++++++---- hw/sd/sdhci-pci.c | 1 + hw/sd/sdhci.c | 3 +++ 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 2e6e719df7b..c42aeab6848 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -30,6 +30,8 @@ #include "hw/sd/sd.h" #include "qom/object.h" +typedef struct SDHCIClass SDHCIClass; + /* * SD/MMC host controller state * @@ -41,13 +43,12 @@ * card to be protected). */ struct SDHCIState { - /*< private >*/ union { PCIDevice pcidev; SysBusDevice busdev; }; - /*< public >*/ + SDHCIClass *sc; SDBus sdbus; MemoryRegion iomem; AddressSpace sysbus_dma_as; @@ -110,6 +111,13 @@ struct SDHCIState { }; typedef struct SDHCIState SDHCIState; +struct SDHCIClass { + union { + PCIDeviceClass pci_parent_class; + SysBusDeviceClass sbd_parent_class; + }; +}; + /* * NOTE: This definition is taken out of Linux kernel and so the * original bit number is preserved @@ -126,10 +134,11 @@ enum { #define TYPE_PCI_SDHCI "sdhci-pci" DECLARE_INSTANCE_CHECKER(SDHCIState, PCI_SDHCI, TYPE_PCI_SDHCI) +DECLARE_CLASS_CHECKERS(SDHCIClass, PCI_SDHCI, + TYPE_PCI_SDHCI) #define TYPE_SYSBUS_SDHCI "generic-sdhci" -DECLARE_INSTANCE_CHECKER(SDHCIState, SYSBUS_SDHCI, - TYPE_SYSBUS_SDHCI) +OBJECT_DECLARE_TYPE(SDHCIState, SDHCIClass, SYSBUS_SDHCI) #define TYPE_IMX_USDHC "imx-usdhc" diff --git a/hw/sd/sdhci-pci.c b/hw/sd/sdhci-pci.c index 5268c0dee50..fe62582de90 100644 --- a/hw/sd/sdhci-pci.c +++ b/hw/sd/sdhci-pci.c @@ -73,6 +73,7 @@ static const TypeInfo sdhci_pci_types[] = { .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(SDHCIState), .class_init = sdhci_pci_class_init, + .class_size = sizeof(SDHCIClass), .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { }, diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index d1b1b187874..176bee6b8f5 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1419,6 +1419,8 @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) void sdhci_initfn(SDHCIState *s) { + s->sc = (SDHCIClass *)object_get_class(OBJECT(s)); /* Cache QOM parent */ + qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, @@ -1960,6 +1962,7 @@ static const TypeInfo sdhci_types[] = { .instance_size = sizeof(SDHCIState), .instance_init = sdhci_sysbus_init, .instance_finalize = sdhci_sysbus_finalize, + .class_size = sizeof(SDHCIClass), .class_init = sdhci_sysbus_class_init, }, { From patchwork Mon Mar 10 00:06:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 14009110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABB92C28B28 for ; Mon, 10 Mar 2025 00:10:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1trQfn-0002AY-F3; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43cf7b88494sm20159685e9.0.2025.03.09.17.06.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:07:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 07/14] hw/sd/sdhci: Make quirks a class property Date: Mon, 10 Mar 2025 01:06:13 +0100 Message-ID: <20250310000620.70120-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Allow to enforce implementations quirks by the class. All TYPE_IMX_USDHC instances use the quirk: move it to the class layer. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c | 12 +++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index c42aeab6848..ee1e7ef4b10 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -116,6 +116,8 @@ struct SDHCIClass { PCIDeviceClass pci_parent_class; SysBusDeviceClass sbd_parent_class; }; + + uint32_t quirks; }; /* diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 176bee6b8f5..570d825d130 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1427,6 +1427,7 @@ void sdhci_initfn(SDHCIState *s) sdhci_raise_insertion_irq, s); s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); + s->quirks = s->sc->quirks; s->io_ops = &sdhci_mmio_le_ops; } @@ -1888,7 +1889,15 @@ static void imx_usdhc_init(Object *obj) SDHCIState *s = SYSBUS_SDHCI(obj); s->io_ops = &usdhc_mmio_ops; - s->quirks = BIT(SDHCI_QUIRK_NO_BUSY_IRQ); +} + +static void imx_usdhc_class_init(ObjectClass *oc, void *data) +{ + SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc); + + sc->quirks = BIT(SDHCI_QUIRK_NO_BUSY_IRQ); + + sdhci_common_class_init(oc, data); } /* --- qdev Samsung s3c --- */ @@ -1969,6 +1978,7 @@ static const TypeInfo sdhci_types[] = { .name = TYPE_IMX_USDHC, .parent = TYPE_SYSBUS_SDHCI, .instance_init = imx_usdhc_init, + .class_init = imx_usdhc_class_init, }, { .name = TYPE_S3C_SDHCI, From patchwork Mon Mar 10 00:06:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 14009111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1F4EC28B28 for ; Mon, 10 Mar 2025 00:10:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1trQfn-0002Ax-PI; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ceaac390bsm60613665e9.35.2025.03.09.17.07.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:07:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 08/14] hw/sd/sdhci: Make I/O region size a class property Date: Mon, 10 Mar 2025 01:06:14 +0100 Message-ID: <20250310000620.70120-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Be ready to have SDHC implementations to cover a wider I/O address range. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan --- include/hw/sd/sdhci.h | 1 + hw/sd/sdhci.c | 10 ++++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index ee1e7ef4b10..dfa0c214036 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -118,6 +118,7 @@ struct SDHCIClass { }; uint32_t quirks; + uint64_t iomem_size; }; /* diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 570d825d130..3467385490d 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1444,6 +1444,8 @@ void sdhci_uninitfn(SDHCIState *s) void sdhci_common_realize(SDHCIState *s, Error **errp) { ERRP_GUARD(); + SDHCIClass *sc = s->sc; + const char *class_name = object_get_typename(OBJECT(s)); switch (s->endianness) { case DEVICE_LITTLE_ENDIAN: @@ -1469,8 +1471,9 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) s->buf_maxsz = sdhci_get_fifolen(s); s->fifo_buffer = g_malloc0(s->buf_maxsz); - memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", - SDHC_REGISTERS_MAP_SIZE); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfb799fsm13080658f8f.2.2025.03.09.17.07.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:07:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 09/14] hw/sd/sdhci: Allow SDHCI classes to register their own MemoryRegionOps Date: Mon, 10 Mar 2025 01:06:15 +0100 Message-ID: <20250310000620.70120-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add MemoryRegionOps as a class property. For now it is only used by TYPE_IMX_USDHC. Otherwise the default remains in little endian. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 1 + hw/sd/sdhci.c | 22 ++++++++-------------- 2 files changed, 9 insertions(+), 14 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index dfa0c214036..108bc1993c6 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -117,6 +117,7 @@ struct SDHCIClass { SysBusDeviceClass sbd_parent_class; }; + const MemoryRegionOps *io_ops; uint32_t quirks; uint64_t iomem_size; }; diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 3467385490d..6868bf68285 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1428,8 +1428,6 @@ void sdhci_initfn(SDHCIState *s) s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); s->quirks = s->sc->quirks; - - s->io_ops = &sdhci_mmio_le_ops; } void sdhci_uninitfn(SDHCIState *s) @@ -1447,6 +1445,7 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) SDHCIClass *sc = s->sc; const char *class_name = object_get_typename(OBJECT(s)); + s->io_ops = sc->io_ops ?: &sdhci_mmio_le_ops; switch (s->endianness) { case DEVICE_LITTLE_ENDIAN: /* s->io_ops is little endian by default */ @@ -1890,17 +1889,11 @@ static const MemoryRegionOps usdhc_mmio_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static void imx_usdhc_init(Object *obj) -{ - SDHCIState *s = SYSBUS_SDHCI(obj); - - s->io_ops = &usdhc_mmio_ops; -} - static void imx_usdhc_class_init(ObjectClass *oc, void *data) { SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc); + sc->io_ops = &usdhc_mmio_ops; sc->quirks = BIT(SDHCI_QUIRK_NO_BUSY_IRQ); sdhci_common_class_init(oc, data); @@ -1957,11 +1950,13 @@ static const MemoryRegionOps sdhci_s3c_mmio_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static void sdhci_s3c_init(Object *obj) +static void sdhci_s3c_class_init(ObjectClass *oc, void *data) { - SDHCIState *s = SYSBUS_SDHCI(obj); + SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc); - s->io_ops = &sdhci_s3c_mmio_ops; + sc->io_ops = &sdhci_s3c_mmio_ops; + + sdhci_common_class_init(oc, data); } static const TypeInfo sdhci_types[] = { @@ -1983,13 +1978,12 @@ static const TypeInfo sdhci_types[] = { { .name = TYPE_IMX_USDHC, .parent = TYPE_SYSBUS_SDHCI, - .instance_init = imx_usdhc_init, .class_init = imx_usdhc_class_init, }, { .name = TYPE_S3C_SDHCI, .parent = TYPE_SYSBUS_SDHCI, - .instance_init = sdhci_s3c_init, + .class_init = sdhci_s3c_class_init, }, }; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfb7aefsm13011423f8f.20.2025.03.09.17.07.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:07:15 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 10/14] hw/sd/sdhci: Allow SDHCI classes to register their own read-only regs Date: Mon, 10 Mar 2025 01:06:16 +0100 Message-ID: <20250310000620.70120-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Some registers are read-only. Since we allow instances to clear/set extra bits of capareg, log when read-only bits normally set by hardware are cleared at board level. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 7 +++++++ hw/sd/sdhci.c | 10 +++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 108bc1993c6..eb21b64f932 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -120,6 +120,13 @@ struct SDHCIClass { const MemoryRegionOps *io_ops; uint32_t quirks; uint64_t iomem_size; + + /* Read-only registers */ + struct { + uint64_t capareg; + uint64_t maxcurr; + uint16_t version; + } ro; }; /* diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 6868bf68285..eb6a0e0f939 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -73,6 +73,7 @@ static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, static void sdhci_check_capareg(SDHCIState *s, Error **errp) { + SDHCIClass *sc = s->sc; uint64_t msk = s->capareg; uint32_t val; bool y; @@ -208,6 +209,11 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp) qemu_log_mask(LOG_UNIMP, "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c0e222dsm13208215f8f.72.2025.03.09.17.07.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:07:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 11/14] hw/sd/sdhci: Allow SDHCI classes to have different register reset values Date: Mon, 10 Mar 2025 01:06:17 +0100 Message-ID: <20250310000620.70120-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For the registers which are not zeroed at reset, allow the different implementations to set particular reset values. Remove the misleading values commented in sdhci-internal.h. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan --- hw/sd/sdhci-internal.h | 24 ++++++++++++------------ include/hw/sd/sdhci.h | 20 ++++++++++++++++++++ hw/sd/sdhci.c | 14 ++++++++++++++ 3 files changed, 46 insertions(+), 12 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 9072b06bdde..d99a8493db2 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -70,7 +70,7 @@ /* R/W Buffer Data Register 0x0 */ #define SDHC_BDATA 0x20 -/* R/ROC Present State Register 0x000A0000 */ +/* R/ROC Present State Register */ #define SDHC_PRNSTS 0x24 #define SDHC_CMD_INHIBIT 0x00000001 #define SDHC_DATA_INHIBIT 0x00000002 @@ -88,7 +88,7 @@ FIELD(SDHC_PRNSTS, CMD_LVL, 24, 1); #define TRANSFERRING_DATA(x) \ ((x) & (SDHC_DOING_READ | SDHC_DOING_WRITE)) -/* R/W Host control Register 0x0 */ +/* R/W Host control Register */ #define SDHC_HOSTCTL 0x28 #define SDHC_CTRL_LED 0x01 #define SDHC_CTRL_DATATRANSFERWIDTH 0x02 /* SD mode only */ @@ -104,17 +104,17 @@ FIELD(SDHC_PRNSTS, CMD_LVL, 24, 1); #define SDHC_CTRL_CDTEST_INS 0x40 #define SDHC_CTRL_CDTEST_EN 0x80 -/* R/W Power Control Register 0x0 */ +/* R/W Power Control Register */ #define SDHC_PWRCON 0x29 #define SDHC_POWER_ON (1 << 0) FIELD(SDHC_PWRCON, BUS_VOLTAGE, 1, 3); -/* R/W Block Gap Control Register 0x0 */ +/* R/W Block Gap Control Register */ #define SDHC_BLKGAP 0x2A #define SDHC_STOP_AT_GAP_REQ 0x01 #define SDHC_CONTINUE_REQ 0x02 -/* R/W WakeUp Control Register 0x0 */ +/* R/W WakeUp Control Register */ #define SDHC_WAKCON 0x2B #define SDHC_WKUP_ON_INS (1 << 1) #define SDHC_WKUP_ON_RMV (1 << 2) @@ -128,17 +128,17 @@ FIELD(SDHC_PWRCON, BUS_VOLTAGE, 1, 3); #define SDHC_CLOCK_IS_ON(x) \ (((x) & SDHC_CLOCK_CHK_MASK) == SDHC_CLOCK_CHK_MASK) -/* R/W Timeout Control Register 0x0 */ +/* R/W Timeout Control Register */ #define SDHC_TIMEOUTCON 0x2E FIELD(SDHC_TIMEOUTCON, COUNTER, 0, 4); -/* R/W Software Reset Register 0x0 */ +/* R/W Software Reset Register */ #define SDHC_SWRST 0x2F #define SDHC_RESET_ALL 0x01 #define SDHC_RESET_CMD 0x02 #define SDHC_RESET_DATA 0x04 -/* ROC/RW1C Normal Interrupt Status Register 0x0 */ +/* ROC/RW1C Normal Interrupt Status Register */ #define SDHC_NORINTSTS 0x30 #define SDHC_NIS_ERR 0x8000 #define SDHC_NIS_CMDCMP 0x0001 @@ -151,7 +151,7 @@ FIELD(SDHC_TIMEOUTCON, COUNTER, 0, 4); #define SDHC_NIS_REMOVE 0x0080 #define SDHC_NIS_CARDINT 0x0100 -/* ROC/RW1C Error Interrupt Status Register 0x0 */ +/* ROC/RW1C Error Interrupt Status Register */ #define SDHC_ERRINTSTS 0x32 #define SDHC_EIS_CMDTIMEOUT 0x0001 #define SDHC_EIS_BLKGAP 0x0004 @@ -159,7 +159,7 @@ FIELD(SDHC_TIMEOUTCON, COUNTER, 0, 4); #define SDHC_EIS_CMD12ERR 0x0100 #define SDHC_EIS_ADMAERR 0x0200 -/* R/W Normal Interrupt Status Enable Register 0x0 */ +/* R/W Normal Interrupt Status Enable Register */ #define SDHC_NORINTSTSEN 0x34 #define SDHC_NISEN_CMDCMP 0x0001 #define SDHC_NISEN_TRSCMP 0x0002 @@ -170,7 +170,7 @@ FIELD(SDHC_TIMEOUTCON, COUNTER, 0, 4); #define SDHC_NISEN_REMOVE 0x0080 #define SDHC_NISEN_CARDINT 0x0100 -/* R/W Error Interrupt Status Enable Register 0x0 */ +/* R/W Error Interrupt Status Enable Register */ #define SDHC_ERRINTSTSEN 0x36 #define SDHC_EISEN_CMDTIMEOUT 0x0001 #define SDHC_EISEN_BLKGAP 0x0004 @@ -205,7 +205,7 @@ FIELD(SDHC_HOSTCTL2, VERSION4, 12, 1); /* since v4 */ FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1); FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1); -/* HWInit Capabilities Register 0x05E80080 */ +/* HWInit Capabilities Register */ #define SDHC_CAPAB 0x40 FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6); FIELD(SDHC_CAPAB, TOUNIT, 7, 1); diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index eb21b64f932..b21adcab670 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -121,6 +121,26 @@ struct SDHCIClass { uint32_t quirks; uint64_t iomem_size; + /* Default reset values */ + struct { + uint32_t sdmasysad; + + uint16_t blksize; + uint16_t blkcnt; + + uint32_t prnsts; + + uint8_t hostctl1; + uint8_t pwrcon; + uint8_t blkgap; + uint8_t wakcon; + + uint16_t clkcon; + uint8_t timeoutcon; + + uint16_t norintstsen; + uint16_t errintstsen; + } reset; /* Read-only registers */ struct { uint64_t capareg; diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index eb6a0e0f939..f731b1a141a 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -295,6 +295,7 @@ static void sdhci_set_readonly(DeviceState *dev, bool level) static void sdhci_reset(SDHCIState *s) { DeviceState *dev = DEVICE(s); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c103f57sm13217968f8f.91.2025.03.09.17.07.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:07:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 12/14] hw/sd/sdhci: Implement Freescale eSDHC as TYPE_FSL_ESDHC Date: Mon, 10 Mar 2025 01:06:18 +0100 Message-ID: <20250310000620.70120-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Per the MPC8569E reference manual, its SDHC I/O range is 4KiB wide, mapped in big endian order, and it only accepts 32-bit aligned access. Set the default register reset values. Reported-by: BALATON Zoltan Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c | 44 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index b21adcab670..e8fced5eedc 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -171,6 +171,8 @@ DECLARE_CLASS_CHECKERS(SDHCIClass, PCI_SDHCI, #define TYPE_SYSBUS_SDHCI "generic-sdhci" OBJECT_DECLARE_TYPE(SDHCIState, SDHCIClass, SYSBUS_SDHCI) +#define TYPE_FSL_ESDHC "fsl-esdhc" + #define TYPE_IMX_USDHC "imx-usdhc" #define TYPE_S3C_SDHCI "s3c-sdhci" diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index f731b1a141a..47e4bd1a610 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1667,7 +1667,44 @@ static void sdhci_bus_class_init(ObjectClass *klass, void *data) sbc->set_readonly = sdhci_set_readonly; } -/* --- qdev i.MX eSDHC --- */ +/* --- Freescale eSDHC (MPC8569ERM Rev.2 from 06/2011) --- */ + +static const MemoryRegionOps fsl_esdhc_mmio_ops = { + .read = sdhci_read, + .write = sdhci_write, + .valid = { + /* + * Per the reference manual (chapter 16): + * + * All eSDHC registers must be accessed as aligned 4-byte quantities. + * Accesses to the eSDHC registers that are less than 4-bytes are not + * supported. + */ + .min_access_size = 4, + .unaligned = false + }, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void fsl_esdhc_class_init(ObjectClass *oc, void *data) +{ + SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc); + + sc->iomem_size = 0x1000; + sc->io_ops = &fsl_esdhc_mmio_ops; + sc->ro.capareg = 0x01e30000; + sc->reset.sdmasysad = 8; + sc->reset.blkcnt = 8; + sc->reset.prnsts = 0xff800000; + sc->reset.hostctl1 = 0x20; /* Endian mode (address-invariant) */ + sc->reset.clkcon = 0x8000; + sc->reset.norintstsen = 0x013f; + sc->reset.errintstsen = 0x117f; + + sdhci_common_class_init(oc, data); +} + +/* --- qdev i.MX uSDHC --- */ #define USDHC_MIX_CTRL 0x48 @@ -1997,6 +2034,11 @@ static const TypeInfo sdhci_types[] = { .class_size = sizeof(SDHCIClass), .class_init = sdhci_sysbus_class_init, }, + { + .name = TYPE_FSL_ESDHC, + .parent = TYPE_SYSBUS_SDHCI, + .class_init = fsl_esdhc_class_init, + }, { .name = TYPE_IMX_USDHC, .parent = TYPE_SYSBUS_SDHCI, From patchwork Mon Mar 10 00:06:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 14009124 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF65BC28B2E for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c0e222dsm13208524f8f.72.2025.03.09.17.07.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:07:30 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 13/14] hw/ppc/e500: Replace generic SDHCI by Freescale eSDHC Date: Mon, 10 Mar 2025 01:06:19 +0100 Message-ID: <20250310000620.70120-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Zoltan reported some U-Boot versions seem to want registers to be initialized correctly before expecting interrupts. Now than we have a proper Freescale eSDHC implementation, use it. Reported-by: BALATON Zoltan Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bernhard Beschow --- hw/ppc/e500.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index fe8b9f79621..2de7d94df9c 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -49,7 +49,6 @@ #include "hw/i2c/i2c.h" #include "hw/irq.h" #include "hw/sd/sdhci.h" -#include "hw/misc/unimp.h" #define EPAPR_MAGIC (0x45504150) #define DTC_LOAD_PAD 0x1800000 @@ -1027,22 +1026,13 @@ void ppce500_init(MachineState *machine) /* eSDHC */ if (pmc->has_esdhc) { - dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); - qdev_prop_set_string(dev, "name", "esdhc"); - qdev_prop_set_uint64(dev, "size", MPC85XX_ESDHC_REGS_SIZE); - s = SYS_BUS_DEVICE(dev); - sysbus_realize_and_unref(s, &error_fatal); - memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET, - sysbus_mmio_get_region(s, 0)); - /* * Compatible with: * - SD Host Controller Specification Version 2.0 Part A2 * (See MPC8569E Reference Manual) */ - dev = qdev_new(TYPE_SYSBUS_SDHCI); + dev = qdev_new(TYPE_FSL_ESDHC); qdev_prop_set_uint8(dev, "sd-spec-version", 2); - qdev_prop_set_uint8(dev, "endianness", DEVICE_BIG_ENDIAN); s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ)); From patchwork Mon Mar 10 00:06:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 14009126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DCC5C28B2F for ; Mon, 10 Mar 2025 00:12:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1trQi7-0004sV-7z; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfcfbsm12872089f8f.28.2025.03.09.17.07.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:07:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 14/14] hw/sd/sdhci: Remove unnecessary 'endianness' property Date: Mon, 10 Mar 2025 01:06:20 +0100 Message-ID: <20250310000620.70120-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The previous commit removed the single use of instance setting the "endianness" property. Since classes can register their io_ops with correct endianness, no need to support different ones. Remove the code related to SDHCIState::endianess field. Remove the now unused SDHCIState::io_ops field, since we directly use the class one. Suggested-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci-internal.h | 1 - include/hw/sd/sdhci.h | 2 -- hw/sd/sdhci.c | 33 +++------------------------------ 3 files changed, 3 insertions(+), 33 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index d99a8493db2..e4da6c831d1 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -308,7 +308,6 @@ extern const VMStateDescription sdhci_vmstate; #define SDHC_CAPAB_REG_DEFAULT 0x057834b4 #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ - DEFINE_PROP_UINT8("endianness", _state, endianness, DEVICE_LITTLE_ENDIAN), \ DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \ \ diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index e8fced5eedc..1016a5b5b77 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -54,7 +54,6 @@ struct SDHCIState { AddressSpace sysbus_dma_as; AddressSpace *dma_as; MemoryRegion *dma_mr; - const MemoryRegionOps *io_ops; QEMUTimer *insert_timer; /* timer for 'changing' sd card. */ QEMUTimer *transfer_timer; @@ -105,7 +104,6 @@ struct SDHCIState { /* Configurable properties */ uint32_t quirks; - uint8_t endianness; uint8_t sd_spec_version; uint8_t uhs_mode; }; diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 47e4bd1a610..cbb9f4ae8c0 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1391,17 +1391,6 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) } static const MemoryRegionOps sdhci_mmio_le_ops = { - .read = sdhci_read, - .write = sdhci_write, - .valid = { - .min_access_size = 1, - .max_access_size = 4, - .unaligned = false - }, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -static const MemoryRegionOps sdhci_mmio_be_ops = { .read = sdhci_read, .write = sdhci_write, .impl = { @@ -1413,7 +1402,7 @@ static const MemoryRegionOps sdhci_mmio_be_ops = { .max_access_size = 4, .unaligned = false }, - .endianness = DEVICE_BIG_ENDIAN, + .endianness = DEVICE_LITTLE_ENDIAN, }; static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) @@ -1467,23 +1456,6 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) SDHCIClass *sc = s->sc; const char *class_name = object_get_typename(OBJECT(s)); - s->io_ops = sc->io_ops ?: &sdhci_mmio_le_ops; - switch (s->endianness) { - case DEVICE_LITTLE_ENDIAN: - /* s->io_ops is little endian by default */ - break; - case DEVICE_BIG_ENDIAN: - if (s->io_ops != &sdhci_mmio_le_ops) { - error_setg(errp, "SD controller doesn't support big endianness"); - return; - } - s->io_ops = &sdhci_mmio_be_ops; - break; - default: - error_setg(errp, "Incorrect endianness"); - return; - } - sdhci_init_readonly_registers(s, errp); if (*errp) { return; @@ -1493,7 +1465,7 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) s->fifo_buffer = g_malloc0(s->buf_maxsz); assert(sc->iomem_size >= SDHC_REGISTERS_MAP_SIZE); - memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, class_name, + memory_region_init_io(&s->iomem, OBJECT(s), sc->io_ops, s, class_name, sc->iomem_size); } @@ -1578,6 +1550,7 @@ void sdhci_common_class_init(ObjectClass *klass, const void *data) dc->vmsd = &sdhci_vmstate; device_class_set_legacy_reset(dc, sdhci_poweron_reset); + sc->io_ops = &sdhci_mmio_le_ops; sc->iomem_size = SDHC_REGISTERS_MAP_SIZE; }