From patchwork Mon Mar 10 12:09:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 14009728 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3680822156F; Mon, 10 Mar 2025 12:09:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741608587; cv=none; b=j+lCNQWXlirH9ZrmXWeCJLUIrQpIG+v99CcgohwOVEMwf1BTk4CrjZYei8hYR5ArBwtOxfrweiAOZo+jCurx30WxXeHsh9rkMtN/1gTBFAm3mL68x3vs84UxMY4wpOF3IuNyi+TL85XUL4MkEWPrHJQZVyf60575BEaxiGMD69M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741608587; c=relaxed/simple; bh=RATihl00ifnEEub10r70xUN32uo8hJFRPkXzX848030=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pqYfkc16B4trOCh4eqTXWCbv4l206KZasGXJHZhr95iGS5tt7LsS2oijjL/sSzfIcd3TIqjLNm5TqKojn3C80a7xZu/9J661Fn7gOlSh+Zw/10Paf/v9ZjMOWW6qWpML8aSLrk1z5cNRkAFnO6pss0XgiVmeyhZYCzwmdtACuDI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Ps4eWNJi; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Ps4eWNJi" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52A8m2Lu027354; Mon, 10 Mar 2025 12:09:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= adN+4ikcEN3NAUucAWLR4IlKG1TfU+4qY+hNlC2pQdc=; b=Ps4eWNJiUZGalMzc W//N8eNrpQCMe3+Rdjg7/g+4l4Z8GtJ7WjT5SkSGW8Q2iz6RjlvGxJ1qcZiCC6wP KqhQcArqxTFjoldQUhW7Zsx1o6tIRRyLEm7hQmD1Z2Mb50f8D4XmWsuPhzTvOiiD nc9wWohMjc4OaRTFMKCxs13yAeBDhTUF406pX4YS1ueAGmrU5MIz0DOki5FQHFbl w9Hp+fyqVjsOXHlCEUq7jh07ZNJfojb1FtnZcj5bKHyScZQo66P191lEqz+X10i2 SbIqodXq6+Yl3LiGdWo/TavNYDeqZJqQH8A2OHX4VhTUw4SMB4T4O+jVXr3xPmA5 V5/qow== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 458f6actcw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Mar 2025 12:09:27 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52AC9RI4011451 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Mar 2025 12:09:27 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 10 Mar 2025 05:09:24 -0700 From: Md Sadre Alam To: , , , , , , , , , Subject: [PATCH v3 1/4] mtd: rawnand: qcom: Pass 18 bit offset from QPIC base address to BAM Date: Mon, 10 Mar 2025 17:39:03 +0530 Message-ID: <20250310120906.1577292-2-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250310120906.1577292-1-quic_mdalam@quicinc.com> References: <20250310120906.1577292-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=WsDRMcfv c=1 sm=1 tr=0 ts=67ced678 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=ftwAy63A9X0dtpR3FuYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: pBTgiuc2HvEDG6vqffZlw-CwldyI3vfk X-Proofpoint-ORIG-GUID: pBTgiuc2HvEDG6vqffZlw-CwldyI3vfk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-10_05,2025-03-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 clxscore=1011 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503100096 Currently we are configuring lower 24 bits of address in descriptor whereas QPIC design expects 18 bit register offset from QPIC base address to be configured in cmd descriptors. This is leading to a different address actually being used in HW, leading to wrong value read. the actual issue is that the NANDc base address is different from the QPIC base address. But the driver doesn't take it into account and just used the QPIC base as the NANDc base. This used to work as the NANDc IP only considers the lower 18 bits of the address passed by the driver to derive the register offset. Since the base address of QPIC used to contain all 0 for lower 18 bits (like 0x07980000), the driver ended up passing the actual register offset in it and NANDc worked properly. But on newer SoCs like SDX75, the QPIC base address doesn't contain all 0 for lower 18 bits (like 0x01C98000). So NANDc sees wrong offset as per the current logic The address should be passed to BAM 0x30000 + offset. In older targets the lower 18-bits are zero so that correct address being paased. But in newer targets the lower 18-bits are non-zero in QPIC base so that 0x300000 + offset giving the wrong value. SDX75 : QPIC_QPIC | 0x01C98000 (Lower 18 bits are non zero) SDX55 : QPIC_QPIC | 0x1B00000 (Lower 18 bits are zero) Same for older targets. Cc: stable@vger.kernel.org Fixes: 8d6b6d7e135e ("mtd: nand: qcom: support for command descriptor formation") Tested-by: Lakshmi Sowjanya D Signed-off-by: Md Sadre Alam --- Change in [v3] * Updated commit message * Removed dev_cmd_reg_start = 0 , which was wrongely got added Change in [v2] * Updated commit message * Added Fixes tag * Added stable kernel tag * Renamed the variable from offset_from_qpic to nandc_offset Change in [v1] * Preliminary correction for the register address forwarded to BAM drivers/mtd/nand/raw/qcom_nandc.c | 4 ++++ include/linux/mtd/nand-qpic-common.h | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 5eaa0be367cd..5443cb918e0b 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2360,6 +2360,7 @@ static const struct qcom_nandc_props ipq806x_nandc_props = { .supports_bam = false, .use_codeword_fixup = true, .dev_cmd_reg_start = 0x0, + .nandc_offset = 0x30000, }; static const struct qcom_nandc_props ipq4019_nandc_props = { @@ -2367,6 +2368,7 @@ static const struct qcom_nandc_props ipq4019_nandc_props = { .supports_bam = true, .nandc_part_of_qpic = true, .dev_cmd_reg_start = 0x0, + .nandc_offset = 0x30000, }; static const struct qcom_nandc_props ipq8074_nandc_props = { @@ -2374,6 +2376,7 @@ static const struct qcom_nandc_props ipq8074_nandc_props = { .supports_bam = true, .nandc_part_of_qpic = true, .dev_cmd_reg_start = 0x7000, + .nandc_offset = 0x30000, }; static const struct qcom_nandc_props sdx55_nandc_props = { @@ -2382,6 +2385,7 @@ static const struct qcom_nandc_props sdx55_nandc_props = { .nandc_part_of_qpic = true, .qpic_version2 = true, .dev_cmd_reg_start = 0x7000, + .nandc_offset = 0x30000, }; /* diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h index cd7172e6c1bb..6268f08b9d19 100644 --- a/include/linux/mtd/nand-qpic-common.h +++ b/include/linux/mtd/nand-qpic-common.h @@ -200,7 +200,7 @@ #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg)) /* Returns the NAND register physical address */ -#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset)) +#define nandc_reg_phys(chip, offset) ((nandc)->props->nandc_offset + (offset)) /* Returns the dma address for reg read buffer */ #define reg_buf_dma_addr(chip, vaddr) \ @@ -458,6 +458,7 @@ struct qcom_nandc_props { bool nandc_part_of_qpic; bool qpic_version2; bool use_codeword_fixup; + u32 nandc_offset; }; void qcom_free_bam_transaction(struct qcom_nand_controller *nandc); From patchwork Mon Mar 10 12:09:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 14009730 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 103722288C6; Mon, 10 Mar 2025 12:09:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741608591; cv=none; b=IIgW36gE5NlxA3wZFSlqnZxAcsReAEBCVoILwUSfPMLCqe46KGGcfNX7s/H+b5qvHCkuniLiS5nRCGE0mSlhMG0lwNWJ3XNuWyXIdw7slXjsD5xwFAZAo2+x2sfO/gMSU8vedRRUu1UopKaVcog2P2xHRau5DJ976vz72alPi/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741608591; c=relaxed/simple; bh=DnoxLs98rYn6XS5mphroQWIxuUXuPaPIETdv9VuFOwk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Px3Vfb7U0YXJnxRt0tdRg6ThK/sskI1EZfrxnHgB3wFkYgVjRdpxWN0vJCCsO9xSiMKNsk7Jvju9QFLPkZthbo7tNpkZPnoMEioDHmvfKdxB9SvpJpNDXiGRGZrIIVaqrzrszijelCqWf0c8y32vr+xNhV+GP48UguRK8IVXSPc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=h/hvpUuu; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="h/hvpUuu" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52A9Sdxk026525; Mon, 10 Mar 2025 12:09:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= oYAMJFCg4hwlJpbMOOHK0AoshW36RVn+FdFKzN7jQ6o=; b=h/hvpUuuPjDO+6Eh 8r22x797Jg6r4nx5MetYHE5Di6JGb+2c1iXYGUwIi8r7+QtshYXeVdR7mBilD+da WW/geQcPZV3pSTJY/ijiPQTL962ssTfeep0EDc4T7sA745KCTIvKR0nAvkxUsVew rjCUmbT8S7EMHnUqC+cZVwt0Cb+Kq+gYBp9g2LLfozzRVVOTVcQIYAw8UJRcjUtu oCYJ1qQWyXCOvTxFdBCvW4XowccIKJ0ou5PV7yaVDPS5KAXyH1MezbtL1K8AlqRi 8AwrFLPsVB+DQMKJPdCaO3yqcvCth+ZDdIxPQeMTRDh9F4Lv3UqJagcIS0UfSdh9 /x+MZQ== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 458f2mcqx0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Mar 2025 12:09:31 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52AC9UKR011513 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Mar 2025 12:09:30 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 10 Mar 2025 05:09:27 -0700 From: Md Sadre Alam To: , , , , , , , , , Subject: [PATCH v3 2/4] mtd: rawnand: qcom: Fix last codeword read in qcom_param_page_type_exec() Date: Mon, 10 Mar 2025 17:39:04 +0530 Message-ID: <20250310120906.1577292-3-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250310120906.1577292-1-quic_mdalam@quicinc.com> References: <20250310120906.1577292-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HmnFvksTTJhI9dgh9tfCocZkKhZSh6a3 X-Proofpoint-ORIG-GUID: HmnFvksTTJhI9dgh9tfCocZkKhZSh6a3 X-Authority-Analysis: v=2.4 cv=ab+bnQot c=1 sm=1 tr=0 ts=67ced67b cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=OhSYzIeDMC8V1oLpjEAA:9 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-10_05,2025-03-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 bulkscore=0 mlxscore=0 impostorscore=0 phishscore=0 clxscore=1011 spamscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503100096 For QPIC V2 onwards there is a separate register to read last code word "QPIC_NAND_READ_LOCATION_LAST_CW_n". qcom_param_page_type_exec() is used to read only one code word If it configures the number of code words to 1 in QPIC_NAND_DEV0_CFG0 register then QPIC controller thinks its reading the last code word, since we are having separate register to read the last code word, we have to configure "QPIC_NAND_READ_LOCATION_LAST_CW_n" register to fetch data from QPIC buffer to system memory. Without this change page read was failing with timeout error / # hexdump -C /dev/mtd1 [ 129.206113] qcom-nandc 1cc8000.nand-controller: failure to read page/oob hexdump: /dev/mtd1: Connection timed out This issue only seen on SDX targets since SDX target used QPICv2. But same working on IPQ targets since IPQ used QPICv1. Cc: stable@vger.kernel.org Fixes: 89550beb098e ("mtd: rawnand: qcom: Implement exec_op()") Reviewed-by: Manivannan Sadhasivam Tested-by: Lakshmi Sowjanya D Signed-off-by: Md Sadre Alam --- Change in [v3] * Updated commit header and message * Added condition check for location register and location_last register based on qpic_version2 * Added Reviewed-by tag Change in [v2] * Updated commit message * Added stable kernel tag * Replaced the buf_count value of 512 with the len in bytes. Change in [v1] * Resolved the issue with reading a single code word in the parameter page read drivers/mtd/nand/raw/qcom_nandc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 5443cb918e0b..d41c0e3926ed 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -1863,7 +1863,12 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_ const struct nand_op_instr *instr = NULL; unsigned int op_id = 0; unsigned int len = 0; - int ret; + int ret, reg_base; + + reg_base = NAND_READ_LOCATION_0; + + if (nandc->props->qpic_version2) + reg_base = NAND_READ_LOCATION_LAST_CW_0; ret = qcom_parse_instructions(chip, subop, &q_op); if (ret) @@ -1915,7 +1920,10 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_ op_id = q_op.data_instr_idx; len = nand_subop_get_data_len(subop, op_id); - nandc_set_read_loc(chip, 0, 0, 0, len, 1); + if (nandc->props->qpic_version2) + nandc_set_read_loc_last(chip, reg_base, 0, len, 1); + else + nandc_set_read_loc_first(chip, reg_base, 0, len, 1); if (!nandc->props->qpic_version2) { qcom_write_reg_dma(nandc, &nandc->regs->vld, NAND_DEV_CMD_VLD, 1, 0); From patchwork Mon Mar 10 12:09:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 14009727 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79AAF223702; Mon, 10 Mar 2025 12:09:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741608587; cv=none; b=jgcpHOO12RvYXOHGTuZAi6tj+NCy37zQBaGF9rs5u1LIv9ijGKEdRzZ6To5BPgTO3cI3vmKtOreyaXPmQrdsebIqCryhDhGORjDic8OJ0dd8RiVur2PT/h7j5ExX5m/fzVQTOgw/s7odpiBSVUuiWZkv3SOjG/gZgiXCblp0oJ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741608587; c=relaxed/simple; bh=rHlkaBYdRyPjxyVjdB/MboqdmaMbmEzLC1229m4Ce24=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ty+L/Jz/1zAo+oYIGQPDcIdXkL6lPcSd1jx2F9gvUawEDxeUVeBW77nwMK1irpneIysuTUf2BsdaQKNJUI+IrPlqGUXU5XbCaglcweZF9vA4TfyQFZ6m0ClDcqHRqQrz3EEYcCnu6IAgJWYIEMiBedmR9x9V7ST6tLy6Vye+57g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=NIDzwFN/; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="NIDzwFN/" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52A8m2Lv027354; Mon, 10 Mar 2025 12:09:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= AQsRj/kwofHWJ1I76e2nIYWsi5tjCpN7F23mCnzpC+o=; b=NIDzwFN/Fq7qkp0X XTiJ2NffxqAj0HNykef7OEkNRSpV+2TTQgftX2PPRijU0GsOl4dDvFyA1GYv/vsN VUMiVtKGGITXyTAoiploEgn8QP43TE7t2PAZc2dH5qOng4a11/eC92vZ9I8NuQ34 oF3ZozaZJwx0OdAars37uMFG5fXEDiOXhtrmc41aX8qnj2EsSOCdLmHsw7kDI+DN dZlT87NWDKk+EC6xHVGuQoJhIi/19mf7dfFIT4myBbVQ/cTLN9x17fFrSZQmnOl2 CcctT5bM1cIUEr4lFb4xLzHJTxsjKK7dcIFHc73MG5qOppDy5VsBOWmrBZTnWnM8 9swylQ== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 458f6actd5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Mar 2025 12:09:34 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52AC9X9F024847 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Mar 2025 12:09:33 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 10 Mar 2025 05:09:30 -0700 From: Md Sadre Alam To: , , , , , , , , , Subject: [PATCH v3 3/4] mtd: rawnand: qcom: Fix read len for onfi param page Date: Mon, 10 Mar 2025 17:39:05 +0530 Message-ID: <20250310120906.1577292-4-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250310120906.1577292-1-quic_mdalam@quicinc.com> References: <20250310120906.1577292-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=WsDRMcfv c=1 sm=1 tr=0 ts=67ced67e cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=09C-ZdBHwT7nDx1AlKIA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: 2V41MEVTYQtpzWjR6JkvwGBKFk28rHiG X-Proofpoint-ORIG-GUID: 2V41MEVTYQtpzWjR6JkvwGBKFk28rHiG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-10_05,2025-03-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 clxscore=1015 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503100096 The minimum size to fetch the data from device to QPIC buffer is 512-bytes. If size is less than 512-bytes the data will not be protected by ECC as per QPIC standard. So while reading onfi parameter page from NAND device set nandc->buf_count = 512. Cc: stable@vger.kernel.org Fixes: 89550beb098e ("mtd: rawnand: qcom: Implement exec_op()") Tested-by: Lakshmi Sowjanya D Signed-off-by: Md Sadre Alam --- Change in [v3] * No change Change in [v2] * Set buf_count to 512 in the parameter page read Change in [v1] drivers/mtd/nand/raw/qcom_nandc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index d41c0e3926ed..c3fdafb7e9eb 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -1930,7 +1930,7 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_ qcom_write_reg_dma(nandc, &nandc->regs->cmd1, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); } - nandc->buf_count = len; + nandc->buf_count = 512; memset(nandc->data_buffer, 0xff, nandc->buf_count); config_nand_single_cw_page_read(chip, false, 0); From patchwork Mon Mar 10 12:09:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 14009729 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A04F2288C3; Mon, 10 Mar 2025 12:09:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741608590; cv=none; b=DX/lRC3zPXWftuLKThOIkymWfniyv6EKSY81DVILM7nyj5vGmPcKUyT1YyTN3tRLjXdN25wTcpPo/IFGQHjwvRrpGrEVQwMTT0WRBDHcMLz8nHqjnASuyBIp+bB72TpRxtZcL4Av5h5Ek7Ppbvtbh2pXKTPMfoZjhYTzX5L8SYE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741608590; c=relaxed/simple; bh=t8D1h9fbsRnyGfaal8jkAqYXA1Fl7fy7WW3NrrAgy5c=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gRRk2gu9Cnazi5N4ExoglinDpLX12S+Kc5AdwEYaR8wZsKl1+z308xNfRS5UX6Rixa6+xEDnIoTwpiPZUK8+5PAyrd0RpdBQmoMDrAfZYm3j0dJVAj+CeU+x8QE39Kf1zxGYIa4E29gjEQCj+HFWfoqEuzH9zd+/V+MwAMyx5QI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Qi0f11ia; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Qi0f11ia" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52A9ujwq024744; Mon, 10 Mar 2025 12:09:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= zrTnM0Fve5fUTlJHvpQwbTFY+eg/oU2A5W1AzhdIjpw=; b=Qi0f11iaA0UGtZkN 6N/bz2oZGnbvjvIYEm670iXYSM22zjRNUT6EcdY7xBaVVM9/8f6yIpUNcE3zR3sL jULrzsPeN51ELMrCrK4sMb6t2jNQ8+q3BV9wor7YYz/DhaFx50jkUiPcWx9A8y8F qPKwtFdS21s+jcElByTVmIlcxkd3bq/BED1W2gqsFn2UEi+TYGhuJ0+8zLS34CtT tyBRnLQFgDVYX+NyKRykSDHe3NjpHjrXQIftEOXZVu0U0XwQ8zAciy47XrdQcY7I iybkv5L5QZlKBfEgMOI+464TpZJu8sdbp5Gsw/fb9Wj1IgtT9yVrozQHwRuYcd4u Ie88Tg== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 458f2mcqxf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Mar 2025 12:09:37 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52AC9b0B024931 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Mar 2025 12:09:37 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 10 Mar 2025 05:09:34 -0700 From: Md Sadre Alam To: , , , , , , , , , Subject: [PATCH v3 4/4] spi: spi-qpic-snand: set nandc_offset for ipq9574 Date: Mon, 10 Mar 2025 17:39:06 +0530 Message-ID: <20250310120906.1577292-5-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250310120906.1577292-1-quic_mdalam@quicinc.com> References: <20250310120906.1577292-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gLsQJTIzA5iegtj2Gj6I81OeBN4tKBcR X-Proofpoint-ORIG-GUID: gLsQJTIzA5iegtj2Gj6I81OeBN4tKBcR X-Authority-Analysis: v=2.4 cv=ab+bnQot c=1 sm=1 tr=0 ts=67ced681 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=PIZUERMwkWLMlXSLb_cA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-10_05,2025-03-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 bulkscore=0 mlxscore=0 impostorscore=0 phishscore=0 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503100096 The BAM block expects NAND register addresses to be computed based on the NAND register offset from QPIC base. This value is 0x30000 for ipq9574. Update the 'nandc_offset' value in the qcom_nandc_props appropriately. Signed-off-by: Md Sadre Alam --- Change in [v3] * Added nand_offset for proper address calculation for newer Socs Change in [v2] * This patch was not part of v2 Change in [v1] * This patch was not part of v1 drivers/spi/spi-qpic-snand.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c index 8c413a6a5152..85a742e21cf9 100644 --- a/drivers/spi/spi-qpic-snand.c +++ b/drivers/spi/spi-qpic-snand.c @@ -1604,6 +1604,7 @@ static void qcom_spi_remove(struct platform_device *pdev) static const struct qcom_nandc_props ipq9574_snandc_props = { .dev_cmd_reg_start = 0x7000, .supports_bam = true, + .nandc_offset = 0x30000, }; static const struct of_device_id qcom_snandc_of_match[] = {