From patchwork Mon Mar 10 22:03:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ignacio Encinas X-Patchwork-Id: 14010775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E6B4C282DE for ; Mon, 10 Mar 2025 22:04:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Message-Id:MIME-Version:Subject: Date:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=ewZM+rVuCTtehzjNWnqyPaXxSsK2d44C7lMtaM8ZI5U=; b=M6QB/QvJf1XUsb zn0AZt7LmKqC5fjLAVJHN1ELuCYljgT7hdCOY0Cm43VJJZ05w9yHyiK927jZ7o1uetnlbzkiPWAKH RevEw2/xqFVLO1/f/ERj0tvJjC9mCFpLmsHAy3+AwSQhxzkLwdZduTiIeduShjsKMqwH7k57XqcrQ Orh5qBDeqxPmSm+qjMW4Hoo23Dp6yrRDQO0JadQCVuLissGHt//2tmhhFhFbqbxswutaeJDTCTCgP O+ld3pJOlLk5gq+y81WTlI7iZBUVo/qqoD1QQegsZHEd6B3NY7xHgNvYEi/NM1MPdKqTEGQ/y3xfc bPJSXkw9B2vghO6b9hqQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1trlEV-000000044i4-25T5; Mon, 10 Mar 2025 22:04:23 +0000 Received: from out-183.mta1.migadu.com ([2001:41d0:203:375::b7]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1trlES-000000044e3-37v9 for linux-riscv@lists.infradead.org; Mon, 10 Mar 2025 22:04:22 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iencinas.com; s=key1; t=1741644253; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=vMEhOW9fgJPCr4InVKo09seDTKCph02bUyGs2pruQNI=; b=N28ATju+SsOf5mOLkX4xSXH0ni5rpddkGVzQ0AFC5fZJcs6P9VO9pz7SF8qelSzN+l2NqC 8kfjOzO5vJk/0dupShTH1+xEiBt1YfuUS0lNDnS+CaDl5gjrC+TAduQkxHPxR2JbuBY8dT j2wlpSllboIUsJ5sIPqcjTn/9mOURqWUOYZ6c/TGMSauNtDAR5erQ72gz/Td0PRtI7fBEn BD3YkUwNcoep0OKwNa9/4u5ftcPliRRNb65AdzzivcwQbINktEq+ujn/vjK1IGQJi8uvsS UnVv0QwKNYfl9M/wc/mFp+6ZjOaSkFGFYRITqUfIkQrcf5YsCIKSgtLPRhqhWQ== From: Ignacio Encinas Date: Mon, 10 Mar 2025 23:03:55 +0100 Subject: [PATCH RFC] riscv: introduce asm/swab.h MIME-Version: 1.0 Message-Id: <20250310-riscv-swab-v1-1-34652ef1ee96@iencinas.com> X-B4-Tracking: v=1; b=H4sIAMphz2cC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1MDYwNz3aLM4uQy3eLyxCTdJAvDJEuTRMvEZMMkJaCGgqLUtMwKsGHRSkF uzkqxtbUAh1/042EAAAA= X-Change-ID: 20250307-riscv-swab-b81b94a9ac1b To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti Cc: Eric Biggers , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linux.dev, skhan@linuxfoundation.org, Zhihang Shao , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Ignacio Encinas X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250310_150421_344635_E1FB3D61 X-CRM114-Status: GOOD ( 13.70 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Implement endianness swap macros for RISC-V. Use the rev8 instruction when Zbb is available. Otherwise, rely on the default mask-and-shift implementation. Signed-off-by: Ignacio Encinas --- Motivated by [1]. A couple of things to note: We need a default implementation to fall back on, but there isn't any in `asm-generic/swab.h`. Should I introduce a first patch moving ___constant_swab into include/uapi/asm-generic/swab.h? I don't particularly like the ARCH_SWAB macro but I can't think of anything better that doesn't result in code duplication. Tested with crc_kunit as pointed out here [2]. I can't provide performance numbers as I don't have RISC-V hardware yet. Ccing everyone involved with [1]. [1] https://lore.kernel.org/all/20250302220426.GC2079@quark.localdomain/ [2] https://lore.kernel.org/all/20250216225530.306980-1-ebiggers@kernel.org/ --- arch/riscv/include/asm/swab.h | 81 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) --- base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b change-id: 20250307-riscv-swab-b81b94a9ac1b Best regards, diff --git a/arch/riscv/include/asm/swab.h b/arch/riscv/include/asm/swab.h new file mode 100644 index 0000000000000000000000000000000000000000..8f8a13b343f6ffbefbb3c7747ab4e14243852014 --- /dev/null +++ b/arch/riscv/include/asm/swab.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_RISCV_SWAB_H +#define _ASM_RISCV_SWAB_H + +#include +#include +#include +#include + +#if defined(CONFIG_RISCV_ISA_ZBB) && !defined(NO_ALTERNATIVE) + +/* + * FIXME, RFC PATCH: This is copypasted from include/uapi/linux/swab.h + * should I move these `#defines` to include/uapi/asm-generic/swab.h + * and include that file here and in include/uapi/linux/swab.h ? + */ +#define ___constant_swab16(x) ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((__u32)( \ + (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x) & (__u32)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((__u64)( \ + (((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \ + (((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \ + (((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \ + (((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \ + (((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ + (((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ + (((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \ + (((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56))) + +#define ___constant_swahw32(x) ((__u32)( \ + (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \ + (((__u32)(x) & (__u32)0xffff0000UL) >> 16))) + +#define ___constant_swahb32(x) ((__u32)( \ + (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \ + (((__u32)(x) & (__u32)0xff00ff00UL) >> 8))) + + +#define ARCH_SWAB(size) \ +static __always_inline unsigned long __arch_swab##size(__u##size value) \ +{ \ + unsigned long x = value; \ + \ + asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, \ + RISCV_ISA_EXT_ZBB, 1) \ + :::: legacy); \ + \ + asm volatile (".option push\n" \ + ".option arch,+zbb\n" \ + "rev8 %0, %1\n" \ + ".option pop\n" \ + : "=r" (x) : "r" (x)); \ + \ + return x >> (BITS_PER_LONG - size); \ + \ +legacy: \ + return ___constant_swab##size(value); \ +} + +#ifdef CONFIG_64BIT +ARCH_SWAB(64) +#define __arch_swab64 __arch_swab64 +#endif + +ARCH_SWAB(32) +#define __arch_swab32 __arch_swab32 + +ARCH_SWAB(16) +#define __arch_swab16 __arch_swab16 + +#undef ARCH_SWAB + +#endif /* defined(CONFIG_RISCV_ISA_ZBB) && !defined(NO_ALTERNATIVE) */ +#endif /* _ASM_RISCV_SWAB_H */