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Tue, 11 Mar 2025 02:25:44 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:5946:3143:114d:3f3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43cea8076fcsm107436465e9.15.2025.03.11.02.25.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 02:25:44 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 11 Mar 2025 10:25:32 +0100 Subject: [PATCH v7 1/8] dmaengine: add DMA_PREP_LOCK and DMA_PREP_UNLOCK flag Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250311-qce-cmd-descr-v7-1-db613f5d9c9f@linaro.org> References: <20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org> In-Reply-To: <20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org> To: Thara Gopinath , Herbert Xu , "David S. Miller" , Vinod Koul , Jonathan Corbet , Md Sadre Alam , Srinivas Kandagatla Cc: linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2774; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=k2JNoMjqu4cYCUFiyyJ8BPrYhDNDgsHQ3cmq2EXWh1k=; b=kA0DAAoBEacuoBRx13IByyZiAGfQAZWh0+HkXZGtwrVkV1G+XYQw0IWSpnVma/ebtd5F7Du/S IkCMwQAAQoAHRYhBBad62wLw8RgE9LHnxGnLqAUcddyBQJn0AGVAAoJEBGnLqAUcddyugMQAIb2 9t62ThB4WAqWMp3QPQOIzKHALZYmvL4AHTh9fIp1/ow2BhYp7c/Zv+VbTeVDCy0FH2GtIK1ug6z FPn0S9v28+YzAsGaFkop5aGnZ9XqxKgJlRrRk+0OrXk3SWyFMGmdma+M+l5KY0eidSnPqEGbSY+ Q+IY8XFnp4jnpUGLY+MLS/n3bP6UshcG9s/GKHuNAjR5x38vZfGztqfHWP0xN4UnMOQmNQ42w26 ctpPVOaxlelQcJvupoTgk1hbRTPPd53OVbn7XAxQT/WkcRYSS3rwN6Llb0IOusf0e6Ai1BEzE23 UoRwDDnxCqNjFXCBeq7sf/IaX94knSksW2xpibpnHa16eMnNrSpNhEYTGUQ7NTnGmQa60cX0p1g t16UQRof0YGyy0yy91dstL3fnutR9Y+KJH3XwRooqQESV/YSkN39asspgrStieDyJjGBWC5XLcU KhDfAqoSZaVBzVSpgcdCvk+Fecllq2DGeUuwo7lRVkJLoHbJDmCzppR+yDd+aRbff0vXPcfIq+B C11yi4JZ8AslaKvk7h644Y2SVg9IQE1VbNzZ+MRrg16Bd+NnFPz49qXL1l+2r55gQqkinLffep5 4OfN8d0viViFKkWJ8XLS8wxldDK0nXFfbw4rR5Y4jU2myRq7tpgioj5epPqEa/YVsDz4bqrTMMu +UG9J X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Md Sadre Alam Add lock and unlock flags for the command descriptor. With the former set in the requester pipe, the bam controller will lock all other pipes and process the request only from requester pipe. Unlocking can only be performed from the same pipe. Setting the DMA_PREP_LOCK/DMA_PREP_UNLOCK flags in the command descriptor means, the caller requests the BAM controller to be locked for the duration of the transaction. In this case the BAM driver must set the LOCK/UNLOCK bits in the HW descriptor respectively. Only BAM IPs version 1.4.0 and above support the LOCK/UNLOCK feature. Signed-off-by: Md Sadre Alam [Bartosz: reworked the commit message] Signed-off-by: Bartosz Golaszewski --- Documentation/driver-api/dmaengine/provider.rst | 15 +++++++++++++++ include/linux/dmaengine.h | 6 ++++++ 2 files changed, 21 insertions(+) diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index 3085f8b460fa..a032e55d0a4f 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -628,6 +628,21 @@ DMA_CTRL_REUSE - This flag is only supported if the channel reports the DMA_LOAD_EOT capability. +- DMA_PREP_LOCK + + - If set, the DMA will lock all other pipes not related to the current + pipe group, and keep handling the current pipe only. + + - All pipes not within this group will be locked by this pipe upon lock + event. + + - only pipes which are in the same group and relate to the same Environment + Execution(EE) will not be locked by a certain pipe. + +- DMA_PREP_UNLOCK + + - If set, DMA will release all locked pipes + General Design Notes ==================== diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 346251bf1026..8ebd43a998a7 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -200,6 +200,10 @@ struct dma_vec { * transaction is marked with DMA_PREP_REPEAT will cause the new transaction * to never be processed and stay in the issued queue forever. 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Tue, 11 Mar 2025 02:25:45 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:5946:3143:114d:3f3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43cea8076fcsm107436465e9.15.2025.03.11.02.25.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 02:25:45 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 11 Mar 2025 10:25:33 +0100 Subject: [PATCH v7 2/8] dmaengine: qcom: bam_dma: extend the driver's device match data Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250311-qce-cmd-descr-v7-2-db613f5d9c9f@linaro.org> References: <20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org> In-Reply-To: <20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org> To: Thara Gopinath , Herbert Xu , "David S. Miller" , Vinod Koul , Jonathan Corbet , Md Sadre Alam , Srinivas Kandagatla Cc: linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3543; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=Pg4kQtSGs2f8BpuZiVEMtvVvzRRbqxcmk7ypHqWY96M=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBn0AGVl3C5lSeEdfpfP+zIBEzDJCcFCX2vmzasU gOKZib0fpaJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCZ9ABlQAKCRARpy6gFHHX chhBD/wIRjW/QOjQXff90g8HVICSDdXkKD5BRJH+wautyIX+duSZp1IFDylvKfYIMy5QHl3mTXA NTYdCzfKfzTze5I89ENDmJ+OsVC8tnYN7Qn+kPwfwYEZVFsMg9LOJHBAAOFV26FljVkgRCmImL6 WHhu6e5mJFZrqmmZLZTLGRPhO2MkzHi/QzqnFmRkILhrjaOq0rNMRtoky8jyIA10i7c98vSbUNj 05A0K55UIiNCd9o+jrsZeXG3zus+Fk+BYi0ai+cTWVBdTHYBAapa9MPPc5pCXT97mH3mJ52LzQl FVK+JbAYbRrs5A0OEiiTbkPtUNQIFUc7BUTOaPs6T1rde8MpuUi7b2+g2UhP0XmTIE1Pp0QKpIG cH7nucGIbu6fIjTG7TG9WO/+dmbd+SheIslA0pV17/0NFf7XF2FBYsMBxT/9yKMw9TOy0JCui8I Jn1jwBI3kY9AuUogPDDztpNoH5odNstKWFndGe2zgNQKEYKdyc7r7zt0ipC8e42XzsWZxU8bWXS a9mrdwihu61+tkiIuBmfVBSkeY3jRvnwTHtmcnT4tgiIsaLlZ4uX2buJg8EADfrpNq57XUPZ4Pd n/ybHmqcs/IEInA7ifOjGoq+bMe77cfKHL+wh2sNuSiEdcllYVbSTyx/HaAnO+JIYDCY6dPZV1p at4UvxJfshZDpkA== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski In preparation for supporting the pipe locking feature flag, extend the amount of information we can carry in device match data: create a separate structure and make the register information one of its fields. This way, in subsequent patches, it will be just a matter of adding a new field to the device data. Signed-off-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov --- drivers/dma/qcom/bam_dma.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 2cf060174795..8861245314b1 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -111,6 +111,10 @@ struct reg_offset_data { unsigned int pipe_mult, evnt_mult, ee_mult; }; +struct bam_device_data { + const struct reg_offset_data *reg_info; +}; + static const struct reg_offset_data bam_v1_3_reg_info[] = { [BAM_CTRL] = { 0x0F80, 0x00, 0x00, 0x00 }, [BAM_REVISION] = { 0x0F84, 0x00, 0x00, 0x00 }, @@ -140,6 +144,10 @@ static const struct reg_offset_data bam_v1_3_reg_info[] = { [BAM_P_FIFO_SIZES] = { 0x1020, 0x00, 0x40, 0x00 }, }; +static const struct bam_device_data bam_v1_3_data = { + .reg_info = bam_v1_3_reg_info, +}; + static const struct reg_offset_data bam_v1_4_reg_info[] = { [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 }, [BAM_REVISION] = { 0x0004, 0x00, 0x00, 0x00 }, @@ -169,6 +177,10 @@ static const struct reg_offset_data bam_v1_4_reg_info[] = { [BAM_P_FIFO_SIZES] = { 0x1820, 0x00, 0x1000, 0x00 }, }; +static const struct bam_device_data bam_v1_4_data = { + .reg_info = bam_v1_4_reg_info, +}; + static const struct reg_offset_data bam_v1_7_reg_info[] = { [BAM_CTRL] = { 0x00000, 0x00, 0x00, 0x00 }, [BAM_REVISION] = { 0x01000, 0x00, 0x00, 0x00 }, @@ -198,6 +210,10 @@ static const struct reg_offset_data bam_v1_7_reg_info[] = { [BAM_P_FIFO_SIZES] = { 0x13820, 0x00, 0x1000, 0x00 }, }; +static const struct bam_device_data bam_v1_7_data = { + .reg_info = bam_v1_7_reg_info, +}; + /* BAM CTRL */ #define BAM_SW_RST BIT(0) #define BAM_EN BIT(1) @@ -391,7 +407,7 @@ struct bam_device { bool powered_remotely; u32 active_channels; - const struct reg_offset_data *layout; + const struct bam_device_data *dev_data; struct clk *bamclk; int irq; @@ -409,7 +425,7 @@ struct bam_device { static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe, enum bam_reg reg) { - const struct reg_offset_data r = bdev->layout[reg]; + const struct reg_offset_data r = bdev->dev_data->reg_info[reg]; return bdev->regs + r.base_offset + r.pipe_mult * pipe + @@ -1225,9 +1241,9 @@ static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan, } static const struct of_device_id bam_of_match[] = { - { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info }, - { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info }, - { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_reg_info }, + { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_data }, + { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_data }, + { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_data }, {} }; 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Tue, 11 Mar 2025 02:25:46 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:5946:3143:114d:3f3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43cea8076fcsm107436465e9.15.2025.03.11.02.25.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 02:25:46 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 11 Mar 2025 10:25:34 +0100 Subject: [PATCH v7 3/8] dmaengine: qcom: bam_dma: add bam_pipe_lock flag support Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250311-qce-cmd-descr-v7-3-db613f5d9c9f@linaro.org> References: <20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org> In-Reply-To: <20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org> To: Thara Gopinath , Herbert Xu , "David S. Miller" , Vinod Koul , Jonathan Corbet , Md Sadre Alam , Srinivas Kandagatla Cc: linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2188; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=q/3RP4DiTyaxTRnIH/tALxp3dBkxS3/vcvd9GKBezPM=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBn0AGVUBvjeQRh7H7aAx1rE8T2VzvFTVozUiuqz vf1B0ns0RSJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCZ9ABlQAKCRARpy6gFHHX cjelEACN3/JUgds8V7OXUaqnsGAgQkUwmon/d9kX8vT1YYVYYguRoqUrSTNeC9njYmcKrucjs5K k2k1oWasiHuafyOeEVIAqLtsXUL6sYz2cSKDl3j4dnfK1HSRE9Uh/ESR3JawYqwT4JI/cZXI6A/ JOPdtRb2ik4iGtUSxn3Uz4rEGv7zfeCKzfUTl+VimkvHv8coNAghD9bI5NsaN3Xo59kB4KesWQb j75ftmhE7WcPw6L6k0H0Y5C394+rKmt4xoFpDczUY/Lbqxbqh9tM3zjFV8H8XNqkE4OWujEkwG6 flbnLqZNiwDxXZg6bRFG24STnKsv/TsTlc54mnt3w9N2nurVJCEI0I6HoWgrv1bNaeySWOb6GS0 hdsCEU9sdYkts4FjT38yi81tbluPpvbOkfn6XOTaynYBMbqoKG0CB8TSjmM5yT58vXEDHqWME1/ r6KKVRQT+1ySkn/cXyBHRT7U3iE3jbWhjp63WTx9zGNmKVuyr1m1jXJRIa6iOHOrqmKDa4sZivJ szseRtVCJsUJ7iUeQSa5RcgQ6rtLTx0MXlxpdjTBuTUmrXvWlo3Qf5rQC/T+oyAUqiZ2+GFPPcT FH5+7j4YRP29sYKuIE0FRl+7zF4fPmhTHyohLVoDmGrF6jrQUPh5arOPMJv7tADVTNJDiX9gFPf tSS4tBeYqPZmF/Q== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Extend the device match data with a flag indicating whether the IP supports the BAM lock/unlock feature. Set it to true on BAM IP versions 1.4.0 and above. Co-developed-by: Md Sadre Alam Signed-off-by: Md Sadre Alam Signed-off-by: Bartosz Golaszewski --- drivers/dma/qcom/bam_dma.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 8861245314b1..737fce396c2e 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -58,6 +58,8 @@ struct bam_desc_hw { #define DESC_FLAG_EOB BIT(13) #define DESC_FLAG_NWD BIT(12) #define DESC_FLAG_CMD BIT(11) +#define DESC_FLAG_LOCK BIT(10) +#define DESC_FLAG_UNLOCK BIT(9) struct bam_async_desc { struct virt_dma_desc vd; @@ -113,6 +115,7 @@ struct reg_offset_data { struct bam_device_data { const struct reg_offset_data *reg_info; + bool bam_pipe_lock; }; static const struct reg_offset_data bam_v1_3_reg_info[] = { @@ -179,6 +182,7 @@ static const struct reg_offset_data bam_v1_4_reg_info[] = { static const struct bam_device_data bam_v1_4_data = { .reg_info = bam_v1_4_reg_info, + .bam_pipe_lock = true, }; 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This allows us to drop two labels and make the devm action callback for DMA channels smaller. Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/dma.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index 1dec7aea852d..6ac2efb7c2f7 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -15,7 +15,6 @@ static void qce_dma_release(void *data) dma_release_channel(dma->txchan); dma_release_channel(dma->rxchan); - kfree(dma->result_buf); } int devm_qce_dma_request(struct device *dev, struct qce_dma_data *dma) @@ -28,26 +27,23 @@ int devm_qce_dma_request(struct device *dev, struct qce_dma_data *dma) dma->rxchan = dma_request_chan(dev, "rx"); if (IS_ERR(dma->rxchan)) { - ret = PTR_ERR(dma->rxchan); - goto error_rx; + dma_release_channel(dma->txchan); + return PTR_ERR(dma->rxchan); } - dma->result_buf = kmalloc(QCE_RESULT_BUF_SZ + QCE_IGNORE_BUF_SZ, - GFP_KERNEL); - if (!dma->result_buf) { - ret = -ENOMEM; - goto error_nomem; - } + ret = devm_add_action_or_reset(dev, qce_dma_release, dma); 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Tue, 11 Mar 2025 02:25:49 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:5946:3143:114d:3f3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43cea8076fcsm107436465e9.15.2025.03.11.02.25.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 02:25:48 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 11 Mar 2025 10:25:36 +0100 Subject: [PATCH v7 5/8] crypto: qce - Map crypto memory for DMA Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250311-qce-cmd-descr-v7-5-db613f5d9c9f@linaro.org> References: <20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org> In-Reply-To: <20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org> To: Thara Gopinath , Herbert Xu , "David S. Miller" , Vinod Koul , Jonathan Corbet , Md Sadre Alam , Srinivas Kandagatla Cc: linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3050; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=9sPBxi7WcEbGhZ0zJXrjtGJm1E4sIIJKZPL3u1QqT70=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBn0AGWE9pP2abtJs+cO7NhWomGNMzeg6/jFNn1m ety2TFhJuuJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCZ9ABlgAKCRARpy6gFHHX cpSSD/91fZUju4zUV/ZekXs1tZBoKMTQqJ+czHlnxT11MLiRsg/LV4MsJahOedMuSoql8s62r/W 8yv/rhWQ2jJu4dFi+7yUsgOuzkovq3C3I4LBY5nOIHGrzndfMDLRKKj+MmcQtgb++A2ARlFYZQj OonHKfEbymseprlvt2ujCmqw1Z1erF7SUTJ5Qcve1IZwxDOUx+Jcjsdek+iZErQJp3N3MzyabIg rLOltvTYAaSAv3mEVFjvQzPXDdJwH/XItvbz/kWPwTxNEZ7IPYOCc1xkmBfHGYQAJwZaZRrNetr EerORctn8YIZ4Pu5/ReqMOpPLCafLqW8DNVShzhXQmsBr0NCQMQKLhqGoywMJZh53eoYXlyNQuG P4pRaPRQk8OXUg2UQ1j6DX40dO4CwcffVbHGKY2b/RpkHzmC71oKQ9GperypP6I2X8NJOGfLag6 9Bh9KNtjmNKNR3NAKJu0VmW7JnFghbETHCCV75FEyaoJOkvhggnLqZMjqoh+4hK4fUypbac5h55 hT8Oi6+Qz8mXQwQgKwpUjnnNJl6KKx6MGu+6FpKrmlE9bG+r7GeK+Mp7eKudruwF+IiKclRg7eT ACvkewx/fYjaU0HcoMsSivLwCXRXH+e0FDxMHzaT3XW2nYcLSBiOJ+62m0670IEyarKdEOAhV4b dSs3QNcfVaEhSwQ== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Md Sadre Alam In preparation for supporting command descriptors, map the crypto memory range for DMA. Signed-off-by: Md Sadre Alam [Bartosz: add kerneldocs, fix DMA mapping leak, rework commit message] Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/core.c | 24 ++++++++++++++++++++++-- drivers/crypto/qce/core.h | 4 ++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index e95e84486d9a..b21c4ecd2034 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -187,10 +187,19 @@ static int qce_check_version(struct qce_device *qce) return 0; } +static void qce_crypto_unmap_dma(void *data) +{ + struct qce_device *qce = data; + + dma_unmap_resource(qce->dev, qce->base_dma, qce->dma_size, + DMA_BIDIRECTIONAL, 0); +} + static int qce_crypto_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct qce_device *qce; + struct resource *res; int ret; qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); @@ -200,7 +209,7 @@ static int qce_crypto_probe(struct platform_device *pdev) qce->dev = dev; platform_set_drvdata(pdev, qce); - qce->base = devm_platform_ioremap_resource(pdev, 0); + qce->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(qce->base)) return PTR_ERR(qce->base); @@ -246,7 +255,18 @@ static int qce_crypto_probe(struct platform_device *pdev) qce->async_req_enqueue = qce_async_request_enqueue; qce->async_req_done = qce_async_request_done; - return devm_qce_register_algs(qce); + ret = devm_qce_register_algs(qce); + if (ret) + return ret; + + qce->dma_size = resource_size(res); + qce->base_dma = dma_map_resource(dev, res->start, qce->dma_size, + DMA_BIDIRECTIONAL, 0); + ret = dma_mapping_error(dev, qce->base_dma); + if (ret) + return ret; + + return devm_add_action_or_reset(qce->dev, qce_crypto_unmap_dma, qce); } static const struct of_device_id qce_crypto_of_match[] = { diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index eb6fa7a8b64a..b86caf8b926d 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -26,6 +26,8 @@ * @dma: pointer to dma data * @burst_size: the crypto burst size * @pipe_pair_id: which pipe pair id the device using + * @base_dma: base DMA address + * @dma_size: size of memory mapped for DMA * @async_req_enqueue: invoked by every algorithm to enqueue a request * @async_req_done: invoked by every algorithm to finish its request */ @@ -42,6 +44,8 @@ struct qce_device { struct qce_dma_data dma; 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Tue, 11 Mar 2025 02:25:50 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:5946:3143:114d:3f3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43cea8076fcsm107436465e9.15.2025.03.11.02.25.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 02:25:49 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 11 Mar 2025 10:25:37 +0100 Subject: [PATCH v7 6/8] crypto: qce - Add BAM DMA support for crypto register I/O Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250311-qce-cmd-descr-v7-6-db613f5d9c9f@linaro.org> References: <20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org> In-Reply-To: <20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org> To: Thara Gopinath , Herbert Xu , "David S. Miller" , Vinod Koul , Jonathan Corbet , Md Sadre Alam , Srinivas Kandagatla Cc: linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=7268; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=SEtk1J0aHmReVO5qvg2CJQYibstzqGHei3j1EagqZzQ=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBn0AGWWyW4/po0MIHlVXsLPUJZuSDfQ4OEd9Xit SeCx9k8FKeJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCZ9ABlgAKCRARpy6gFHHX cq4VD/9FDpLWt9mPryfeerf+nPVXJLK6pl7LZQ9bw8MBT20l732sLFeEo1fBmFryCq1e8VSqaOy KzOFaDxuetC95xDRefpPGkFDnaP8gQqKchFGjyGW63WhklMmI6ejpdqjM2lLDGhw0pmHwuUixr0 RyIoREuHVYjhCsO/r7Ak1DOqPHX9GvFy4nbWiz5gHFuNeKKnPCIn00IJ13F4wY5SlWrmops+/bJ FiKEFkEj5t8Dq/hhx1IYosQnSvhaQeYlDu83HwsiT5sgPhz9SSy4xR4Fro3Rpd8imzt/8oe3qPz 7aMCrXUjiJTW7RU9ImUcrxg6weDieddBisaB9EITyX6wCAlraPMkPPNQZx2gKMMFlP5MCr9mZnJ HBVMnaWgjbpqit9mMF4Zpev5lKpvz2XaMCZHWoPj216/WVF1GwL5z161Zl84U0mbEOl11+dt3gC Xmb/mkq22/eyWgNvpc3eFFo8rjpsIIctA7RgMDE4Su1cFisReSsDPcLv0oJy/ehLtVUxl7j+HnA LqFpDM625qnIlJ/M0d01QnAdC+Rv+w97EEnIetgwwzLop7imKwr0zMh1OwoUUu95Nusn1Yqinb2 g1N6GeeiGkuceqVBoYXtjjn/xcwMt6/SJKoJ8LyiFriKee3h/gwKxwtt7GZT2oe2EAARGCZNb+4 z+kmGPdAXpvB/Kw== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Md Sadre Alam Add BAM/DMA support infrastructure. These interfaces will allow us to port the algorithm implementations to use DMA for transaction with BAM locking. Signed-off-by: Md Sadre Alam [Bartosz: remove unused code, rework coding style, shuffle code around for better readability, simplify resource management, many other tweaks] Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/dma.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/crypto/qce/dma.h | 17 ++++++ 2 files changed, 156 insertions(+) diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index 6ac2efb7c2f7..71b191944e3f 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -5,10 +5,135 @@ #include #include +#include #include +#include "core.h" #include "dma.h" +struct qce_bam_transaction { + struct bam_cmd_element qce_bam_ce[QCE_BAM_CMD_ELEMENT_SIZE]; + struct scatterlist qce_reg_write_sgl[QCE_BAM_CMD_SGL_SIZE]; + struct qce_desc_info *qce_desc; + u32 qce_bam_ce_index; + u32 qce_pre_bam_ce_index; + u32 qce_write_sgl_cnt; +}; + +void qce_clear_bam_transaction(struct qce_device *qce) +{ + struct qce_bam_transaction *qce_bam_txn = qce->dma.qce_bam_txn; + + memset(&qce_bam_txn->qce_bam_ce_index, 0, sizeof(u32) * 8); +} + +static int qce_dma_prep_cmd_sg(struct qce_device *qce, struct dma_chan *chan, + struct scatterlist *qce_bam_sgl, + int qce_sgl_cnt, unsigned long flags, + enum dma_transfer_direction dir_eng, + dma_async_tx_callback cb, void *cb_param) +{ + struct dma_async_tx_descriptor *dma_desc; + struct qce_desc_info *desc; + dma_cookie_t cookie; + + desc = qce->dma.qce_bam_txn->qce_desc; + + if (dir_eng == DMA_MEM_TO_DEV) + desc->dir = DMA_TO_DEVICE; + if (dir_eng == DMA_DEV_TO_MEM) + desc->dir = DMA_FROM_DEVICE; + + if (!qce_bam_sgl || !qce_sgl_cnt) + return -EINVAL; + + if (!dma_map_sg(qce->dev, qce_bam_sgl, + qce_sgl_cnt, desc->dir)) { + dev_err(qce->dev, "failure in mapping sgl for cmd desc\n"); + return -ENOMEM; + } + + dma_desc = dmaengine_prep_slave_sg(chan, qce_bam_sgl, qce_sgl_cnt, + dir_eng, flags); + if (!dma_desc) { + dev_err(qce->dev, "failed to prepare the command descriptor\n"); + dma_unmap_sg(qce->dev, qce_bam_sgl, qce_sgl_cnt, desc->dir); + kfree(desc); + return -EINVAL; + } + + desc->dma_desc = dma_desc; + desc->dma_desc->callback = cb; + desc->dma_desc->callback_param = cb_param; + + cookie = dmaengine_submit(desc->dma_desc); + + return dma_submit_error(cookie); +} + +int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags) +{ + struct qce_bam_transaction *qce_bam_txn = qce->dma.qce_bam_txn; + struct dma_chan *chan = qce->dma.rxchan; + unsigned long desc_flags; + int ret = 0; + + desc_flags = DMA_PREP_CMD; + + /* + * The HPG recommends always using the consumer pipe for command + * descriptors. + */ + if (qce_bam_txn->qce_write_sgl_cnt) + ret = qce_dma_prep_cmd_sg(qce, chan, qce_bam_txn->qce_reg_write_sgl, + qce_bam_txn->qce_write_sgl_cnt, + desc_flags, DMA_MEM_TO_DEV, + NULL, NULL); + if (ret) { + dev_err(qce->dev, + "error while submitting the command descriptor for TX: %d\n", + ret); + return ret; + } + + qce_dma_issue_pending(&qce->dma); + + if (qce_bam_txn->qce_write_sgl_cnt) + dma_unmap_sg(qce->dev, qce_bam_txn->qce_reg_write_sgl, + qce_bam_txn->qce_write_sgl_cnt, + DMA_TO_DEVICE); + + return ret; +} + +static __maybe_unused void +qce_prep_dma_command_desc(struct qce_device *qce, struct qce_dma_data *dma, + unsigned int addr, void *buff) +{ + struct qce_bam_transaction *qce_bam_txn = dma->qce_bam_txn; + struct bam_cmd_element *qce_bam_ce_buffer; + int qce_bam_ce_size, cnt, index; + + index = qce_bam_txn->qce_bam_ce_index; + qce_bam_ce_buffer = &qce_bam_txn->qce_bam_ce[index]; + bam_prep_ce_le32(qce_bam_ce_buffer, addr, BAM_WRITE_COMMAND, + *((__le32 *)buff)); + + cnt = qce_bam_txn->qce_write_sgl_cnt; + qce_bam_ce_buffer = + &qce_bam_txn->qce_bam_ce[qce_bam_txn->qce_pre_bam_ce_index]; + ++qce_bam_txn->qce_bam_ce_index; + qce_bam_ce_size = (qce_bam_txn->qce_bam_ce_index - + qce_bam_txn->qce_pre_bam_ce_index) * + sizeof(struct bam_cmd_element); + + sg_set_buf(&qce_bam_txn->qce_reg_write_sgl[cnt], qce_bam_ce_buffer, + qce_bam_ce_size); + + ++qce_bam_txn->qce_write_sgl_cnt; + qce_bam_txn->qce_pre_bam_ce_index = qce_bam_txn->qce_bam_ce_index; +} + static void qce_dma_release(void *data) { struct qce_dma_data *dma = data; @@ -19,6 +144,7 @@ static void qce_dma_release(void *data) int devm_qce_dma_request(struct device *dev, struct qce_dma_data *dma) { + struct qce_bam_transaction *qce_bam_txn; int ret; dma->txchan = dma_request_chan(dev, "tx"); @@ -43,6 +169,19 @@ int devm_qce_dma_request(struct device *dev, struct qce_dma_data *dma) dma->ignore_buf = dma->result_buf + QCE_RESULT_BUF_SZ; + dma->qce_bam_txn = devm_kmalloc(dev, sizeof(*qce_bam_txn), GFP_KERNEL); + if (!dma->qce_bam_txn) + return -ENOMEM; + + dma->qce_bam_txn->qce_desc = devm_kzalloc(dev, + sizeof(*dma->qce_bam_txn->qce_desc), + GFP_KERNEL); + if (!dma->qce_bam_txn->qce_desc) + return -ENOMEM; + + sg_init_table(dma->qce_bam_txn->qce_reg_write_sgl, + QCE_BAM_CMD_SGL_SIZE); + return 0; } diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index 31629185000e..7d9d58b414ed 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -6,14 +6,22 @@ #ifndef _DMA_H_ #define _DMA_H_ +#include #include +struct qce_device; + /* maximum data transfer block size between BAM and CE */ #define QCE_BAM_BURST_SIZE 64 #define QCE_AUTHIV_REGS_CNT 16 #define QCE_AUTH_BYTECOUNT_REGS_CNT 4 #define QCE_CNTRIV_REGS_CNT 4 +#define QCE_BAM_CMD_SGL_SIZE 64 +#define QCE_BAM_CMD_ELEMENT_SIZE 64 +#define QCE_DMA_DESC_FLAG_BAM_NWD (0x0004) +#define QCE_MAX_REG_READ 8 + struct qce_result_dump { u32 auth_iv[QCE_AUTHIV_REGS_CNT]; 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Miller" , Vinod Koul , Jonathan Corbet , Md Sadre Alam , Srinivas Kandagatla Cc: linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4727; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=Ummz+nuGMXPRajfLduo+chy+xyXsFEfhI+3un0WGWII=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBn0AGWBpep/bMxzHaVQ/LP3izEIuA5yaLo/RFaG 4AmPWJibzmJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCZ9ABlgAKCRARpy6gFHHX co0pEADKnxz86ATPO90pb6sb4gzp0jyiY6t5PhpXJGqPeBK/X06TiIWtC7rnot42QQM0qPTWcJj yLF7pvYjPv7xO3cT0FmAkur+HvME67DfwS0OxXi4fm8XMDXRFywJv627WlaZldp/iUMMSMXURA0 o5M3ogaNrksZjI/M+x/RTeV6xRQbGS4UJ2CfBbs9936nqo3IvX9vQM65E5HjwUvRAQhe1g4zcdn knCnAsF6Ountz7kYwmgF4SXfsWhRpYi3jX+c4Sjc71bNqhCM58hrRQZjEDYRcdG8+3ADHnpV5DL eosMm7hM3ikdy8TEKxFyQK3sE0PApTGW5wK7K7AajDbglSpLCZCYRo/TC6kSt6ohHg6HQQL9aqE deTLkw1jJfPE4ZUR4ADxzAj7rxSIOqCJNjoTo2pVgT0av3VsGNmZeO8P5CU4+9sQMrCXYYmOwii n+ugme68vbrv5lx/R6hN4csW0cYaAUueu9gOe0aQw+i/KVSaPjHGzNaQzNBu6wBRMfqbcvb0j16 WmdKpRY/DTsqzqv/FMEZ2uAXlbVeuLO4VfC+tpeh8mGxen2yG6lUdZVBkGjcKGl/RS8em/L4+Ko NMPqRWVfahE6OfVHvK5kXuk5+iM2PciONT2DXkobzz+R9+4v35b/AI6ggGbe3mGqp9ROpEjLu/e 4c8QR4FQM9xnIvw== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Replace the qce_write() implementation with one that uses DMA. Convert all algorithm implementations to use command descriptors. This makes the driver use BAM DMA exclusively instead of register read/writes. Co-developed-by: Md Sadre Alam Signed-off-by: Md Sadre Alam Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/common.c | 17 +++++++++-------- drivers/crypto/qce/common.h | 1 + drivers/crypto/qce/dma.c | 13 ++++++++++--- 3 files changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index 04253a8d3340..80984e853454 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -23,11 +23,6 @@ static inline u32 qce_read(struct qce_device *qce, u32 offset) return readl(qce->base + offset); } -static inline void qce_write(struct qce_device *qce, u32 offset, u32 val) -{ - writel(val, qce->base + offset); -} - static inline void qce_write_array(struct qce_device *qce, u32 offset, const u32 *val, unsigned int len) { @@ -157,11 +152,13 @@ static int qce_setup_regs_ahash(struct crypto_async_request *async_req) __be32 mackey[QCE_SHA_HMAC_KEY_SIZE / sizeof(__be32)] = {0}; u32 auth_cfg = 0, config; unsigned int iv_words; + int ret; /* if not the last, the size has to be on the block boundary */ if (!rctx->last_blk && req->nbytes % blocksize) return -EINVAL; + qce_clear_bam_transaction(qce); qce_setup_config(qce); if (IS_CMAC(rctx->flags)) { @@ -225,7 +222,7 @@ static int qce_setup_regs_ahash(struct crypto_async_request *async_req) qce_crypto_go(qce, true); - return 0; + return qce_submit_cmd_desc(qce, 0); } #endif @@ -325,7 +322,9 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) u32 encr_cfg = 0, auth_cfg = 0, config; unsigned int ivsize = rctx->ivsize; unsigned long flags = rctx->flags; + int ret; + qce_clear_bam_transaction(qce); qce_setup_config(qce); if (IS_XTS(flags)) @@ -388,7 +387,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) qce_crypto_go(qce, true); - return 0; + return qce_submit_cmd_desc(qce, 0); } #endif @@ -438,7 +437,9 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) unsigned long flags = rctx->flags; u32 encr_cfg, auth_cfg, config, totallen; u32 iv_last_word; + int ret; + qce_clear_bam_transaction(qce); qce_setup_config(qce); /* Write encryption key */ @@ -537,7 +538,7 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) /* Start the process */ qce_crypto_go(qce, !IS_CCM(flags)); - return 0; + return qce_submit_cmd_desc(qce, 0); } #endif diff --git a/drivers/crypto/qce/common.h b/drivers/crypto/qce/common.h index 02e63ad9f245..ec58c1b6aa36 100644 --- a/drivers/crypto/qce/common.h +++ b/drivers/crypto/qce/common.h @@ -100,5 +100,6 @@ void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len); int qce_check_status(struct qce_device *qce, u32 *status); void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step); int qce_start(struct crypto_async_request *async_req, u32 type); +void qce_write(struct qce_device *qce, unsigned int offset, u32 val); #endif /* _COMMON_H_ */ diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index 71b191944e3f..b8b305fc1b6a 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -8,6 +8,7 @@ #include #include +#include "common.h" #include "core.h" #include "dma.h" @@ -106,9 +107,9 @@ int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags) return ret; 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Tue, 11 Mar 2025 02:25:53 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:5946:3143:114d:3f3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43cea8076fcsm107436465e9.15.2025.03.11.02.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 02:25:52 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 11 Mar 2025 10:25:39 +0100 Subject: [PATCH v7 8/8] crypto: qce - Add support for BAM locking Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250311-qce-cmd-descr-v7-8-db613f5d9c9f@linaro.org> References: <20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org> In-Reply-To: <20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org> To: Thara Gopinath , Herbert Xu , "David S. Miller" , Vinod Koul , Jonathan Corbet , Md Sadre Alam , Srinivas Kandagatla Cc: linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=6057; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=mrvGg9IYidCko0IY95KksqDIDUmheB3bWnzVDjWoezs=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBn0AGW3z/MEW+57clZJmFBlWb40oPbtQUg+R7rM RG+pb3potqJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCZ9ABlgAKCRARpy6gFHHX coa+EACj+s86pmH1/FV+U6jTKbWslnLU5pSjxSz1J1xTIPXHByRw3DxuqMVwyNyB0OVctxAHYuU WUfeNHgjhkY7mdhu7ruUxgA/DbpAggoCPnzd0T3EHbSRGj/NVsalYensT/Wzx/73Ac6HIeI8eEQ s0746GNrevv9VM+ZIa6vfd6wSEsiY0QC9CpQOVWPmIzJYjd5XOkFTUgLrGczu5fvZ1fACWGp7O7 FQFiged/bW9zhEhdXYwQ+mX5Fv23kl1C/2VDsnqN/o1xlTZwe17rZkJMIPUP2wdJNXoiY5x6P0p tovPkf3+Mt410WvjsQLNZGF1CGQg10KfG37jX2rbdtlXRtTbY0hMXxnbVQkErvynLnNWS/GLVZM tqsoHO9lNg0iS4CCZ+gsXI+sS6A0FkgqNb/jjYWmZ+FyqGWdBpyLqXnmmpfvUmniL599tbxIIVr Xf29NF721nqKzCBuYyRT2IyCoSkmMLGiVoWffuAsUCntsp6LqXr+hRyfZqCqw2dDC6sW+xx8hn+ 09zGux2N0SaKZVwC/PkwySuWxufy+/0wcLoHV0esnnXhYeFqMTCBu20uaC5sU4joRbK4vwGRwCk JdSCafXkHVRTe/CW7HdQgTgYAEwGNTTJ7YYeyGZJQpjdbFmCTI0MjGstjMtZbaF1iFB0QWOIRMs GcJc1JMeyE0EXVw== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Md Sadre Alam The BAM driver now supports command descriptor locking. Add helper functions that perform the dummy writes and acquire/release the lock and use them across the supported algos. With this: if mutliple execution environments (e.g.: a trusted app and linux) try to access the same crypto engine, we can serialize their accesses. Signed-off-by: Md Sadre Alam [Bartosz: rework the coding style, naming convention, commit message and ifdef logic] Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/aead.c | 4 ++++ drivers/crypto/qce/common.c | 30 ++++++++++++++++++++++++++++++ drivers/crypto/qce/core.h | 3 +++ drivers/crypto/qce/dma.c | 4 ++++ drivers/crypto/qce/dma.h | 2 ++ drivers/crypto/qce/sha.c | 4 ++++ drivers/crypto/qce/skcipher.c | 4 ++++ 7 files changed, 51 insertions(+) diff --git a/drivers/crypto/qce/aead.c b/drivers/crypto/qce/aead.c index 11cec08544c9..5d45841c029e 100644 --- a/drivers/crypto/qce/aead.c +++ b/drivers/crypto/qce/aead.c @@ -63,6 +63,8 @@ static void qce_aead_done(void *data) sg_free_table(&rctx->dst_tbl); } + qce_bam_unlock(qce); + error = qce_check_status(qce, &status); if (error < 0 && (error != -EBADMSG)) dev_err(qce->dev, "aead operation error (%x)\n", status); @@ -433,6 +435,8 @@ qce_aead_async_req_handle(struct crypto_async_request *async_req) else rctx->assoclen = req->assoclen; + qce_bam_lock(qce); + diff_dst = (req->src != req->dst) ? true : false; dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL; diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index 80984e853454..251bf3cb1dd5 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -565,6 +565,36 @@ int qce_start(struct crypto_async_request *async_req, u32 type) #define STATUS_ERRORS \ (BIT(SW_ERR_SHIFT) | BIT(AXI_ERR_SHIFT) | BIT(HSD_ERR_SHIFT)) +void qce_bam_lock(struct qce_device *qce) +{ + int ret; + + qce_clear_bam_transaction(qce); + + /* This is just a dummy write to acquire the lock on the BAM pipe. */ + qce_write(qce, REG_AUTH_SEG_CFG, 0); + + ret = qce_submit_cmd_desc(qce, QCE_DMA_DESC_FLAG_LOCK); + if (ret) + dev_err(qce->dev, + "Failed to lock the command descriptor: %d\n", ret); +} + +void qce_bam_unlock(struct qce_device *qce) +{ + int ret; + + qce_clear_bam_transaction(qce); + + /* This just dummy write to release the lock on the BAM pipe. */ + qce_write(qce, REG_AUTH_SEG_CFG, 0); + + ret = qce_submit_cmd_desc(qce, QCE_DMA_DESC_FLAG_UNLOCK); + if (ret) + dev_err(qce->dev, + "Failed to unlock the command descriptor: %d\n", ret); +} + int qce_check_status(struct qce_device *qce, u32 *status) { int ret = 0; diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index b86caf8b926d..3341571991a4 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -65,4 +65,7 @@ struct qce_algo_ops { int (*async_req_handle)(struct crypto_async_request *async_req); }; +void qce_bam_lock(struct qce_device *qce); +void qce_bam_unlock(struct qce_device *qce); + #endif /* _CORE_H_ */ diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index b8b305fc1b6a..f3178144fa94 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -80,6 +80,10 @@ int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags) int ret = 0; desc_flags = DMA_PREP_CMD; + if (flags & QCE_DMA_DESC_FLAG_LOCK) + desc_flags |= DMA_PREP_LOCK; + else if (flags & QCE_DMA_DESC_FLAG_UNLOCK) + desc_flags |= DMA_PREP_UNLOCK; /* * The HPG recommends always using the consumer pipe for command diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index 7d9d58b414ed..c98dcab1dc62 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -21,6 +21,8 @@ struct qce_device; #define QCE_BAM_CMD_ELEMENT_SIZE 64 #define QCE_DMA_DESC_FLAG_BAM_NWD (0x0004) #define QCE_MAX_REG_READ 8 +#define QCE_DMA_DESC_FLAG_LOCK (0x0002) +#define QCE_DMA_DESC_FLAG_UNLOCK (0x0001) struct qce_result_dump { diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c index 0c7aab711b7b..4c701fca16f2 100644 --- a/drivers/crypto/qce/sha.c +++ b/drivers/crypto/qce/sha.c @@ -60,6 +60,8 @@ static void qce_ahash_done(void *data) rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]); rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]); + qce_bam_unlock(qce); + error = qce_check_status(qce, &status); if (error < 0) dev_dbg(qce->dev, "ahash operation error (%x)\n", status); @@ -90,6 +92,8 @@ static int qce_ahash_async_req_handle(struct crypto_async_request *async_req) rctx->authklen = AES_KEYSIZE_128; } + qce_bam_lock(qce); + rctx->src_nents = sg_nents_for_len(req->src, req->nbytes); if (rctx->src_nents < 0) { dev_err(qce->dev, "Invalid numbers of src SG.\n"); diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index cab796cd7e43..42414fe9b787 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -52,6 +52,8 @@ static void qce_skcipher_done(void *data) sg_free_table(&rctx->dst_tbl); + qce_bam_unlock(qce); + error = qce_check_status(qce, &status); if (error < 0) dev_dbg(qce->dev, "skcipher operation error (%x)\n", status); @@ -82,6 +84,8 @@ qce_skcipher_async_req_handle(struct crypto_async_request *async_req) dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL; + qce_bam_lock(qce); + rctx->src_nents = sg_nents_for_len(req->src, req->cryptlen); if (diff_dst) rctx->dst_nents = sg_nents_for_len(req->dst, req->cryptlen);