From patchwork Thu Mar 13 14:23:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 14015176 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9707711CA9; Thu, 13 Mar 2025 14:24:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741875842; cv=none; b=kgGphikvM0McSxqh6p/k0Afsb5ibCQGqjlr6IwgTBeqZ5wslx5ZWmZa3R+ur/ybwg5TqRb7N0+BakrNwyLkK6HS0kKfs3ElTjSdabElbUgoDnwQqbDffmVHrAeksdfR0oLLwU9isFP9rcU2w7mLDqG445ZMLp9xE3stkHljQ4Lo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741875842; c=relaxed/simple; bh=NXrvr52QEd3dyKE2/9JNvYBGy5hL4EsZu3YzjUhsF18=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=VwLZ3GzPDVjtePkh0MYfoLcMAOMr7tlpgPY7I1rjz2A2G/e7KoTVpFR5AdtpaXl2FiARs4n6GkbeKqGRj3KeAgcrYGkkeW8NqsK1WuINQK+VbcT3C6DxCaTkYEZaYaMigoWjfvu1Yvbn7yXrz5O47FOYZIIndh2EUcKRdAxZIC8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Ynl62L1E; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ynl62L1E" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741875841; x=1773411841; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NXrvr52QEd3dyKE2/9JNvYBGy5hL4EsZu3YzjUhsF18=; b=Ynl62L1EIgO6BSaU4fpdYEIV0PNn2DGoHKxKmBlLU9m13XA9ig/57Wy6 B8IN35RNtiKrEwYv8cyt+CiU8+sZxZMt3GwCopTn3GSM1APexqUgzZO2l qw54rmx0KPzvS2j4vvZ45vifsIGFfrbb2h4guPlfLQ+PebLAIKQ1a6LVU Fg5JRDKSOfFQyu6TB+iWkeXCqdzOBNRz9ujqys/1jXbl3uIA3ttm+ab/C Pr0zHZyQBnpcPopJuY42/Ct6RYEiZwJc5oO9/4mIHFe0RNcXgK05ysi6G vIpjqlpgh3Z4LzNN9BOMMhUVFGwyZLPrDraJf8uGMSP2yHmFS6GzVO9Z2 Q==; X-CSE-ConnectionGUID: bSwQb52TRFGtx2KyqkMfeg== X-CSE-MsgGUID: kJcWo0FjS5eIKL+p259m2Q== X-IronPort-AV: E=McAfee;i="6700,10204,11372"; a="43173531" X-IronPort-AV: E=Sophos;i="6.14,244,1736841600"; d="scan'208";a="43173531" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 07:24:00 -0700 X-CSE-ConnectionGUID: QyeUm5j9ScGBX6OqHrYN1A== X-CSE-MsgGUID: voJxlvFeQKuZRkp8hdJhaQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,244,1736841600"; d="scan'208";a="126027318" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.195]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 07:23:56 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, Guenter Roeck , Lukas Wunner , Mika Westerberg , "Rafael J. Wysocki" , Rajat Jain , Joel Mathew Thomas , linux-kernel@vger.kernel.org Cc: Jonathan Cameron , =?utf-8?q?Ilpo_J=C3=A4rv?= =?utf-8?q?inen?= , stable@vger.kernel.org Subject: [PATCH 1/4] PCI/hotplug: Disable HPIE over reset Date: Thu, 13 Mar 2025 16:23:30 +0200 Message-Id: <20250313142333.5792-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250313142333.5792-1-ilpo.jarvinen@linux.intel.com> References: <20250313142333.5792-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 pciehp_reset_slot() disables PDCE (Presence Detect Changed Enable) and DLLSCE (Data Link Layer State Changed Enable) for the duration of reset and clears the related status bits PDC and DLLSC from the Slot Status register after the reset to avoid hotplug incorrectly assuming the card was removed. However, hotplug shares interrupt with PME and BW notifications both of which can make pciehp_isr() to run despite PDCE and DLLSCE bits being off. pciehp_isr() then picks PDC or DLLSC bits from the Slot Status register due to the events that occur during reset and caches them into ->pending_events. Later, the IRQ thread in pciehp_ist() will process the ->pending_events and will assume the Link went Down due to a card change (in pciehp_handle_presence_or_link_change()). Change pciehp_reset_slot() to also clear HPIE (Hot-Plug Interrupt Enable) as pciehp_isr() will first check HPIE to see if the interrupt is not for it. Then synchronize with the IRQ handling to ensure no events are pending, before invoking the reset. Similarly, if the poll mode is in use, park the poll thread over the duration of the reset to stop handling events. In order to not race irq_syncronize()/kthread_{,un}park() with the irq / poll_thread freeing from pciehp_remove(), take reset_lock in pciehp_free_irq() and check the irq / poll_thread variable validity in pciehp_reset_slot(). Fixes: 06a8d89af551 ("PCI: pciehp: Disable link notification across slot reset") Fixes: 720d6a671a6e ("PCI: pciehp: Do not handle events if interrupts are masked") Closes: https://bugzilla.kernel.org/show_bug.cgi?id=219765 Suggested-by: Lukas Wunner Signed-off-by: Ilpo Järvinen Cc: stable@vger.kernel.org --- drivers/pci/hotplug/pciehp_hpc.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index bb5a8d9f03ad..c487e274b282 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -77,10 +77,15 @@ static inline int pciehp_request_irq(struct controller *ctrl) static inline void pciehp_free_irq(struct controller *ctrl) { - if (pciehp_poll_mode) + down_read_nested(&ctrl->reset_lock, ctrl->depth); + if (pciehp_poll_mode) { kthread_stop(ctrl->poll_thread); - else + ctrl->poll_thread = NULL; + } else { free_irq(ctrl->pcie->irq, ctrl); + ctrl->pcie->irq = IRQ_NOTCONNECTED; + } + up_read(&ctrl->reset_lock); } static int pcie_poll_cmd(struct controller *ctrl, int timeout) @@ -766,8 +771,9 @@ static int pciehp_poll(void *data) while (!kthread_should_stop()) { /* poll for interrupt events or user requests */ - while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD || - atomic_read(&ctrl->pending_events)) + while (!kthread_should_park() && + (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD || + atomic_read(&ctrl->pending_events))) pciehp_ist(IRQ_NOTCONNECTED, ctrl); if (pciehp_poll_time <= 0 || pciehp_poll_time > 60) @@ -907,6 +913,8 @@ int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe) down_write_nested(&ctrl->reset_lock, ctrl->depth); + if (!pciehp_poll_mode) + ctrl_mask |= PCI_EXP_SLTCTL_HPIE; if (!ATTN_BUTTN(ctrl)) { ctrl_mask |= PCI_EXP_SLTCTL_PDCE; stat_mask |= PCI_EXP_SLTSTA_PDC; @@ -918,9 +926,21 @@ int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe) ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); + /* Make sure HPIE is no longer seen by the interrupt handler. */ + if (pciehp_poll_mode) { + if (ctrl->poll_thread) + kthread_park(ctrl->poll_thread); + } else { + if (ctrl->pcie->irq != IRQ_NOTCONNECTED) + synchronize_irq(ctrl->pcie->irq); + } + rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port); pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); + if (pciehp_poll_mode && ctrl->poll_thread) + kthread_unpark(ctrl->poll_thread); + pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask); ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); From patchwork Thu Mar 13 14:23:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 14015177 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 704F1267B9A; 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X-CSE-ConnectionGUID: s8eEGxRWQuSreRXEBe2wZg== X-CSE-MsgGUID: dD6n79AYTo6B8td4XfSyMA== X-IronPort-AV: E=McAfee;i="6700,10204,11372"; a="43173562" X-IronPort-AV: E=Sophos;i="6.14,244,1736841600"; d="scan'208";a="43173562" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 07:24:10 -0700 X-CSE-ConnectionGUID: 2WqtBt/zR6mt+8n4R/qu2w== X-CSE-MsgGUID: rQcfhDgWSsipDlTGBKLqIg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,244,1736841600"; d="scan'208";a="126027390" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.195]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 07:24:06 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, Guenter Roeck , Lukas Wunner , Mika Westerberg , "Rafael J. Wysocki" , Rajat Jain , Joel Mathew Thomas , linux-kernel@vger.kernel.org Cc: Jonathan Cameron , =?utf-8?q?Ilpo_J=C3=A4rv?= =?utf-8?q?inen?= Subject: [PATCH 2/4] PCI/hotplug: Clearing HPIE for the duration of reset is enough Date: Thu, 13 Mar 2025 16:23:31 +0200 Message-Id: <20250313142333.5792-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250313142333.5792-1-ilpo.jarvinen@linux.intel.com> References: <20250313142333.5792-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The previous change cleared HPIE (Hot-Plug Interrupt Enable) in pciehp_reset_slot(). Clearing HPIE should be enough to synchronize with the interrupt and event handling so that clearing PDCE (Presence Detect Changed Enable) and DLLSCE (Data Link Layer State Changed Enable) is not necessary. However, the commit be54ea5330d ("PCI: pciehp: Disable Data Link Layer State Changed event on suspend") found out that under some circumstances, clearing also DLLSCE is necessary. While this is logically part of the previous change, remove PDCE and DLLSCE clearing in now separately to allow bisect pinpoint it better if removing their clearing causes some issues. Suggested-by: Lukas Wunner Signed-off-by: Ilpo Järvinen --- drivers/pci/hotplug/pciehp_hpc.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index c487e274b282..634cf5004f76 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -915,11 +915,8 @@ int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe) if (!pciehp_poll_mode) ctrl_mask |= PCI_EXP_SLTCTL_HPIE; - if (!ATTN_BUTTN(ctrl)) { - ctrl_mask |= PCI_EXP_SLTCTL_PDCE; + if (!ATTN_BUTTN(ctrl)) stat_mask |= PCI_EXP_SLTSTA_PDC; - } - ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; stat_mask |= PCI_EXP_SLTSTA_DLLSC; pcie_write_cmd(ctrl, 0, ctrl_mask); From patchwork Thu Mar 13 14:23:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 14015178 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC1C2267F77; Thu, 13 Mar 2025 14:24:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741875863; cv=none; b=QaD8JhmOoSkFkpnfFNIEF1A8LdN/IhwumYBTkVCvy5jNRLauvWcXc7K1ijJPpeQ+0rIE3k2raeP86wX27mOakjoSOAlWo4swItvzfTQqFuZfCAVI3Zts3mc8Xn1OOHsiT9GqYgywCZ+K8V1BcnpSXeUMktGz8j9FXvkCAQgVmfM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741875863; c=relaxed/simple; bh=I8Al09f7wcLXoD3DPF6GNanA8tygpSAjedUh2Nvo+JA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=jPkXZiRwOTuKZo4U7P/4d0hViZw6mirBGjMnQeVqq7elhfXL7yj/+ewMimYo/1Rwpuz5zDBSWbRYNn1Zd2OGQDIA1h4xWtmCxuV7q1zqU0fm8FjyS7xnqXlK7+t89mUUAN1ebHa1oA5nmxgte3rx/yYQkag5SouZMmaUIRI+6/w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=l+YuMV1c; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="l+YuMV1c" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741875862; x=1773411862; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I8Al09f7wcLXoD3DPF6GNanA8tygpSAjedUh2Nvo+JA=; b=l+YuMV1cRS16rsPakFdTux0t/mkF5w7H9rbVRNQzIKoaE0zp/sdVLZ5X oq+tplm8BV3Z68Qeq1WPWwW53ezkukXnFTdVzP/UY7Gt6SBhkpf2ECCUI pM1Q+qRmAT0IHn8am3BwnVqBwxB0uxBVjfc8NVMLZ3lkmFo3J08QbV4lJ Jfj9BO5ZrjnBjUNmJ5flM2/+mkbCHaWOR7A/sGvDddjRqKwhM4vWzooJH KMEZPeUUmK4x8SWDfTfOJ4WXRIGaFrMnR0Ez7oyoylQ+8Oeif/E8z+sHI npYI45NrKYLnvC++PPEw2AV1BBhpKlPy9rrg/A2+Neon7tizWqVG/ek19 A==; X-CSE-ConnectionGUID: i4X+S54WTF6hH6faokuRKg== X-CSE-MsgGUID: WAiuR62gR+uk72EVlkOB2g== X-IronPort-AV: E=McAfee;i="6700,10204,11372"; a="43173604" X-IronPort-AV: E=Sophos;i="6.14,244,1736841600"; d="scan'208";a="43173604" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 07:24:22 -0700 X-CSE-ConnectionGUID: HlD4va/lQkeubo96Tc+Qcg== X-CSE-MsgGUID: kEFraZpzQpCWHZEyI0+KGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,244,1736841600"; d="scan'208";a="126027444" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.195]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 07:24:18 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, Guenter Roeck , Lukas Wunner , Mika Westerberg , "Rafael J. Wysocki" , Rajat Jain , Joel Mathew Thomas , linux-kernel@vger.kernel.org Cc: Jonathan Cameron , =?utf-8?q?Ilpo_J=C3=A4rv?= =?utf-8?q?inen?= Subject: [PATCH 3/4] PCI/hotplug: reset_lock is not required synchronizing with irq thread Date: Thu, 13 Mar 2025 16:23:32 +0200 Message-Id: <20250313142333.5792-4-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250313142333.5792-1-ilpo.jarvinen@linux.intel.com> References: <20250313142333.5792-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Disabling HPIE (Hot-Plug Interrupt Enable) and synchronizing with irq handling in pciehp_reset_slot() is enough to ensure no pending events are processed during the slot reset. Thus, there is no need to take reset_lock in the IRQ thread. Suggested-by: Lukas Wunner Signed-off-by: Ilpo Järvinen --- drivers/pci/hotplug/pciehp_hpc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 634cf5004f76..26150a6b48f4 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -748,12 +748,10 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id) * Disable requests have higher priority than Presence Detect Changed * or Data Link Layer State Changed events. */ - down_read_nested(&ctrl->reset_lock, ctrl->depth); if (events & DISABLE_SLOT) pciehp_handle_disable_request(ctrl); else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC)) pciehp_handle_presence_or_link_change(ctrl, events); - up_read(&ctrl->reset_lock); ret = IRQ_HANDLED; out: From patchwork Thu Mar 13 14:23:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 14015179 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E475267F50; Thu, 13 Mar 2025 14:24:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741875873; cv=none; b=k2Zu2T1biXMBdzuJiGFWp35Dk76spmLHDTLk233lPEB+QR1nH72LG23eZEwSak9j/mJD51paO/5N/eO5Yc3dDbElVgxbxOKQe5PWyIjdwc1HNWQgaFRnuEasAASO8GRb215nC2kDIkondoOj9LcohAMP6IjZ2j3RVtWfG9/kMXU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741875873; c=relaxed/simple; bh=0FxnfcYBhT+cVr2BAwoxmIHH0W1Uu+mQyjkUQszWQkE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=u8fUDQm2p5dT/0Qw/mrjSXvvDQFmbrNr8QMLxKiBsqRKxOyftdUPepmPKPD84vyUrY8NrEmF8yLRMgYMK4rXA0UR+iLdvpVrOWm9Snmsfl+EwRLZJFwJS2J9Hf8ZSiaxTMoBbPqP84yc580PbgALhv4qpFva28zY0vXkvoHTrGM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XtMBj6Fw; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XtMBj6Fw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741875873; x=1773411873; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0FxnfcYBhT+cVr2BAwoxmIHH0W1Uu+mQyjkUQszWQkE=; b=XtMBj6FwzLBJmzia9DlorgYCdrkGdhEp5aOL4fltbIGDdpX3G6RyCuRk TA+xxhY1/PmtrPlf0BSL0r8jZQIXeTWZ+a5/2GOuW1wY6LjsucEq0EBt3 HznpuYnrXQvWtvKipk70DAp5StyOdxjqLPfvwReotlCCSHkv1yuV5xaXr jvuhOrcAbEHNVTDZMQX4Z8VCA0TZStUMB+zcKLlpxCwtJuDTZa05uN6Hp b0j4WcByB1McPkZfs3QPFp7YVIzZJrdi0mIUANgbXT4PswRD8tDL2ewlb 3VU3OwXsaxmHiKCHKSOzWhh2Zz/T3rp54PQ6pM0dhgkCaa0Ps6H8FGOTE Q==; X-CSE-ConnectionGUID: 5NP5LecaSgafuDpTu9wXNw== X-CSE-MsgGUID: RUJolReCSBu2QfPQGdJUcw== X-IronPort-AV: E=McAfee;i="6700,10204,11372"; a="43173625" X-IronPort-AV: E=Sophos;i="6.14,244,1736841600"; d="scan'208";a="43173625" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 07:24:32 -0700 X-CSE-ConnectionGUID: JkwN5/auRf+iKsiHt2VPRw== X-CSE-MsgGUID: pRVvhwE5T9Sw8DRNhlwXCQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,244,1736841600"; d="scan'208";a="126027481" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.195]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 07:24:27 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, Guenter Roeck , Lukas Wunner , Mika Westerberg , "Rafael J. Wysocki" , Rajat Jain , Joel Mathew Thomas , linux-kernel@vger.kernel.org Cc: Jonathan Cameron , =?utf-8?q?Ilpo_J=C3=A4rv?= =?utf-8?q?inen?= Subject: [PATCH 4/4] PCI/hotplug: Don't enabled HPIE in poll mode Date: Thu, 13 Mar 2025 16:23:33 +0200 Message-Id: <20250313142333.5792-5-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250313142333.5792-1-ilpo.jarvinen@linux.intel.com> References: <20250313142333.5792-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 PCIe hotplug can operate in poll mode without interrupt handlers using a polling kthread only. The commit eb34da60edee ("PCI: pciehp: Disable hotplug interrupt during suspend") failed to consider that and enables HPIE (Hot-Plug Interrupt Enable) unconditionally when resuming the Port. Only set HPIE if non-poll mode is in use. This makes pcie_enable_interrupt() match how pcie_enable_notification() already handles HPIE. Fixes: eb34da60edee ("PCI: pciehp: Disable hotplug interrupt during suspend") Signed-off-by: Ilpo Järvinen --- drivers/pci/hotplug/pciehp_hpc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 26150a6b48f4..7e1ed179c7f3 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -846,7 +846,9 @@ void pcie_enable_interrupt(struct controller *ctrl) { u16 mask; - mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; + mask = PCI_EXP_SLTCTL_DLLSCE; + if (!pciehp_poll_mode) + mask |= PCI_EXP_SLTCTL_HPIE; pcie_write_cmd(ctrl, mask, mask); }