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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v2 1/4] xen/arm32: Initialize MM specific registers in enable_mmu Date: Thu, 13 Mar 2025 18:28:47 +0000 Message-ID: <20250313182850.1527052-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250313182850.1527052-1-ayan.kumar.halder@amd.com> References: <20250313182850.1527052-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DA:EE_|SJ1PR12MB6194:EE_ X-MS-Office365-Filtering-Correlation-Id: a435c073-413a-489d-e89e-08dd625cf1b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: we/x794P0YQhA8B+jYNq25pBXZH/D7W9ng//JvL6nf8TKPtM1nbMnT1n2bOFX9RQqn3dAWE2QhFB8guSYDBELICyoGaOLSaIksL4Nt9zIiBxQby5dEfHw1JERep8YphxYWjQB24W96gKWUdxUsKC62TJmAWrrqMUq1zcF7M4R3R1pJLX5e/KO39Ro15awqEDhP7FLcdHof9dwr15MaoBXXZlWIABnRTpKDPX3+dRb/+HwDBcVw5JB2RIAyIMOZL0tqkABEZd6M0ouDB8xyja0ZzxT+QstCjTQRgFdJkig9tEHzChEmZDsEwJbAY3NTZ2L89yNZ0pzOGlvEceyo9a9mJUTuR6Rr5VCOY+F8/MJzNcZ6Rv+e8OYQd6agOMjKBqbRB+sPv8r3/pkLbohx+zDodIASkHC3wn7a8v7D8tPO93Wgbxlo1/cbJLKXPo7nplAovixzLDA7GoBdDiar2oN8QhjyQwfI6RBHHPgx5qAACNdol5yUm+X12kHWSxTTXP2kIF89SuTCH9QNhkEjOWV7kMpno20BeFoP0VGYiGTYVv5bK/kYjXz2Wf2byNyOE3BDJbSZFEoQbrWtE/KkE30IjdSDQvmDQJn7j4xUjn1H0lBeiAs/tY4M5QyEGJRtMnadL/XpMqcxog1kT5NtJe7clYa+OskbsAj0lUQQ28ja14r1bUjJ1zh+vJOO+09loZaZlbyJdjvKVJ5ooJ0QMJ12IP0zfPl+w++UfxRSqncy0GieqirHyg9TT0xZ0KOwC5/3yP/HpnANkWVATzczcTHWQg7cAgnDCQQhyo9pdkXbvlnUuvEvZgyBBb/QDAEw95kXFo1C7GP+PCBd3mG2Iql3LL5CQf0+4fmFpjXp6+Q0d4geaBGumy7ACekYvLIJwcsPfzDz9td/WWV2UPq2erSGD+mJlwW5+tjyyYZIziMsKaGYkUUSSijMkeY+PpupXQKz++Z2QmuZxRfykms0VyZ0yN31eG680y3jojVVCj+Jtv+en+mcvSfoSLwp84KMCwiiUAvyug7KMQDc/HxMx0ugugfrUsPU5JP8XjqeTkm/LBoAZZRFKOfYjqMXv5n0/Gto6y90qVfW4a5Zc5uwOUwWeTYk5jJY2ySsL8/0SxbOKZfaIJbvY1z6aj/Df+IXVJznMlNRt+Ax48SpjAS3gr1yXzDEjiGNdHkerrzPkFazFQGGdvRN0r4IDspkFVCW/ie54k2BmbwBhWzBqMym2e5+EK+bKUynacM0ornceiBg/NRiAV7HDfLMnT/yTqbCStLTEXNVf01fJKsLw9V+0Izc6EEjwphjc9i8tVh/r4OY/SxA1ex7h/RCQI+afC7s6B01X+r0U0YBJmdePtQuihpEl9Y6U7oylH/nHUJ+yX6iZAD9LAx4KJkUNblSVZpI4fWVHtfST8kYp/YLsfY4RaWa8hVBp0dE7Xd+wnf2A9NtsjdgEE2DcnGdqxIKA+luck3yim+Xf6j7Qfv0vGF/SSgQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2025 18:29:08.6947 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a435c073-413a-489d-e89e-08dd625cf1b7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6194 All the memory management specific registers are initialized in enable_mmu. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - HTCR and HMAIR{0,1} are not set together with the other memory management registers in enable_mmu() Similar changes are to be done in arm64 as well. I prefer to do that in a separate patch so that all the arm32 changes are kept together in this series. xen/arch/arm/arm32/head.S | 14 -------------- xen/arch/arm/arm32/mmu/head.S | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 4ff5c220bc..50da179f81 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -218,20 +218,6 @@ cpu_init: add pc, r1, r10 /* Call paddr(init func) */ cpu_init_done: - /* Set up memory attribute type tables */ - mov_w r0, MAIR0VAL - mov_w r1, MAIR1VAL - mcr CP32(r0, HMAIR0) - mcr CP32(r1, HMAIR1) - - /* - * Set up the HTCR: - * PT walks use Inner-Shareable accesses, - * PT walks are write-back, write-allocate in both cache levels, - * Full 32-bit address space goes through this table. - */ - mov_w r0, (TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) - mcr CP32(r0, HTCR) mov_w r0, HSCTLR_SET mcr CP32(r0, HSCTLR) diff --git a/xen/arch/arm/arm32/mmu/head.S b/xen/arch/arm/arm32/mmu/head.S index 1e2bbf0c82..8fa74bd556 100644 --- a/xen/arch/arm/arm32/mmu/head.S +++ b/xen/arch/arm/arm32/mmu/head.S @@ -279,6 +279,21 @@ ENDPROC(create_page_tables) enable_mmu: PRINT("- Turning on paging -\r\n") + /* Set up memory attribute type tables */ + mov_w r0, MAIR0VAL + mov_w r1, MAIR1VAL + mcr CP32(r0, HMAIR0) + mcr CP32(r1, HMAIR1) + + /* + * Set up the HTCR: + * PT walks use Inner-Shareable accesses, + * PT walks are write-back, write-allocate in both cache levels, + * Full 32-bit address space goes through this table. + */ + mov_w r0, (TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) + mcr CP32(r0, HTCR) + /* * The state of the TLBs is unknown before turning on the MMU. * Flush them to avoid stale one. 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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v2 2/4] xen/arm32: mpu: Create boot-time MPU protection regions Date: Thu, 13 Mar 2025 18:28:48 +0000 Message-ID: <20250313182850.1527052-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250313182850.1527052-1-ayan.kumar.halder@amd.com> References: <20250313182850.1527052-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DB:EE_|MN6PR12MB8567:EE_ X-MS-Office365-Filtering-Correlation-Id: 4c82c922-23ca-4a85-c943-08dd625cf7c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: 9OzXtZ8yXP8uabH/weyYxeeRRy00s1l4u6pfj38FapK+QhVsO88DPwEAtLE86t73iA2TcA4jX31HB5HZJacimYGDTGi2mkj0/vuh9QbBWos4JjasR02CxLw9suj6/ViYeHPogVb0okc/vyKEXl6dtA/WEfwI/drSnF08Ai0BevhVTEykY0SDsxve80zUF2r6q9rEhN3+OdZWVcSOB5sYDg7e1F2dv+yz3YTEibzW1He6J7x9Qf4UpEvODKfZY52+w9JnOhK6LSb9wtos/2CF2jVO1h6W9QTiaP5rJuHz/6XMHd8W2S2AGywvjPvYOQyNF8IrYEnNkOwhU4I2bfrhR6H+1zN+JllnoE+SxWd1RWOsfU6hdvhXojo7khiCj434+PoeXjeAGfTITvdFFeZozk1fhDRl9E/gps8rqAtoUtoSdWeFlWWhXZV/VRr4aTro2m62jRSUO/Ll8UJgPGVaMIy5G1en7xtbsklLfW/cBFN5y2t6Ta9txPZ5cozGwRn7RUEDJTXUVgiKCBYW/mypNVIuSgdTf1YvgbCFsN0wyi37xkV4fmoWSDNji56skhEojlArUO0qjc+fa6sEpoa5G+34YojAnp0GFqX3IkeJBiq+974vRh2p2MsVPiLBDDpKc6cXmrGovDWKUEgdB0TTqhinqNNC18pG+EbNVo7eWi3JEI+3HJUTuEXCYlziO/A2/NY1iTAAmkZs/wouQVk43E2QpB8nM49Xu412dXHLNtockh4YfOOhrR7FKopVbHSp/W6moiMnW/dij4HLRVQoH2XqIxS0mq4G9u5mNx//opYfbQ1S5VYnRIaS1GygnztN6I4iELiKbkWgAtEZmsooAR0ba2+yAmOI1XLWzdjJLHvd6z+KjnwUNOV/hk91NZtnGjqZeHEuUSCUrsMchX3BGQbYj3QM63ycQt8/S4edFZukuVQH5v4xn3rd4lFFf/fKhr05RVtKZxtbliGg7yiFRO3rd2ATjGVKs+7iTic4TS1lYlrcXSuXSG/UF4c0cSumbdVPb/PCiMNKICr9P4XswE1hfV8qa0oSxYQdCExsUyhDVgVQY8J9BJDvQqTDoG4e3Tee1ugp+d/IW5sxmQBNcdRgznQTBIELun6fb8TLpktrHFfub1NgA4jnymXPE+oA3YmoXujDvyg0annIswR0/zAWNYbWxoK5Zs2IuzLeYlYQBw5h5x/m3RquSvfMTP93u2K/sjrQMc3dYusovFivXqyU0F1UX5nAQPs2IHEXKJket04LxVCt617eZCoAE/ONVBs11jD2Jkk32z0vXb6RXwV0fXKJYWdYkpeUGF6UzFShFmpi6BlyRiF0TbY6AxBhHV+sUepV+k51OpWXTuZ1+kB+SJj+IA8kqNJsCqlP51fDMkB2/rW4EstEAl5nGzBdqmVKDoM3ItPheyaCVa4QcfGFSGNf4WF4TQXDfRSP3i8y8QCKCSowNdAc24BXno2rUGbTWo5EPsJzn++GbxES0g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2025 18:29:18.8429 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c82c922-23ca-4a85-c943-08dd625cf7c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8567 Define enable_boot_cpu_mm() for the Armv8-R AArch32. Like boot-time page table in MMU system, we need a boot-time MPU protection region configuration in MPU system so Xen can fetch code and data from normal memory. To do this, Xen maps the following sections of the binary as separate regions (with permissions) :- 1. Text (Read only at EL2, execution is permitted) 2. RO data (Read only at EL2) 3. RO after init data and RW data (Read/Write at EL2) 4. Init Text (Read only at EL2, execution is permitted) 5. Init data and BSS (Read/Write at EL2) Before creating a region, we check if the count exceeds the number defined in MPUIR_EL2. If so, then the boot fails. Also we check if the region is empty or not. IOW, if the start and end address are same, we skip mapping the region. One needs to set up HMAIR0 and HMAIR1 registers in enable_mpu(). The register configurations are the same as in enable_mmu(). Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/mpu/Makefile | 1 + xen/arch/arm/arm32/mpu/head.S | 170 ++++++++++++++++++++++++++ xen/arch/arm/include/asm/cpregs.h | 4 + xen/arch/arm/include/asm/mpu/cpregs.h | 21 ++++ 5 files changed, 197 insertions(+) create mode 100644 xen/arch/arm/arm32/mpu/Makefile create mode 100644 xen/arch/arm/arm32/mpu/head.S create mode 100644 xen/arch/arm/include/asm/mpu/cpregs.h diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 40a2b4803f..537969d753 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -1,5 +1,6 @@ obj-y += lib/ obj-$(CONFIG_MMU) += mmu/ +obj-$(CONFIG_MPU) += mpu/ obj-$(CONFIG_EARLY_PRINTK) += debug.o obj-y += domctl.o diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makefile new file mode 100644 index 0000000000..3340058c08 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -0,0 +1 @@ +obj-y += head.o diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S new file mode 100644 index 0000000000..40648ce1a8 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/head.S @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include +#include +#include + +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + +#define REGION_TEXT_PRBAR 0x18 /* SH=11 AP=10 XN=0 */ +#define REGION_RO_PRBAR 0x1D /* SH=11 AP=10 XN=1 */ +#define REGION_DATA_PRBAR 0x19 /* SH=11 AP=00 XN=1 */ +#define REGION_DEVICE_PRBAR 0x11 /* SH=10 AP=00 XN=1 */ + +#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * sel: region selector + * base: reg storing base address + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be + * REGION_NORMAL_PRLAR + * + * Preserves \maxcount + * Output: + * \sel: Next available region selector index. + * Clobbers \base, \limit, \prbar, \prlar + * + * Note that all parameters using registers should be distinct. + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + mcr CP32(\sel, PRSELR_EL2) + isb + mcr CP32(\prbar, PRBAR_EL2) + mcr CP32(\prlar, PRLAR_EL2) + dsb sy + isb + + add \sel, \sel, #1 + +1: +.endm + +/* + * Failure caused due to insufficient MPU regions. + */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * Enable EL2 MPU and data cache + * If the Background region is enabled, then the MPU uses the default memory + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch32 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region here. + * + * Clobbers x0 + * + */ +FUNC_LOCAL(enable_mpu) + /* Set up memory attribute type tables */ + mov_w r0, MAIR0VAL + mov_w r1, MAIR1VAL + mcr CP32(r0, HMAIR0) + mcr CP32(r1, HMAIR1) + + mrc CP32(r0, HSCTLR) + bic r0, r0, #SCTLR_ELx_BR /* Disable Background region */ + orr r0, r0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr r0, r0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + mcr CP32(r0, HSCTLR) + isb + + ret +END(enable_mpu) + +/* + * Maps the various sections of Xen (decsribed in xen.lds.S) as different MPU + * regions. + * + * Clobbers r0 + * + */ + +FUNC(enable_boot_cpu_mm) + /* Get the number of regions specified in MPUIR_EL2 */ + mrc CP32(r5, MPUIR_EL2) + and r5, r5, #NUM_MPU_REGIONS_MASK + + /* x0: region sel */ + mov r0, #0 + + /* Xen text section. */ + ldr r1, =_stext + ldr r2, =_etext + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_TEXT_PRBAR + + /* Xen read-only data section. */ + ldr r1, =_srodata + ldr r2, =_erodata + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_RO_PRBAR + + /* Xen read-only after init and data section. (RW data) */ + ldr r1, =__ro_after_init_start + ldr r2, =__init_begin + prepare_xen_region r0, r1, r2, r3, r4, r5 + + /* Xen code section. */ + ldr r1, =__init_begin + ldr r2, =__init_data_begin + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_TEXT_PRBAR + + /* Xen data and BSS section. */ + ldr r1, =__init_data_begin + ldr r2, =__bss_end + prepare_xen_region r0, r1, r2, r3, r4, r5 + +#ifdef CONFIG_EARLY_PRINTK + /* Xen early UART section. */ + ldr r1, =CONFIG_EARLY_UART_BASE_ADDRESS + ldr r2, =(CONFIG_EARLY_UART_BASE_ADDRESS + CONFIG_EARLY_UART_SIZE) + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_DEVICE_PRBAR, attr_prlar=REGION_DEVICE_PRLAR +#endif + + b enable_mpu + ret +END(enable_boot_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index aec9e8f329..6019a2cbdd 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -1,6 +1,10 @@ #ifndef __ASM_ARM_CPREGS_H #define __ASM_ARM_CPREGS_H +#ifdef CONFIG_MPU +#include +#endif + /* * AArch32 Co-processor registers. * diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/asm/mpu/cpregs.h new file mode 100644 index 0000000000..bd17a8c75a --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_MPU_CPREGS_H +#define __ASM_ARM_MPU_CPREGS_H + +#define HMPUIR p15,4,c0,c0,4 + +/* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */ +#define HPRSELR p15,4,c6,c2,1 +#define PRBAR_EL2 p15,4,c6,c3,0 +#define PRLAR_EL2 p15,4,c6,c8,1 + +#define MPUIR_EL2 HMPUIR +#define PRSELR_EL2 HPRSELR + +#endif + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ From patchwork Thu Mar 13 18:28:49 2025 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Luca Fancellu Subject: [PATCH v2 3/4] xen/arm32: mpu: Implement a dummy enable_secondary_cpu_mm Date: Thu, 13 Mar 2025 18:28:49 +0000 Message-ID: <20250313182850.1527052-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250313182850.1527052-1-ayan.kumar.halder@amd.com> References: <20250313182850.1527052-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DA:EE_|DS0PR12MB8767:EE_ X-MS-Office365-Filtering-Correlation-Id: a76572db-4956-4f8c-7580-08dd625d0097 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: 5AaCStyoJ0dsOtfk417GouM3uAvNsbD3gG6gqR/6FtmCcbXIglXX6n1uXTV2DKth/OM74AHMGnpcdWlsbkF4UVJRCVhUhZ3AzGQOUoSLaK0sKpmV3SW8IxAKYSAI/aTs6AnT29ecrnVox+G96o2kUVFW6WZ2AMXH7AvyECTmZJlin5dr+TThVFHBMVM9izMwggM6piyWXkf3ybFOdMi75Y56IKQuUYV8nJRsfMCSZz5BZCW3qEZ+Z9yUiapdVa8G3fPSwzP8IUsF4urfndXOGJVkUgM3ZGXOewlaF9EYYnNp0tl13ICCJLK/v3dLD5QNiyKehL+wxnls5ZxL5XdQx6XMpJsgBK58JYRSc61FfryiQoTnPxFVjWF8UuGttwFYypaCJA7S1OIGHTxo85/jS5FaihxEi9PXNsHLdyqIjG9xKpgcP9BZyQvH1Ki/7jt6j65pkEUIVw6TIEbONsF/P/lQaMbBrec8BvsV6VegdhXj+C65a6vxHEVRMpd1ehs1FpSejt9PkeUqamgLNgx93uPjOKVJXIH8JmdjKe8OMZxhZuIMjYGF/ZV7vRa1YIEm1hSep5tpjC5hPu9GkuBd1cjT/EVFylOJIMpDV6wkWRTGQXEz5aor1sj0GI7iYBOeGI7Y0xjDkvF3uEwWepnWzTk0Tr9+cT4kndL5/UwQ68NThn7VLZmIzgwBr8bSSPkYYFcgSE3SqSJ7v9hM/UU126OfIOFgl23osfM7e6HKVynrdXlHpBOtM21N3dxxhGv+lBkYe1N8K17Imhgt73ISMVvzIbMTieGE0+DCvf8Y5nqYSGI4iRLPL+D1KsyH+bdNYILiLRSV0+vhAeAl8hZRi5rYHJyhC1ibjonAZaXCTMD4/AWHwmRYHj9K/eZK5MepfhFjkBo6rPROXQVJMtJ+EgNnjCrhJyveQr6B5NfFlGAkEe3EMP7ENKwxPNGW/G2TtAkqBqxwJLZXE2OB5oW7Q71qO3O+wIUFfDT8glmmpDsAqmYX1zAlKGCfSs2Ux2bEoK5NRn5mrE96ao9lSNJMRcop6Sw+xRBYMhYMGaaMQqezGPx629SYrH9bKqEawhqiSkePXcWQZEchBOgZuM/k8VPbyk+H9w0GB7kFMBhNRC4AluF3VJFweP0APOzW09WHenaB9aiZeCDrNvfEC/iNugmOnj3FJaR2D/3X3f1zKB66xZ3i7j40TDrp2ukF2AZpO5kLQJSdOpiefNpsu07bVPnClUM8hdzakq2Ria4wLAOKz2WCuQGVGccOKBYwR+5qfyVRzj0ysomXfjpxbtoxKFF65A0D2Nqa6vSRZnzgQOneSmqG04Mb1mGzQCPUP8N3pgRNS1mV0sA5M4LcFk3aSHo7/gd80WmYwiyunof4APxgfxqn3JWDgu5MLmtGrCKYE641ap+m8HsIvgujTUaIFsHK1XFyNdGrYRRfFNyhL+jnJfN/BhCfSC/eGiAn1tbfqiy1bv1I+FJNq7gpvhOq9A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2025 18:29:33.6478 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a76572db-4956-4f8c-7580-08dd625d0097 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8767 Secondary cpus initialization is not yet supported. Thus, we print an appropriate message and put the secondary cpus in WFE state. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu --- Changes from :- v1 - 1. Add R-b. xen/arch/arm/arm32/mpu/head.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S index 40648ce1a8..b6d31701f2 100644 --- a/xen/arch/arm/arm32/mpu/head.S +++ b/xen/arch/arm/arm32/mpu/head.S @@ -162,6 +162,16 @@ FUNC(enable_boot_cpu_mm) ret END(enable_boot_cpu_mm) +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper to + * please the common code. + */ +ENTRY(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +ENDPROC(enable_secondary_cpu_mm) + /* * Local variables: * mode: ASM From patchwork Thu Mar 13 18:28:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 14015764 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF8ABC282DE for ; Thu, 13 Mar 2025 18:33:11 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.913347.1319422 (Exim 4.92) (envelope-from ) id 1tsnMe-0004ir-MU; Thu, 13 Mar 2025 18:33:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 913347.1319422; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2025 18:29:37.8391 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 19adf3b3-6ce8-4672-ff16-08dd625d0316 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7900 From: Michal Orzel ArmV8-R AArch32 does not support LPAE. The reason being PMSAv8-32 supports 32-bit physical address only. Signed-off-by: Michal Orzel Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. New patch. xen/arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 89c099ff46..b413e8399b 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -58,7 +58,7 @@ config ARM_PA_BITS_32 config ARM_PA_BITS_40 bool "40-bit" - depends on ARM_32 + depends on ARM_32 && !MPU endchoice config PADDR_BITS