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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn CC: Gal Pressman , Mark Bloch , "Moshe Shemesh" , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , "Jonathan Corbet" , , , , , Yael Chemla Subject: [PATCH net-next 1/4] net/mlx5e: Ensure each counter group uses its PCAM bit Date: Thu, 13 Mar 2025 21:24:43 +0200 Message-ID: <1741893886-188294-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1741893886-188294-1-git-send-email-tariqt@nvidia.com> References: <1741893886-188294-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E0:EE_|DM3PR12MB9415:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f5ac050-1b59-4ea9-bca9-08dd6264da3d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: mErlW0cJnO6AKlwIOE4JU1uO6mdQ4YiD9nmkaOnF6clBCz70E6F0+E+6BjKCuR1N7ji3tbYilbcXyD+t42y2LadpevFZgWRSCoa9pqW4+Hsez3EhAqNvolZLjFdaA2EGR/gi1RN+RwrLp1x4zvoCLxMi4zWsKIqO3yanysHNfZCpSXc/QtP1mWrrhmNn/k0JM23BP4o8TVWx+rN1fgrjZrHg1hBdlKepQHfCbUH5UP7t/gK8ezFe0KDD2Gsrt747egsFFdA4vZsS1fHc/PdEF+KlIGC1SI7+BPBU+pcLvyCt3A09iB0o5wj+yObEK0GHXONKYPlQUPMo4S7vEYsWn1p4HQDtkB7k0KwhT028XXKR1d5FmVFNx5t6tqJbGkwU4OvBXxs1ckbGfc/n7I+FfSYFuq08V2Qhr0ETh8/VjDsH25zWi1Eg6C4mtRGfIeOEvHqpp2xRO1QkaJMEEE0yRagAUpTdprM7rxgA7OlCStBTQlWnDQ5HKyODlwC6TfpJPA8LRwZz3jEebXEBkUTj9n2/ZuleG7qDTqA0VTrdIGrSIEFnMLPAciLmANtxSh+LYMVzYwXo4/agbjbqC7NmakbRV+REuaGuIDmJhtCgMFCmDIZcdxTZs+fncpp1lHN2of5mQuC+njS2g8uRHRik8sZyBUYvO/DC4xEyTMAwCORdxVLu6eYHyQiaB+C3i+cf3XROhrarqYTd4XC1HJgoBU2GVCMpGDs+QYpwzX7YggRm01y43Kg9fEgm4YuriWQSCqRoDZ2pYsYtTv88viR69PFg1fKIAEgvxAKEHkCGT/l8eS3rG1ugjNd8s8fKOunD1/Pu6PJrZrs2i1QVxXPW/6JmY29KzWegzl3hl7kuBR1mx6djbdPFb51EI8IMRcRKpnYl6zQQot6nN+UccNbBV9+nixUhSVL8Jx3/XK51++bTtspcWX4UJykn659HdbN60JODv3O3tFRR5+KxH22oSAlrI7GiVth1m2dLlkyrmY5XViE3oqIZEZ9NX/ofdwsM3kxo8qamHOAAbKfB7IEqhIsMdpyAhwgcW2Kv7HxRMDKesw6+npbRwPc0op89GGWm1aDReUWAI598uEVkc3OD2cTnWNFJEVoLIA7ikkIFL/jF4MRYqkx/zHAplX8XI+yuC4UeUsiBqjeD0UDveEGmTpn952CA+GQJtsXorAuxcpJm1fftL63FYd2WE4qS21I+KJLlTccX47FvA7lAWCTWokAJEEVzCqDd0iPEX4y/hvJOukMCEVLfECLBoSbJtFYB8A009+PPBgX5hgJ0X9OaIpcMOdxobGZhqd22ED3zIcu0TKpiWuRX5nfOnmd9HhTr48uiPOIXQ7GBEyTzuNCUdredkrxi9QLlg0O6w54BDde/uJzO/LBJ6Z9F98145JExlCgxITS8k5XfeMG+TEMIIcPvL94bFaCeBsQLZ5w9ftloT/FOJba5b+gtJi4MKDgNn7bgo/o8x58hTtSwdTbbyQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2025 19:25:45.2177 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2f5ac050-1b59-4ea9-bca9-08dd6264da3d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9415 X-Patchwork-Delegate: kuba@kernel.org From: Yael Chemla The code was incorrectly relying on PCAM bit of ppcnt_statistical_group for accessing per_lane_error_counters. If ppcnt_statistical_group PCAM bit was not set, we would not read per_lane_error_counters, even when its PCAM bit is set. Given the existing device capabilities, it seems to cause no harm, so this change primarily serves as cleanup. Signed-off-by: Yael Chemla Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Kalesh AP --- .../ethernet/mellanox/mlx5/core/en_stats.c | 24 ++++++++----------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index 611ec4b6f370..77d34037b92b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -1272,11 +1272,9 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy) ethtool_puts(data, "link_down_events_phy"); - if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - return; - - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) - ethtool_puts(data, pport_phy_statistical_stats_desc[i].format); + if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) + for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) + ethtool_puts(data, pport_phy_statistical_stats_desc[i].format); if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++) @@ -1294,15 +1292,13 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) data, MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters, counter_set.phys_layer_cntrs.link_down_events)); - if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - return; - - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) - mlx5e_ethtool_put_stat( - data, - MLX5E_READ_CTR64_BE( - &priv->stats.pport.phy_statistical_counters, - pport_phy_statistical_stats_desc, i)); + if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) + for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) + mlx5e_ethtool_put_stat( + data, + MLX5E_READ_CTR64_BE( + &priv->stats.pport.phy_statistical_counters, + pport_phy_statistical_stats_desc, i)); if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++) From patchwork Thu Mar 13 19:24:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 14015834 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2060.outbound.protection.outlook.com [40.107.243.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFFAC1F1521; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn CC: Gal Pressman , Mark Bloch , "Moshe Shemesh" , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , "Jonathan Corbet" , , , , , Yael Chemla Subject: [PATCH net-next 2/4] net/mlx5e: Access PHY layer counter group as other counter groups Date: Thu, 13 Mar 2025 21:24:44 +0200 Message-ID: <1741893886-188294-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1741893886-188294-1-git-send-email-tariqt@nvidia.com> References: <1741893886-188294-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E60:EE_|SJ2PR12MB8182:EE_ X-MS-Office365-Filtering-Correlation-Id: 01982513-d16b-41c0-70f5-08dd6264dc5a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|1800799024|376014; X-Microsoft-Antispam-Message-Info: H7ts9AtK2/fs/rUSApFADOjl+xpSuxaFEzIb1EjWPLyD47ifOU+VdNxDSA8H0WbN1wDBioK1Vc5ojf3BRaeIGTwFRtDboiswHCSuFwJ7ZB37hROE+egOSIsGhz5LdMqSMnKkPSZvmgClO8qHTh25QZNA6LcjrClBEQdeo3BhiMR1Sv+Y7GzlyTqezKXRN6+6dvgaS6wIaTagZ+n8j9rvx2RgHiL1y85szayZXSR2hncd13r2BAuH2/RnlyeolrNajs/depWNJG1oV4OUolAW7OHZoqedr7Fw6zKTFqy42bY0wFrN7RDBPjX3JwH/tbIUqCvcHzVpSE5wfqFvWW+2ZIOrUWgfrplieP0J6qYcQ5lM5bq+xyu7R4Vaz+KJi9UGrdUV0Y18YMHRhsQ2aAnjj/oQNv/uhiqHPyWBMepYHkFYioYYtzBna+Sm42EWcIRu35JbZhoJ6dES7KZ5UbqkwMzaj59TA4rmIo0PeCXm2xkcSubZ8VNySS31vXfko5GmW7orCb8Q69mERU2ZXtKJ9lC5mPf9lB9ZAJaHNEZJXiyHO4Gnt2tIAiwL/D2e079qZmlr6NBMMfBhIsjpFZGlFZVQ6onjN1llIiHCi5fm43+aUgqctMHzM3ZwCl+vx8LPAjG7ufo6XI5qXa//P1eBHmgQRTShr3dXTlh46Vx6yG9DzQ/6wDNbDKihFLK5PxBDCplEi3ncTUWaIu2ZUs8zUOygDGHhI0coKipil5FUfKy0EwV512gLV6Ce5Bu2IZosqWdlGhuN3zeqift+cM/1N21Jmxvsxr4VMyUJeH7ig63kihCBD6xnW7bjy9pyqqh8hZ0PZawzRLzaSyVMXsa3riJqBgkV+WI9POClkfUQzAW4Y8+X0jnEa79tp32U6ku3MrE4b11oeYe+/gpReVAjxwrD3gzK3nD9lqa9FDdnd4A5O01llVWYlbV1+6LQfwygP0o5c/TbtdMEar3S/IP0REQDW9n7ytdykFgr6TyIB+XjSmohD4LUoMmR0P1yKmFU8xdQzPe50kkDLJcXoDNDCOrMGyeFmJweL9AExaHoDwPnr4OV8TRVfLvxyezHS3u8C+Y9Y6yNteFdFX+XAzFUGnWHKsD2+elLMzOCGsSI8VvJ8xTRan0yEwoxf3ZOjbNdQ0fmvOZvEe6CwQNBVLdIhT21CAdnc3GTqjdLS/SDTSlGULBhz0pXt+51TV9o4w0Fr4t4f0YF3bjDZnBrVEQbVnXvOFgOJgN+bbKTYASpkT+W8AyoGkQTCl8vuypAFHywetm8QE/n+1ItwL8dtDXg5CFrOtIFsBeUt8bRppQFDoAFjLLx9gcIDnzqZu+IZ4Nox49lES1oKEiyvT+8hQpmLen1dPR9twnOfWy41vZlyG/rfJ+ymVVqvGrcy5ukzgdoBS2dXqaT4/uZRQYQ1V8IcyfN2krz1512X/WRjk+OqaIXtEJSKLg5MYhxaTmZYA2OU0TgDSjXN6G9ecDANAmnwA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(7416014)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2025 19:25:48.7769 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01982513-d16b-41c0-70f5-08dd6264dc5a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E60.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8182 X-Patchwork-Delegate: kuba@kernel.org From: Yael Chemla Adjust the way physical layer counters group is accessed to match the generic method used for accessing other PPCNT counter groups. Signed-off-by: Yael Chemla Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_stats.c | 25 +++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index 77d34037b92b..0cf0c920532f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -1227,6 +1227,13 @@ void mlx5e_stats_ts_get(struct mlx5e_priv *priv, mutex_unlock(&priv->state_lock); } +#define PPORT_PHY_LAYER_OFF(c) \ + MLX5_BYTE_OFF(ppcnt_reg, \ + counter_set.phys_layer_cntrs.c) +static const struct counter_desc pport_phy_layer_cntrs_stats_desc[] = { + { "link_down_events_phy", PPORT_PHY_LAYER_OFF(link_down_events) } +}; + #define PPORT_PHY_STATISTICAL_OFF(c) \ MLX5_BYTE_OFF(ppcnt_reg, \ counter_set.phys_layer_statistical_cntrs.c##_high) @@ -1243,6 +1250,8 @@ pport_phy_statistical_err_lanes_stats_desc[] = { { "rx_err_lane_3_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane3) }, }; +#define NUM_PPORT_PHY_LAYER_COUNTERS \ + ARRAY_SIZE(pport_phy_layer_cntrs_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \ @@ -1253,8 +1262,7 @@ static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) struct mlx5_core_dev *mdev = priv->mdev; int num_stats; - /* "1" for link_down_events special counter */ - num_stats = 1; + num_stats = NUM_PPORT_PHY_LAYER_COUNTERS; num_stats += MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) ? NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0; @@ -1270,7 +1278,8 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy) struct mlx5_core_dev *mdev = priv->mdev; int i; - ethtool_puts(data, "link_down_events_phy"); + for (i = 0; i < NUM_PPORT_PHY_LAYER_COUNTERS; i++) + ethtool_puts(data, pport_phy_layer_cntrs_stats_desc[i].format); if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) @@ -1287,10 +1296,12 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) struct mlx5_core_dev *mdev = priv->mdev; int i; - /* link_down_events_phy has special handling since it is not stored in __be64 format */ - mlx5e_ethtool_put_stat( - data, MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters, - counter_set.phys_layer_cntrs.link_down_events)); + for (i = 0; i < NUM_PPORT_PHY_LAYER_COUNTERS; i++) + mlx5e_ethtool_put_stat( + data, + MLX5E_READ_CTR32_BE(&priv->stats.pport + .phy_counters, + pport_phy_layer_cntrs_stats_desc, i)); if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) for (i = 0; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn CC: Gal Pressman , Mark Bloch , "Moshe Shemesh" , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , "Jonathan Corbet" , , , , , Yael Chemla Subject: [PATCH net-next 3/4] net/mlx5e: Get counter group size by FW capability Date: Thu, 13 Mar 2025 21:24:45 +0200 Message-ID: <1741893886-188294-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1741893886-188294-1-git-send-email-tariqt@nvidia.com> References: <1741893886-188294-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E1:EE_|MN0PR12MB6248:EE_ X-MS-Office365-Filtering-Correlation-Id: 026ae6c9-0259-4091-8baa-08dd6264de09 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: zTc7to10CBFRt3aYDv0o1U/EuaPwBNiNFQqMp1disMxk5DTVl7flgFVAaZ8cxKLl23p96Kbls1JiKBk6QIMF81DVHgvf0bsbaPtvPhaE6ZoVuepuLfSVqNQYIL4ipTggbbd40DAXOhk2QDROqu/hi1IOs5CNVMEAJqEVKSpefnniTSaTurn1yj6wfq4gYBIWKYCyzKcG/I5b+KYR3febzDkCnYxnUQWkBwdIMGHAXOzsb3G+/gZSdSU25/FL6o7/OfgKlZRSaj12uT4hQEryFBtWCEzuz3Zn9sPNGra12kAb4EVOUhBaDoXcpxhK5KzlEEgkzRssZNs5ImL5p4pgh0xieO6nkrzoLLx+f20oicU3glqLLn87hIHXH+FeD5YYSopDYayUCwlq7YpqghEG9ArxHXpUgS/BcVRYeFDZ6grENCRbSuP2qskjdOEOUaARenb1AXksB8Co1MdvOf80A2LzQUkzUq0UhGBDxdsDpo2c8f2jWIerawD0cX/flBtNfJ+V/dq1MYUnqVbwYKYq0jiMs3lcT+bglylAHZ+fub5AvXQWoA1FJs4tnUMA34/kReBmGGw2O0vH+O6DsCiF/XxsXcgArExxnj5wrFDZ7CJ9E8Zr0wCTZn5N/4XYkP/J+7v/j6EfiLFoC0EfcBw/txPa83VmnnJpiAl1yQ41LBOIxhgpcDuKzQ27v+95u8SjKeRy2bf1xfIIWf4PY2lxGyWNdBoqAS/TDBD16VsBiAX9aXJUInIlkR6z104Y1NOazqxVCkbX30SQjxoCrTR3ibZ5BD7S8+4t1O8MomZb/k8/RhBtyRxGsNWGGp7mmnidLVeqzqwlPjxWR3ERi95vkxVIN3EOGf+1G7ckgKhFn50m3kd6DDmCTI55tOP6Am64m6HcXrqEz/eiRcdwenlCQddx/jvaFOr0hTH/AiFZVmXvKtA2q+nm7c44BAxlqTE/bBM4IxA3dvfqHT3itHr+nV20U87PR9kSszWfY2M7wMmCZhaNmmcwJADdURUMbHZs0RlJHEtZb1nxqbXJz3p4zxpbOSXmyRqj+yKuqGrepyvYD1XNWycnmmj27YwO2A7nkk/eP/VDhyM89LjpwEUIr0eDHgZVKkYTg29J/6OOcu9gRRGA7ZsF2Q03UbtgFX2tI2vUweKdDJovXvjieoDXIS4/xtzx9KA0HMQPRmokcuqS5qZ79NnIz9dDflQTdXWjyW8kOpBAIA/vV4iFbInbz1npP7XrgLMEKVIwEUCz/t3QMxZsMLwP/QRHiSvw+gl3hjOFOhNb5hvFRhCeGmUPaRu/T0yCOoNs5ydKRw4Dk7auphFDJrOv+yCYiUF2I7J7R1rER1kfT9bzCyQ9T+W7g0XPeHA3FSTZk5vGv8Zpy5alHcT8ln4y6PlNgLgmbgMdmk9RN41WwNgglVe5dUqv4lj1sPjAyo8gWgDpX5HkC2hbPviPxVO2YzaN77dGFo+iyAQ2AJftrRMK0RP6VaxqeA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2025 19:25:51.5866 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 026ae6c9-0259-4091-8baa-08dd6264de09 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6248 X-Patchwork-Delegate: kuba@kernel.org From: Yael Chemla Retrieve the number of fields supported by each PPCNT counter group based on the FW capability for this group. Signed-off-by: Yael Chemla Signed-off-by: Tariq Toukan Reviewed-by: Kalesh AP --- .../ethernet/mellanox/mlx5/core/en_stats.c | 58 ++++++++++--------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index 0cf0c920532f..a417962acfa9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -1257,6 +1257,13 @@ pport_phy_statistical_err_lanes_stats_desc[] = { #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_err_lanes_stats_desc) +#define NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(dev) \ + (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_statistical_group) ? \ + NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0) +#define NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(dev) \ + (MLX5_CAP_PCAM_FEATURE(dev, per_lane_error_counters) ? \ + NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0) + static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) { struct mlx5_core_dev *mdev = priv->mdev; @@ -1264,11 +1271,9 @@ static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) num_stats = NUM_PPORT_PHY_LAYER_COUNTERS; - num_stats += MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) ? - NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0; + num_stats += NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(mdev); - num_stats += MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters) ? - NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0; + num_stats += NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev); return num_stats; } @@ -1281,14 +1286,15 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy) for (i = 0; i < NUM_PPORT_PHY_LAYER_COUNTERS; i++) ethtool_puts(data, pport_phy_layer_cntrs_stats_desc[i].format); - if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) - ethtool_puts(data, pport_phy_statistical_stats_desc[i].format); + for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(mdev); i++) + ethtool_puts(data, pport_phy_statistical_stats_desc[i].format); - if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++) - ethtool_puts(data, - pport_phy_statistical_err_lanes_stats_desc[i].format); + for (i = 0; + i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev); + i++) + ethtool_puts(data, + pport_phy_statistical_err_lanes_stats_desc[i] + .format); } static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) @@ -1303,23 +1309,21 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) .phy_counters, pport_phy_layer_cntrs_stats_desc, i)); - if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) - mlx5e_ethtool_put_stat( - data, - MLX5E_READ_CTR64_BE( - &priv->stats.pport.phy_statistical_counters, - pport_phy_statistical_stats_desc, i)); + for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(mdev); i++) + mlx5e_ethtool_put_stat( + data, + MLX5E_READ_CTR64_BE( + &priv->stats.pport.phy_statistical_counters, + pport_phy_statistical_stats_desc, i)); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn CC: Gal Pressman , Mark Bloch , "Moshe Shemesh" , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , "Jonathan Corbet" , , , , , Yael Chemla Subject: [PATCH net-next 4/4] net/mlx5e: Expose port reset cycle recovery counter via ethtool Date: Thu, 13 Mar 2025 21:24:46 +0200 Message-ID: <1741893886-188294-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1741893886-188294-1-git-send-email-tariqt@nvidia.com> References: <1741893886-188294-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E60:EE_|DS7PR12MB6357:EE_ X-MS-Office365-Filtering-Correlation-Id: 974c9b4b-64bd-42cc-35fe-08dd6264e151 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: osbrk686ddROyn/SXl9D6MKumf5o9FJD82EtCK8WUKB+Ywuai4aVEdZ3EhsaEh67um2tEvfrSg4N1En0JQKixfa3/XeFfTRv+V+dI2gdCab5Ii/r//VOJCWwWTKCt3tHek9aOPLVK7+pXJZOIMxQ4hCTgHko/zSxOpatYwmFEdFD2Al9uff2PKpLyQrxO8BRcL6Hg3wBQH+8A5TU4rzm7wPTyLi6vQBM+aXmVIWaDDAAe10Wy9N5bNo6fxxrBveJ++FfL/coTEJY58kUDrMOSW2gTXRcU47NpHcbZ1OG88La6kSG/3KpLy3kLrd2ahELbzQL1yPTksOHUpLaEfsCLXq8tmkdKR9n4bwwBMq56Dqb9fEcgcyjtAadsxI3fAUXhWDzpVTBO2s7PFy95IYjPvEWXvWK61W+wZrcjnhpeN4z1t46wJwA61j6UoNnDXfttNgeMZmqVY7Pn0P+McSo97GNH5MiaP+NR7rmJxBqODBQEdY0XiNWO+wYPIMvwpb6uCTNuc+6sIHshMcvZWPPYSk4LTAXax39m5Y3IXVk5DHftz7I7OwWrXcnWyW7bi1cWYyRUKLjKYotELI+QVM4uqz8qBRLNEFjrjpwBCZbnpC/JAgE6jIuXt6apnbRtNAOw4JjjEL9aBAhbV37rP4DjlIjAqR0V59CTc5e6oJnaxHWYrq9II54WWbpnOSfgjCdKQNk8MWxwkotNcAKkxYxu8ZTWDLILDqmCCLyn2JdcbbocoUBHBDGI82TDFWJbBimTZFAHgn9lCjlUnYcS4jG5k+U3gZXAaNHx+FUeP+gab17r3To6tPeqQdU00G+ZU4KMT7/Q9xdGX80ie89nM5ndffdCs292Vhksrah10LqH3Sdtw1sI2beKkHEr3BJfN+8QHCer/mBQuAaT3EvDdKnBK01A6fBRR0u9mhoeo6f/TqIM4w4ujvwJwIhTCmDMI9h3a/ZZk1UoV+FEF1etUqCgvIBxoc6J9GJx/zif1V9yWIMTcaVXdCG6HFo1/kO8j6wwqAjLj7ADiYvpHTrYgiZhUBPzWFRp1619ayFDP4cW0dGS+YDc5npzhQtVPsBZQuQwb9M63V142cKItjVqlfCau+1aPrmu0e8nyaMxSESoByINACsbdKWZ5kfkZ+bbtVilhSThrPF4Fh2RjJl+Atv5Cmq1Xp6LEJfVOlxbeBGQiT7tguEKhTwkTT0nw7yOJDGzmbYpRmuwmeuvUKzOF0NBxUrwW5N1pI7M6A4iuDepgGs5t+V26m1+hguJUTyz9QElJn4Lu66qvppkrCIxk2xSQch/kBkY860an79yyPmT3oDL3JvOluBslssCoan3pKq5zgSYrpcgbvnPw2+rLSNCgkf3SGq/J4PzkXrxnfTFvsEBwQBhVkr+bRp4+ldARWMwjl0PtpeF8gxyr6wxHobT9VkucdNxMOj/RGMnymLr/POnXN4RplhHOUAoZBqNyqSDUCiCO94e/ry7KDgXbBhFg== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2025 19:25:57.0894 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 974c9b4b-64bd-42cc-35fe-08dd6264e151 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E60.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6357 X-Patchwork-Delegate: kuba@kernel.org From: Yael Chemla Display recovery event of PPCNT recovery counters group. Counts (per link) the number of total successful recovery events of any recovery types during port reset cycle. Signed-off-by: Yael Chemla Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/counters.rst | 5 +++ .../ethernet/mellanox/mlx5/core/en_stats.c | 44 ++++++++++++++++--- .../ethernet/mellanox/mlx5/core/en_stats.h | 4 ++ 3 files changed, 48 insertions(+), 5 deletions(-) diff --git a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst index 99d95be4d159..f9a1cf370b5a 100644 --- a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst +++ b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst @@ -1082,6 +1082,11 @@ like flow control, FEC and more. need to replace the cable/transceiver. - Error + * - `total_success_recovery_phy` + - The number of total successful recovery events of any type during + ports reset cycle. + - Error + * - `rx_out_of_buffer` - Number of times receive queue had no software buffers allocated for the adapter's incoming traffic. diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index a417962acfa9..acb00fd7efa4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -1250,12 +1250,22 @@ pport_phy_statistical_err_lanes_stats_desc[] = { { "rx_err_lane_3_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane3) }, }; +#define PPORT_PHY_RECOVERY_OFF(c) \ + MLX5_BYTE_OFF(ppcnt_reg, counter_set.phys_layer_recovery_cntrs.c) +static const struct counter_desc +pport_phy_recovery_cntrs_stats_desc[] = { + { "total_success_recovery_phy", + PPORT_PHY_RECOVERY_OFF(total_successful_recovery_events) } +}; + #define NUM_PPORT_PHY_LAYER_COUNTERS \ ARRAY_SIZE(pport_phy_layer_cntrs_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_err_lanes_stats_desc) +#define NUM_PPORT_PHY_RECOVERY_COUNTERS \ + ARRAY_SIZE(pport_phy_recovery_cntrs_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(dev) \ (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_statistical_group) ? \ @@ -1263,6 +1273,9 @@ pport_phy_statistical_err_lanes_stats_desc[] = { #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(dev) \ (MLX5_CAP_PCAM_FEATURE(dev, per_lane_error_counters) ? \ NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0) +#define NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(dev) \ + (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_recovery_counters) ? \ + NUM_PPORT_PHY_RECOVERY_COUNTERS : 0) static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) { @@ -1275,6 +1288,7 @@ static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) num_stats += NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev); + num_stats += NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); return num_stats; } @@ -1295,6 +1309,10 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy) ethtool_puts(data, pport_phy_statistical_err_lanes_stats_desc[i] .format); + + for (i = 0; i < NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); i++) + ethtool_puts(data, + pport_phy_recovery_cntrs_stats_desc[i].format); } static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) @@ -1324,6 +1342,13 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) MLX5E_READ_CTR64_BE( &priv->stats.pport.phy_statistical_counters, pport_phy_statistical_err_lanes_stats_desc, i)); + + for (i = 0; i < NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); i++) + mlx5e_ethtool_put_stat( + data, + MLX5E_READ_CTR32_BE( + &priv->stats.pport.phy_recovery_counters, + pport_phy_recovery_cntrs_stats_desc, i)); } static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy) @@ -1339,12 +1364,21 @@ static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy) MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); - if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - return; + if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) { + out = pstats->phy_statistical_counters; + MLX5_SET(ppcnt_reg, in, grp, + MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); + mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, + 0); + } - out = pstats->phy_statistical_counters; - MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); - mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); + if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_recovery_counters)) { + out = pstats->phy_recovery_counters; + MLX5_SET(ppcnt_reg, in, grp, + MLX5_PHYSICAL_LAYER_RECOVERY_GROUP); + mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, + 0); + } } void mlx5e_get_link_ext_stats(struct net_device *dev, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h index 5961c569cfe0..0d87947e348d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h @@ -309,6 +309,9 @@ struct mlx5e_vport_stats { #define PPORT_PHY_STATISTICAL_GET(pstats, c) \ MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \ counter_set.phys_layer_statistical_cntrs.c##_high) +#define PPORT_PHY_RECOVERY_GET(pstats, c) \ + MLX5_GET64(ppcnt_reg, (pstats)->phy_recovery_counters, \ + counter_set.phys_layer_recovery_cntrs.c) #define PPORT_PER_PRIO_GET(pstats, prio, c) \ MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \ counter_set.eth_per_prio_grp_data_layout.c##_high) @@ -324,6 +327,7 @@ struct mlx5e_pport_stats { __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; + __be64 phy_recovery_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];