From patchwork Thu Mar 13 21:43:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 14015935 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7508F1F4E30 for ; Thu, 13 Mar 2025 21:43:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741902201; cv=none; b=XUljJOQTbF4dvJcFrClLTZpJcuOWjXcppPmV7i06bxGupcNUzBD9VI7wBKXzkEZH8iEvTqmGQpT7osllQsthYqCSzt1G4+WHF3xTVDxhL24/pa4gWeeMJ6VLE7nxbZ8IsgRZE0P1fVwZAnP4AdrtSdhu7CJ2CRMnhD5QTKcYdzI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741902201; c=relaxed/simple; bh=NaZu91DC4T8heFZFo5XZ2syZfWhTaJWbyUNy8uixAT4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eWvRZyKkA/dG/P1zKwPvGBvKUmGIXy6JQbAE/AKCwLoowC9sUOuA4IvW0fxUJn8OvMUDdeB1Ubzt15Hx59+laZFRNtECiY/MPxsznXFxnFEdjmi2rJWs4p4408sTtkffopqJWaWq6l3akyUevIUjI+oaCeCX1Qq51y/EaZZjM8w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=b2OAtKlh; arc=none smtp.client-ip=209.85.218.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="b2OAtKlh" Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-ac2b10bea16so291060966b.0 for ; Thu, 13 Mar 2025 14:43:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741902197; x=1742506997; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=v+Au6V+nm5YKxU288WKh4NUBJU2SyJevP5UMvrIA5i8=; b=b2OAtKlhBW9xtV+GU2vRGF+mKQ5FDsaluza2OobOIxUn8H7em+qDlQiFNjU+ownvG7 ysrZUuJANLkUTWX8MWj8EWGM6y6LH4IT+q/OdVwhaiHv/gQWyABwymqLUwpCFx+RtjOd FpnlSiarc7d0JKBkvDSsOLk9dJZyXZPbs9hdC4p5YbptwgkdlNcYcEPwIw0zocNrw8LW 1C2vghifvLfBPRz7a9QWbDjx1PUsQmCjtPlgozIAbuBLeAns3ciSobTK7ibQ7qOnmpFp IC8uG2JDyNZfRyYLBJ6XZwxs2Ut/Fil1ZlNrsTAz9ltuoTK1OlaJXGJllZ+PX2Xs1Th9 RSRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741902197; x=1742506997; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v+Au6V+nm5YKxU288WKh4NUBJU2SyJevP5UMvrIA5i8=; b=cyuJBhzjCYZr7UqENRPu3fs/EBh+yyizE2lq38Xmfyb5oAt7dNnIBwmFpHOv7VJRVv PvBp7+yOxZ2z/yAYlRhhrIH3/8IR+A50jVwjB6Uop8Qx5J7ayMyr+tPxPDJQ1Ud/RoVW tjSXef3IkdZxOdnJQtC2pldwzsO2EEK5B76vsLRQ/QtrXD9tcY3FzyzX9xz87ru4gfmY 4wLTJbKuKDJTQWrsSHlwECNrKXC8BDMTyFLMXL2vhkJLxadBzLAPNSf+Xx630OR6mvlQ ORMKSvz5Ow3I/Y9DYa1u4RCq4nt9D+cTGncgnhDr+NLi1Mg5wq736L4A55Aj5uZ0D6sG le6w== X-Forwarded-Encrypted: i=1; AJvYcCWLOLpS3YHOzoYmuLc3e1plrXIFXoXeX0rkY59ImR/TBHXw2YQY+3EhIetI57CSkayxacTPTTv6mpA=@vger.kernel.org X-Gm-Message-State: AOJu0YzvcyTPYz8aqCEcZtdtkondND+vGO+l3sjv1meXNMg2ZAIX8xFr SOqQoloUyiXmLSG86GbdJmrLXse2MAncLtqXqx6O4hNCoJuJvdcZoDAqK93isnQ= X-Gm-Gg: ASbGncvFhNLM5xrIM1/tq3yV0Nm4QDnl6Oa4UqXMzOs1G7hFY0T/2za0BF1a4fCWYUl 4WU2MJKsdjVFevlOgSFlEImeV0hoFfDu0dhjQXTrJtisUnEQdq44pwzWUnvw0H0ADd/LPP4rOHu KCcXFU+CkPsWE4qZRrpUFigk5ynlyV9b+sa7qwY6op8ELa1oD3vmoOJLHz3tITDbDxnfgH+FY35 zQ51dmzvQAnTRf1HTn6Z3vN244EPi7kW4yHbagXtTvfhmlLH/rsad72VmpXAE7XRakA4q7hInOB LB224PyW0JOuVgSd2+QEohhpqAejJc1JbbM78IPp4YApEYpt3pWF8AZ49On3DEmVM61JOsRqlFF jzWRymsuD9b3s413s5frZeBuWCnrOKzFN+dYIUUl1BH/n1h0sn/fzVZpFrXWS/QNKZwBldhH6Cu zAhyA= X-Google-Smtp-Source: AGHT+IHvGRlUnca+L9ajzxTMQ3ZVV9sUWOvELGKMoU5iE6uqCQcPOCFhwS9U5tYCom0ODtsxVB3EIw== X-Received: by 2002:a17:907:6ea9:b0:ab7:1012:3ccb with SMTP id a640c23a62f3a-ac330181a8amr10857666b.14.1741902196696; Thu, 13 Mar 2025 14:43:16 -0700 (PDT) Received: from [192.168.178.107] (2001-1c06-2302-5600-7555-cca3-bbc4-648b.cable.dynamic.v6.ziggo.nl. [2001:1c06:2302:5600:7555:cca3:bbc4:648b]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac314a489e0sm126938866b.151.2025.03.13.14.43.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 14:43:16 -0700 (PDT) From: Bryan O'Donoghue Date: Thu, 13 Mar 2025 21:43:13 +0000 Subject: [PATCH v5 1/5] dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-1-846c9a6493a8@linaro.org> References: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org> In-Reply-To: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue , Vladimir Zapolskiy X-Mailer: b4 0.14.2 From: Vladimir Zapolskiy The switch to multiple power domains implies that the required-opps property shall be updated accordingly, a record in one property corresponds to a record in another one. Fixes: 7ec95ff9abf4 ("dt-bindings: clock: move qcom,x1e80100-camcc to its own file") Signed-off-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Signed-off-by: Bryan O'Donoghue --- Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml index 5bbbaa15a26090186e4ee4397ecba2f3c2541672..938a2f1ff3fca899b5708101df7f8aa07e943336 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml @@ -40,9 +40,9 @@ properties: - description: A phandle to the MMCX power-domain required-opps: - maxItems: 1 - description: - A phandle to an OPP node describing MMCX performance points. + items: + - description: A phandle to an OPP node describing MXC performance points + - description: A phandle to an OPP node describing MMCX performance points required: - compatible @@ -66,7 +66,8 @@ examples: <&sleep_clk>; power-domains = <&rpmhpd RPMHPD_MXC>, <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From patchwork Thu Mar 13 21:43:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 14015936 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91F111F55EB for ; Thu, 13 Mar 2025 21:43:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741902202; cv=none; b=RDM9bRhHaxsiX93Stjsjxw91e3/rR5VHEVt+ySxcpUHDE5Aw45pJxY77tPSgKCGVpRvbhX24BMP2yIEtrNcXnXwEQNUe3CEQsynmb+vKm0C3nwIPRTqUzUqEn/QVMw3seQv4rl2LRVGFoiOfWrhRy/lsJh5IXB+OcfL3KodV4Ws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741902202; c=relaxed/simple; bh=c+Qj4DKg1eJLbF7tyQrBCEXmEKREnLZPMNtUuVGeFP8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bB/7SHIzU/E1RMdb9aWyVEAaNsAx0VHt+SB8T09AGX1/txv593PdRdadiZrO+dziKDUKcBGKq6pufd2l35j+2BWJJ7ulKVOT2Xkxi0OOjsdcNScDzaFIOBtrKqbhwQe4/N34OD862OrKb3PfyNecDmlwovEBnz9FdHr/3pl1E6g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=W4g2Via5; arc=none smtp.client-ip=209.85.208.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="W4g2Via5" Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-5e6ff035e9aso2937566a12.0 for ; Thu, 13 Mar 2025 14:43:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741902198; x=1742506998; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=r4FtVmYZgckl7YtfkY/SWerCLj70ANs6HxOobmm+Pok=; b=W4g2Via5pOOLqhY9IMsy0/A3EPmMiuSkyZo1xeB1XOlJjzKpNlCEdpV2AkA33Q5jel 2AXHpvi+/+Q/B+A6l9weX+tjxCRossSIoKtnFfEHRe3jvRUWtR6aWSCdlBh3c4gQYTrH v9NJBMjZQlmPYSF0ToANF4vTDrNJj/74/EhVA+3PE3IEfEtlBhrfirWXg56H/xwb+rxK LwVdHU7fDeboibW+K6ofB603fzOf0a0hWSVh85Vx4Roy0ffZBn2ODYZuLOwwfhoW3ADY 49mOdRwmWeUzQde7ACexd+GSmXQ/UDZDo4sT/5Y1Cq6cGwHssOQrbha2FcdwyRW0REHE s/wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741902198; x=1742506998; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r4FtVmYZgckl7YtfkY/SWerCLj70ANs6HxOobmm+Pok=; b=VIcZ6O4t+WLcA7DwsXA2oHnmrg6OAuPan7dLLj14gXieYNzPTrrwvdn8HNNo4RI9zE oiF54xrkfJT/MWuOSCKIg8rN/ot3kaQlUVM4/JL8ZRfc91TZm6q4hNNV2oLfSElS2nOe b6GNMtBA5HsmO6jhMPSb7xWDBM8eiDeV+nCPpcxkOhl6koZhjeaE45WCdG4crOAcISRI w/BldmJnReRTEK0FhiRwgRkqe7Ldw0mNrlID5vUtnWyShr4TGz/hc7RWnGP+E9hzAEZk XHIw8Amv1qjwbmMmXoFg7sWsmnsk6n0rJaL2DcnY0JVTupJNHurLSL5gGc9UcRMFkX5o BacA== X-Forwarded-Encrypted: i=1; AJvYcCWdKTMNtxOaxJLYC0EIBFkiPTmw0DMF5q3B3YvJh9NjINsanJHTUDsk3o92ysKSD19pRZpOCWodD8Y=@vger.kernel.org X-Gm-Message-State: AOJu0Yy3oif3shTmRBYoVHXxGS3xsZzE+j9B39PmMKmRqvlydUZgYjGF LB7RsradEmtyHCafU1fTiJVnlJmYxwSLa1J3ruO6qR0DHZdngtznOTPbqAccQJM= X-Gm-Gg: ASbGncuAiyJAsfhhIIjrcyqExmFyiVGMgYPwuVdeLzueBmZ1ICIa8vo/A6xcY9eP+BJ GOHaYLe/UbWT1s2bkA42XkbKqzxD5+XI7DEGtQmIBiwOTU/ru96owN+awAGhYrMWX8e4UmkQTRZ pWpLL/7198ME9M0Qd9m6OcvSPBbMNS8nymkyR5nrqwiexA1bscIgYn3yzG5oKN6dp9cA02ZFrHv zqiiYNln9tCaVahTpA1OfHRHaMJDYDNiViMu1BTBXRpUPhTIVuy2wJzNl3NXgqyaRnpjHtJLthF 15/I9ZV9jjNKL+FX+RJy0ej7VVhzZNhOtQLWYsF83HzlUgUhcRS15MULUGMiWsn56m4AyhMNPVi uaaL6tBgpPL4ZLsbehfRilc0X21ePhLby0Zb/mXzqCXVC+iKGcP3faXepbPxddo0YwCu2 X-Google-Smtp-Source: AGHT+IG31Bns9+INvTorzGO/VBSn1BB5KJ1NQlQKRGr39RPhBs28xbw07ArB+XgHyNt78iLUfWBJWg== X-Received: by 2002:a17:907:7296:b0:abb:9d27:290b with SMTP id a640c23a62f3a-ac330108a28mr11919166b.9.1741902197774; Thu, 13 Mar 2025 14:43:17 -0700 (PDT) Received: from [192.168.178.107] (2001-1c06-2302-5600-7555-cca3-bbc4-648b.cable.dynamic.v6.ziggo.nl. [2001:1c06:2302:5600:7555:cca3:bbc4:648b]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac314a489e0sm126938866b.151.2025.03.13.14.43.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 14:43:17 -0700 (PDT) From: Bryan O'Donoghue Date: Thu, 13 Mar 2025 21:43:14 +0000 Subject: [PATCH v5 2/5] dt-bindings: media: Add qcom,x1e80100-camss Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-2-846c9a6493a8@linaro.org> References: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org> In-Reply-To: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue , Vladimir Zapolskiy X-Mailer: b4 0.14.2 Add bindings for qcom,x1e80100-camss in order to support the camera subsystem for x1e80100 as found in various Co-Pilot laptops. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue --- .../bindings/media/qcom,x1e80100-camss.yaml | 367 +++++++++++++++++++++ 1 file changed, 367 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml new file mode 100644 index 0000000000000000000000000000000000000000..113565cf2a991a8dcbc20889090e177e8bcadaac --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -0,0 +1,367 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,x1e80100-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 Camera Subsystem (CAMSS) + +maintainers: + - Bryan O'Donoghue + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,x1e80100-camss + + reg: + maxItems: 17 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_wrapper + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy4 + - const: csitpg0 + - const: csitpg1 + - const: csitpg2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 29 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: core_ahb + - const: cpas_ahb + - const: cpas_fast_ahb + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe_lite + - const: cphy_rx_clk_src + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy4 + - const: csiphy4_timer + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 13 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy4 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + - const: sf_icp_mnoc + + iommus: + maxItems: 8 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: top + + vdd-csiphy-0p8-supply: + description: + Phandle to a 0.8V regulator supply to a PHY. + + vdd-csiphy-1p2-supply: + description: + Phandle to 1.8V regulator supply to a PHY. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - vdd-csiphy-0p8-supply + - vdd-csiphy-1p2-supply + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: isp@acb6000 { + compatible = "qcom,x1e80100-camss"; + + reg = <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x1000>, + <0 0x0ace6000 0 0x1000>, + <0 0x0ace8000 0 0x1000>, + <0 0x0acec000 0 0x4000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0ac62000 0 0x4000>, + <0 0x0ac71000 0 0x4000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x1800 0x60>, + <&apps_smmu 0x1860 0x60>, + <&apps_smmu 0x18e0 0x00>, + <&apps_smmu 0x1980 0x20>, + <&apps_smmu 0x1900 0x00>, + <&apps_smmu 0x19a0 0x20>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + + power-domain-names = "ife0", + "ife1", + "top"; + + vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>; + vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + csiphy_ep0: endpoint { + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; From patchwork Thu Mar 13 21:43:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 14015937 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53BEA1F582F for ; Thu, 13 Mar 2025 21:43:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741902203; cv=none; b=YGdEFLiESS+wKzz0v/f/tLeiwWXZvEWRiCsobokHemcpuTlV1ZAWQ7uK0krS7e4E77VCNVD+Lfj0nBPCgoFO71Wxdx45rMGKUA4DrapiXkRXunBRmYUHuwXi6dPXQlOcAr3cLeDIayd1kAc1lFZq5/D1zdWAqLPVKYpp1QyOGqk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741902203; c=relaxed/simple; bh=CU+/XDQ60jyq3i9MimUs3kFmTV8jnj/R31j8nRU/h1U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Y/hU+zRqyminf+A2yWZY2avgOFo+XqOFpFA2uDMSzpRctz/TRNXEef6t6aFr8gAHphEoIH87+8n9fr7jHClrsf4SQ/6UF4W2WtmorOuRAdZkHTRZcc33DQVqmuS7b0NqufHqZ/22puAzk/Ir58YJgxq46Joq2k1sUv2hP/tGQQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=pbEhd9pM; arc=none smtp.client-ip=209.85.208.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="pbEhd9pM" Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-5e5e63162a0so2117328a12.3 for ; Thu, 13 Mar 2025 14:43:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741902199; x=1742506999; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3DObyF/iUzXjPpPEbY0w+cm8oMYW2eB7he9g871AEyE=; b=pbEhd9pM8ra3fKyT2RD25J71QAUmiOcCl1UN/Ih1RumGcG5o38g4d00Dwf//mJKKUZ J91FTzCrmIFKaQT6oR7WLFqylYQur3v32DyOT9RVk5rueH6RS7PKO2euBG81y6k2AShs c7150ofqLXOe8WPWZdu5wjeDVmefVZtMmxTZQ4D1TGHQ9wc5Q+IEtOy2iwKdJ5bSFmLR qwwONoOkPdjyBgN+wRidak4xPrgIF8OJDSJeTOiDhT2BXvxiHL6pYhJPn0oKeR93J2mT pn1bYYAV7A2T6oPw75HqWisbuhX4f4SyG9j7NdLUi5YEqxURd727OLYyx/Hy380sS0c3 Wf4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741902199; x=1742506999; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3DObyF/iUzXjPpPEbY0w+cm8oMYW2eB7he9g871AEyE=; b=ubQ5MPHH6qTJPEIQ5E4tBryvlvxmBj8J6ErXUeQhD1wOa+xjHRpDb1R/RhgTi2LMYe 5nBnXTfNAqE6TWR6FdLJkpoTJt7qdRZ9rq/puylkrr53BueQE+XhrVJb0rQyuLCM8z88 soFJze2ADvyygWPRIRQKGHbiiwFxCuuhkSBL/c3Zl5tRsYHyAYHfsS2sek+/E2JMoG1w xglf1bjwFSRHsfg9f2B8R6944ZvgJfnX+C+M054lQHdAGGAZKNsG38ovJD6CW3bYAX3L sSYeVBJyRhebLo2+I5acSSubPt/52uDzQf6JMQwYX6Ve7CnTrkPuPfrDAmneJg5Cp1w7 JqtA== X-Forwarded-Encrypted: i=1; AJvYcCWwPahIc68a9cPcmKFOUq4V16r5UwAdLGkN4IBg3hH6MBvI8eZSM9hCGcLp6Y0e4WeLff7ZpsN4Fq8=@vger.kernel.org X-Gm-Message-State: AOJu0Yx23hk5KNptHMHUecbRotZYUlkvZarnVsP27ZWGhRC3dk4OHaBc mI4xP6TxZt2g2ufAr0Z4FOKtP/oLbczPuRrK56JOx2SBOWkCBiupWe1NV0xee8M= X-Gm-Gg: ASbGncs8B7UQslsVSFFWqofkOvUFNrKD0dTwU5UWK9TZEIiTGYi1/lw+YNV0CgtFVhJ Z9ZsQY/IGJN88Msajr6uiEJDMzZXEciGp2rRB2aQC4Vy8t0KDH2NVSpVQSLFf3dwVPwRXmct7iR Uh0pZIgc/eN7iciisebYDpW+e37IN1npm6DHJO5fnkOWd+/GpTyiknv1ktqnDo5DLkifiWbXXOY Mp9RFKp4Mf4PYQsimNKJNDm5hsWTprocc6yl8r4CDn3lWZvUkcnA+PhuEPjamCrePIEigGy4rV+ RrPd3o8ThbRDNMTKIr1s17vaBdcJsBkDnoY1riAv8VRv1IJhqlyl0ARvBs6Aya34UmrNRwqOyth aCjA0BrhPJc9AuNZpDz6hiaGKmzhGOWugmAyWF1s5KY4HwjVmXh29N2R3q+TxIr4/xdKOqJ54+3 hcEAs= X-Google-Smtp-Source: AGHT+IGqp9Nz1XfOSp4Qxd087skZCs2Rbdil1yKkGG8XXXQucMNRahCo9RWdRZoOFBRNF3FMGjSfAw== X-Received: by 2002:a17:907:7241:b0:ac2:892f:43b with SMTP id a640c23a62f3a-ac330376b95mr10613866b.36.1741902199562; Thu, 13 Mar 2025 14:43:19 -0700 (PDT) Received: from [192.168.178.107] (2001-1c06-2302-5600-7555-cca3-bbc4-648b.cable.dynamic.v6.ziggo.nl. [2001:1c06:2302:5600:7555:cca3:bbc4:648b]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac314a489e0sm126938866b.151.2025.03.13.14.43.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 14:43:18 -0700 (PDT) From: Bryan O'Donoghue Date: Thu, 13 Mar 2025 21:43:15 +0000 Subject: [PATCH v5 3/5] arm64: dts: qcom: x1e80100: Add CAMCC block definition Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-3-846c9a6493a8@linaro.org> References: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org> In-Reply-To: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue , Vladimir Zapolskiy , Konrad Dybcio X-Mailer: b4 0.14.2 Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration of previous CAMCC blocks with the exception of having two required power-domains not just one. Reviewed-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 46b79fce92c90d969e3de48bc88e27915d1592bb..065a219e69c632eca288c9ade001949e37b92173 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -5116,6 +5117,22 @@ usb_1_ss1_dwc3_ss: endpoint { }; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,x1e80100-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,x1e80100-mdss"; reg = <0 0x0ae00000 0 0x1000>; From patchwork Thu Mar 13 21:43:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 14015938 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75D211F7075 for ; Thu, 13 Mar 2025 21:43:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741902204; cv=none; b=sOtfsxIIfSbw8OajIZPCtx4z7DPiLCtGPpN2h5o1IX+zycDKtUnrYlmn4X5mGbUwl8sbclFwV/jw6jy1XxvlFWMLvKETjkJO/S7tUuRObeDz3UK0sU4nw8Pl1euWxB15yNRc7ShLh+PjZxSDpo+ElFxNtD1ubIlJuZTPLVHYXDo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741902204; c=relaxed/simple; bh=a3wrzpVCaYNuMwQuNJHx7mKyoFe02+zkw63lLomddaA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RcMvi52yWOQCt+oPgmVmAAP9v3hzn1aIuYpLmOqaRkDqc4ptnwgRfz5j9vcMzFPCHXelyFxsG9BOiCjo/sdg9GvO4NBbitTsfk+Iznrys3mhZDlQ3oWg4jSbCoghkeXuTqwWx/9n4Jm6gQ5Ru6t5C1Z3rhkwxD7kvXgV2ZiGgj0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=tJamV0ca; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="tJamV0ca" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-abbb12bea54so275480166b.0 for ; Thu, 13 Mar 2025 14:43:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741902201; x=1742507001; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qZMmcHfeB4rBHuWqkNhUsUagbSg6bNeQKDj5E5I8kNM=; b=tJamV0caOKAODX9elPyfz2762PepQmOA4jbp8A54lFjSBTVt2Xou5vNiwkLCI6hfnH 1SB7mG3JjSRP0A77cF05jv8EfIVuWsqK7ukUpny6Re8Fgv3ShReQQkXNObLWfAzxbex2 JZLR4j0mWicYX7QZMIOEXouEgyVdhwNPlLbF/MkEVp7SAA4MnKAObExbymNkCFvOSstV u49hePDOSN3PSgXCbSC+V6RtTvH/hevhURgs8TjjjK5bVCg2KEgb552DJHCATB1XMGjf uURrvc3yMm3FCJQl3FzSXkRvTppAdkh+V+RfuxnIN8Gv8EjhvIi+EMpnjTEGg9Au1TGu 1XVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741902201; x=1742507001; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qZMmcHfeB4rBHuWqkNhUsUagbSg6bNeQKDj5E5I8kNM=; b=AE28aYBQQVHFFhDztmszOzL1PlV0yKaKh+D5wC3jFw/YxVvbjfyAnO3hjvyzwe6DSu CLnzEcVKb5nu1ndlRPbMBNuD5Eyvwmb/yuvbBGDrevRvRfZaTca1QDV1ZdIljKoqO116 02la22b/rjKuHn9bgGoa1IK0ADPlocRgN81upkhWt4WxKg7CjIy/wlcP76zwXXooYHO3 P+LqzMzzpSFi2rWuQMEcUUng+eNgS2jcwZLV6C/s4aiZvO11aQNXPx2U0vOxWjoSKzKz VHPgsMPp7ibpvusPvT7elgVwNvU2yU4dePExqVtQLmw31tWYRoiiBPSxQ5dmQOGSf/4o bpbA== X-Forwarded-Encrypted: i=1; AJvYcCXPRZMM9DyKeVVc/w4JKgMzp9LANF75/Sap1ZX92BZgfOmH5urMjraMFf8/20kzGlHa0rB8owDPTT4=@vger.kernel.org X-Gm-Message-State: AOJu0YyVuRI6ECUsLnhE7uW3zL/vBUwuXS1/e44y2+/rNInZbx4tD3sz sacL7Qw1Fqe0dklcPg5J2wihiTw5SIMhncpBixshJRxq21ampNQ3vO5lrSFbb00= X-Gm-Gg: ASbGncvzr+R5u8I2ZEzZTAf2QA33RL8BstqrzkzUFrAuEeO+hm3Lt4DFUod8NULmhEz SmXkujMLjG48a43/zxKdEoumOWCVVccPjNyDQz66h5TE5xKl9AbCERjAItVLg3aX1Niimp7uHvb pW3xFFzCgQd/y0V/1rLDTLKaAU+YDBFadM51A760b4AcG9BFn59Yx+M1lVpXrx1XOVNsVC59mnT Rd5+tBBy4v09Qh2GEyrA5R2oAtC2JCt6iDe3W0eInM2qBZU/njrlz7O4gS9nPZ0ACt+rBx23yDg pFHloDeQsXqddlWw2ZVDzW+TVi2xnnxjzZOrDh228W/QutbqNCYlDgcpOsz8gXKe39rVa5L2AD+ VIAlB1Cz+kt6LVNoy9T06Isjja/9K7WfG7B7ZlT/Y8Yel19nebdIJatQJxH/5N6pXUFwt X-Google-Smtp-Source: AGHT+IEoowJuPUsYRRA5+TwZx73pPwDGjlSG75J2GAB4x1TkjB/AGGligwnBjapO7S/jscNp4DnL5w== X-Received: by 2002:a17:907:2d0f:b0:ac2:8a59:92f4 with SMTP id a640c23a62f3a-ac330408d5cmr8908566b.51.1741902200774; Thu, 13 Mar 2025 14:43:20 -0700 (PDT) Received: from [192.168.178.107] (2001-1c06-2302-5600-7555-cca3-bbc4-648b.cable.dynamic.v6.ziggo.nl. [2001:1c06:2302:5600:7555:cca3:bbc4:648b]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac314a489e0sm126938866b.151.2025.03.13.14.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 14:43:20 -0700 (PDT) From: Bryan O'Donoghue Date: Thu, 13 Mar 2025 21:43:16 +0000 Subject: [PATCH v5 4/5] arm64: dts: qcom: x1e80100: Add CCI definitions Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-4-846c9a6493a8@linaro.org> References: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org> In-Reply-To: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue , Konrad Dybcio , Vladimir Zapolskiy X-Mailer: b4 0.14.2 Add in two CCI busses. One bus has two CCI bus master pinouts: cci_i2c_sda0 = gpio101 cci_i2c_scl0 = gpio102 cci_i2c_sda1 = gpio103 cci_i2c_scl1 = gpio104 The second bus has two CCI bus master pinouts: cci_i2c_sda2 = gpio105 cci_i2c_scl2 = gpio106 aon_cci_i2c_sda3 = gpio235 aon_cci_i2c_scl3 = gpio236 Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 150 +++++++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 065a219e69c632eca288c9ade001949e37b92173..4ae0f67a634a982143df7aa933ec4de697f357a5 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5117,6 +5117,84 @@ usb_1_ss1_dwc3_ss: endpoint { }; }; + cci0: cci@ac15000 { + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac15000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci0_default>; + pinctrl-1 = <&cci0_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac16000 { + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac16000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,x1e80100-camcc"; reg = <0 0x0ade0000 0 0x20000>; @@ -5741,6 +5819,78 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 239>; wakeup-parent = <&pdc>; + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins = "gpio235","gpio236"; + function = "aon_cci"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins = "gpio235","gpio236"; + function = "aon_cci"; + drive-strength = <2>; + bias-pull-down; + }; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { /* SDA, SCL */ pins = "gpio0", "gpio1"; From patchwork Thu Mar 13 21:43:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 14015939 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EACF1F8692 for ; Thu, 13 Mar 2025 21:43:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741902206; cv=none; b=sCpE+VzNOYI4IZ2rUmswMHcvCgHSPku776wDMRnHs3UeXrBdpu/GV0QH7j6BO09GCgHTOd6Ur8ilWz+PFqvrii4Fn3SeTWWepQaOh2jUBupd0YWg2LC/OqDT4TGaJaDfx6I7Ut9OcNZiFvSRRQf7h0VrteaBUOU1+nF46TtmdYE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741902206; c=relaxed/simple; bh=3qEj3bbV+h7bw70W9Qu2rgKmNJSTX2xHpgR9W8Jm1k8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PPeo2EkGlfnGb2+1Gd/f7FhrV59+L6Qv1VqswoeOIMam6qpj6jk1b05FbDd+igh83Z2hLrnCH+pZA1qTp7lqAkHUf6sQXhxeCGD4jfizt4goeTwhV1SnvEO1hpHjNiWqMSg+1b8EmpjiMMS07I/OWQ6GEp/iHKJw4pn1Ix/EBCY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=pZrLZ7oe; arc=none smtp.client-ip=209.85.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="pZrLZ7oe" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-5e535e6739bso2199806a12.1 for ; Thu, 13 Mar 2025 14:43:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741902203; x=1742507003; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RP6R7UedA0jjAiOICwsvyjhC9KhOLijiSoq6VNfxblc=; b=pZrLZ7oeeFUGqiQDOTVodTlsnceWEqoODz00M2dar3HYnMDQW9MiijoFTYdaGrMqdd IKlWMViugK2frWeCD7UuMZUEaOGv5Qb0c/DrbiXC05xdiADTeJ8wdvoByFvUrel5CcA7 chG6Ec/SicdzwgNJNdM5cjQwb3f5aMRpZCOUP064CxCnijeSR6As13mg8wiA13MrY4DK ItnUXN8pWFIeNFZq72zX1IUDye0OJsyxI0VaIGfr1+QH+A3rkpuw3khtmRNIPdt42JPm 0JBrXPmix7RjkxsJ9iXZXzZ5oq3ICDrlM7OdKI/qf8ew0c9jvl+eUEqaQEj4O4YVrXLI lUKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741902203; x=1742507003; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RP6R7UedA0jjAiOICwsvyjhC9KhOLijiSoq6VNfxblc=; b=RygwnMgXSrQabPWGvmadUyobKVAfsOQ9wyLT5N6V2Ku1OjmNHxPePhL2O1fSwB/atf G5yQh4c3g7PMMaQWqNK9nHL8o1UxLXTysh8L5PIvtflBIKTwlr39/GQpD/5yqHVa7ZFp e/j7KZZJzXtOA/gOpxHORFJrCt/zybrQ3RbBkS2dvrARAbDFOIWddCSP2hnLOCOckTFP ESYmOqH+a6J0ALB/pvTCa9KYHhoeX2McRadZ+GrkXS2VPLp+iKHyF+lUbU6aXwiIqWc2 oht1FHzOvIGVeRNEuj96RxMrAMkeDBGPWFy2Qa7JbpYSK9ggjXQXb5nTbPjDvBcjF2wW /A4Q== X-Forwarded-Encrypted: i=1; AJvYcCWHy9GW4+eAP+NtgW83ke5NHpGdU8LufkrK1tD5PRnRG53PtiI6pgsoXyDSWk6c2zHszOYcFybl1Ng=@vger.kernel.org X-Gm-Message-State: AOJu0Ywj8xUwoOF3bVjTbztbKYfNAALvHsJ3sfz4WvTAYT+EN/uYARFm O0C1jFQ+OuQewlFTEjdgefqk10cqHll0kqZ4WokU75DbJiuIKb/VHUgOkezXyorqt6y734KyUmR YkIiBRw== X-Gm-Gg: ASbGncu4gvnxmqPsMf0aT2lcElfTP0U50VWkCf5jauku7lf0osbzPHUPGNNjYp/XrGL EOyi0on/SkpzjExoPkIPgNypSBwbfyHorVx62AYWUjS18ki6MQmKWNNwbyWaZvCK2dLMISNfau4 OF3A+w4VFabSMTbkrSemiWN73cqxCrOJq/Fu03LmjJgGywNe9h+d6ayhrKxyF55y54Z6Fm1Qswu 1VAKmstI+Ytf9ReEmbOqQuNMb2QkP8sn7aK/unMbxBciDobxpDRbmBq47UaFzbcrUqvRbQBlkOA XhFxrHxNg+x9TPCEQ12nQrZjDO+jxjyb6Xhs0iYuxIzVm0iop5LXku4hmRMCi72dntMfl9xQ32T X9LLzOKPiUDQRo2OwgcCNMX99Rdi42WH2KnQyaBaZunQnw9YOcPcMlRkgDcTEwNys+e4Y6fvtpF 3HH1M= X-Google-Smtp-Source: AGHT+IFYkpUpQ5BP9/tADncg2iE/HgpuKPzuNh/CyEJk9AwACJ2Z13I6RlW0QgpvZ68ZluXuowvTCw== X-Received: by 2002:a17:907:9281:b0:abf:49de:36de with SMTP id a640c23a62f3a-ac330108ae9mr12984666b.1.1741902202588; Thu, 13 Mar 2025 14:43:22 -0700 (PDT) Received: from [192.168.178.107] (2001-1c06-2302-5600-7555-cca3-bbc4-648b.cable.dynamic.v6.ziggo.nl. [2001:1c06:2302:5600:7555:cca3:bbc4:648b]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac314a489e0sm126938866b.151.2025.03.13.14.43.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 14:43:21 -0700 (PDT) From: Bryan O'Donoghue Date: Thu, 13 Mar 2025 21:43:17 +0000 Subject: [PATCH v5 5/5] arm64: dts: qcom: x1e80100: Add CAMSS block definition Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-5-846c9a6493a8@linaro.org> References: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org> In-Reply-To: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue , Konrad Dybcio , Vladimir Zapolskiy X-Mailer: b4 0.14.2 Add dtsi to describe the xe180100 CAMSS block 4 x CSIPHY 2 x CSID 2 x CSID Lite 2 x IFE 2 x IFE Lite Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 185 +++++++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 4ae0f67a634a982143df7aa933ec4de697f357a5..ee78c630e2a1c38643c9222a6d6fff4cc1216a47 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5195,6 +5195,191 @@ cci1_i2c1: i2c-bus@1 { }; }; + camss: isp@acb6000 { + compatible = "qcom,x1e80100-camss"; + + reg = <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0ace8000 0 0x2000>, + <0 0x0acec000 0 0x2000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0ac62000 0 0x4000>, + <0 0x0ac71000 0 0x4000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x1800 0x60>, + <&apps_smmu 0x1860 0x60>, + <&apps_smmu 0x18e0 0x00>, + <&apps_smmu 0x1900 0x00>, + <&apps_smmu 0x1980 0x20>, + <&apps_smmu 0x19a0 0x20>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,x1e80100-camcc"; reg = <0 0x0ade0000 0 0x20000>;